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ARM: dts: brcmstb: un-hexify clock frequency

PATCH New Brian Norris 3 participants 5 messages Mar 19, 2015 Device tree bindings

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#0 lore raw

PATCH 1/2 ARM: dts: brcmstb: un-hexify clock frequency

This value makes much more sense in decimal.

---
 arch/arm/boot/dts/bcm7445.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/boot/dts/bcm7445.dtsi +1 -1
index 0ca0f4e523d0..b183dc99111a 100644
@@ -76,7 +76,7 @@
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-			clock-frequency = <0x4d3f640>;
+			clock-frequency = <81000000>;
 		};
 
 		sun_top_ctrl: syscon at 404000 {
Signature · 1 line
1.9.1
#1 lore raw

PATCH 2/2 ARM: dts: brcmstb: add IRQ0 controller

This L2 controller handles multiplexing a few different interrupts. We also need it for configuring the interrupt forwarding masks for the UART.

With this, we can *now* boot BCM7445 to a prompt using the upstream kernel + DTB.

---
 arch/arm/boot/dts/bcm7445.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)
arch/arm/boot/dts/bcm7445.dtsi +12 -0
index b183dc99111a..9eaeac8dce1b 100644
@@ -96,6 +96,18 @@
 				     "syscon";
 			reg = <0x452000 0x100>;
 		};
+
+		irq0_intc: interrupt-controller at f040a780 {
+			compatible = "brcm,bcm7120-l2-intc";
+			interrupt-parent = <&gic>;
+			#interrupt-cells = <1>;
+			reg = <0x40a780 0x8>;
+			interrupt-controller;
+			interrupts = <GIC_SPI 0x45 0x0>,
+				     <GIC_SPI 0x43 0x0>;
+			brcm,int-map-mask = <0x25c>, <0x7000000>;
+			brcm,int-fwd-mask = <0x70000>;
+		};
 	};
 
 	smpboot {
Signature · 1 line
1.9.1
#2 lore raw

PATCH 2/2 ARM: dts: brcmstb: add IRQ0 controller

Quoted 8 lines · Brian Norris

This L2 controller handles multiplexing a few different interrupts. We also need it for configuring the interrupt forwarding masks for the UART.

With this, we can *now* boot BCM7445 to a prompt using the upstream kernel + DTB.

Applied to devicetree/next, thanks!

Signature · 1 line
Florian