CHV PM fix & Improvements
Subsystems (2)
v2 cover CHV PM fix & Improvements
From: Deepak S <[email protected]>
Adding few of PM fixes and Improvements for CHV/VLV. Addressed few comments.
Deepak S (4):
drm/i915/chv: Remove Wait for a previous gfx force-off drm/i915: Re-adjusting rc6 promotional timer for chv drm/i915/chv: Set min freq to efficient frequency on chv drm/i915: Setup static bias for GPU
drivers/gpu/drm/i915/i915_drv.c | 6 ++++-- drivers/gpu/drm/i915/i915_reg.h | 5 +++++ drivers/gpu/drm/i915/intel_pm.c | 18 +++++++++++++++--- 3 files changed, 24 insertions(+), 5 deletions(-)
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1.9.1 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
PATCH v2 1/4 drm/i915/chv: Remove Wait for a previous gfx force-off
From: Deepak S <[email protected]>
On CHV, PUNIT team confirmed that 'VLV_GFX_CLK_STATUS_BIT' is not a sticky bit and it will always be set. So ignore Check for previous Gfx force off during suspend and allow the force clk as part S0ix Sequence
--- drivers/gpu/drm/i915/i915_drv.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
drivers/gpu/drm/i915/i915_drv.c +4 -2
@@ -1194,11 +1194,13 @@ int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)int err; val =I915_READ (VLV_GTLC_SURVIVABILITY_REG ); -WARN_ON (!!(val &VLV_GFX_CLK_FORCE_ON_BIT ) == force_on);#define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)/* Wait for a previous force-off to settle */ -if (force_on) { +if (force_on && !IS_CHERRYVIEW (dev_priv->dev)) { +/* WARN_ON only for the Valleyview */ +WARN_ON (!!(val &VLV_GFX_CLK_FORCE_ON_BIT ) == force_on); + err =wait_for (!COND ,20 );if (err) { DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",
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PATCH v2 2/4 drm/i915: Re-adjusting rc6 promotional timer for chv
In reply to [email protected]From: Deepak S <[email protected]>
After feedback from the hardware team we are changing the RC6 promotional timer to increase the power saving without changing performance.
--- drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/gpu/drm/i915/intel_pm.c +2 -2
@@ -4980,8 +4980,8 @@ static void cherryview_enable_rps(struct drm_device *dev)I915_WRITE (RING_MAX_IDLE (ring->mmio_base),10 );I915_WRITE (GEN6_RC_SLEEP ,0 ); -/* TO threshold set to 1750 us ( 0x557 * 1.28 us) */ -I915_WRITE (GEN6_RC6_THRESHOLD ,0x557 ); +/* TO threshold set to 500 us ( 0x186 * 1.28 us) */ +I915_WRITE (GEN6_RC6_THRESHOLD ,0x186 );/* allows RC6 residency counter to work */ I915_WRITE(VLV_COUNTER_CONTROL,
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1.9.1 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH v2 2/4] drm/i915: Re-adjusting rc6 promotional timer for chv
2015-03-19 11:14 GMT-03:00 <[email protected]>:
Quoted 5 lines
From: Deepak S <[email protected]>
After feedback from the hardware team we are changing the RC6 promotional timer to increase the power saving without changing performance.
I was told that my review comments were sent to the previous submission of this patch. So just to document things, this is what I wrote:
"I can't really say whether this is really what we want since I didn't do any measurements, but the patch seems to do what it says, so:
And Deepak replied that the measurements were done by the hardware team.
Since the patch is the same, the R-B tag still applies.
Quoted 28 lines
Signed-off-by Deepak S <[email protected]>--- drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)drivers/gpu/drm/i915/intel_pm.c +2
-3@@ -4980,8 +4980,8 @@ static void cherryview_enable_rps(struct drm_device *dev)I915_WRITE (RING_MAX_IDLE (ring->mmio_base),10 );I915_WRITE (GEN6_RC_SLEEP ,0 ); -/* TO threshold set to 1750 us ( 0x557 * 1.28 us) */ -I915_WRITE (GEN6_RC6_THRESHOLD ,0x557 ); +/* TO threshold set to 500 us ( 0x186 * 1.28 us) */ +I915_WRITE (GEN6_RC6_THRESHOLD ,0x186 );/* allows RC6 residency counter to work */ I915_WRITE(VLV_COUNTER_CONTROL, --1.9.1
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Paulo Zanoni _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH v2 2/4] drm/i915: Re-adjusting rc6 promotional timer for chv
Quoted 10 lines · Paulo Zanoni
2015-03-19 11:14 GMT-03:00 <[email protected]>:
Quoted 5 lines
From: Deepak S <[email protected]>
After feedback from the hardware team we are changing the RC6 promotional timer to increase the power saving without changing performance.
I was told that my review comments were sent to the previous submission of this patch. So just to document things, this is what I wrote:
Quoted 7 lines
"I can't really say whether this is really what we want since I didn't do any measurements, but the patch seems to do what it says, so:
Reviewed-by Paulo Zanoni <[email protected]>"And Deepak replied that the measurements were done by the hardware team.
Since the patch is the same, the R-B tag still applies.
Thanks Paulo.
Quoted 23 lines
Quoted 23 lines
Signed-off-by Deepak S <[email protected]>--- drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)drivers/gpu/drm/i915/intel_pm.c +2
-3@@ -4980,8 +4980,8 @@ static void cherryview_enable_rps(struct drm_device *dev)I915_WRITE (RING_MAX_IDLE (ring->mmio_base),10 );I915_WRITE (GEN6_RC_SLEEP ,0 ); -/* TO threshold set to 1750 us ( 0x557 * 1.28 us) */ -I915_WRITE (GEN6_RC6_THRESHOLD ,0x557 ); +/* TO threshold set to 500 us ( 0x186 * 1.28 us) */ +I915_WRITE (GEN6_RC6_THRESHOLD ,0x186 );/* allows RC6 residency counter to work */ I915_WRITE(VLV_COUNTER_CONTROL, --1.9.1
Quoted 6 lines
Quoted 4 lines
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PATCH v2 3/4 drm/i915/chv: Set min freq to efficient frequency on chv
In reply to [email protected]From: Deepak S <[email protected]>
After feedback from the hardware team, now we set the GPU min/idel freq to RPe. Punit is expecting us to operate GPU between Rpe & Rp0. If we drop the frequency to RPn, punit is failing to change the input voltage to minimum :(
v2: Change commit message
--- drivers/gpu/drm/i915/intel_pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/gpu/drm/i915/intel_pm.c +1 -1
@@ -4859,7 +4859,7 @@ static void valleyview_init_gt_powersave(struct drm_device *dev) dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;if (dev_priv->rps.min_freq_softlimit ==0 ) - dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; + dev_priv->rps.min_freq_softlimit = dev_priv->rps.efficient_freq;mutex_unlock (&dev_priv->rps.hw_lock); }
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1.9.1 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH v2 3/4] drm/i915/chv: Set min freq to efficient frequency on chv
2015-03-19 11:14 GMT-03:00 <[email protected]>:
Quoted 6 lines
From: Deepak S <[email protected]>
After feedback from the hardware team, now we set the GPU min/idel freq to RPe. Punit is expecting us to operate GPU between Rpe & Rp0. If we drop the frequency to RPn, punit is failing to change the input voltage to minimum :(
Since this is far away from the obvious, I am imagining some programmer from the future looking at this code and imagining min_freq_softlimit was "accidentally" set to RPe instead of RPn. Can't we add a comment in the code - not just the commit message -, to make it clear that we're doing this since the punit is weird?
Another thing which I noticed is that your patch title mentions CHV, but your patch touches the VLV function instead of the CHV one. This also leads me to think that maybe the power measurement experiments you did were done using the non-patched CHV code... Can you please clarify your intentions here? And also maybe redo the power measurements if needed.
Also, I think we need at least an ACK from Chris here, especially since he was already discussing the previous version of this patch.
Thanks,
Paulo
Quoted 28 lines
v2: Change commit message
Signed-off-by Deepak S <[email protected]>--- drivers/gpu/drm/i915/intel_pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)drivers/gpu/drm/i915/intel_pm.c +1
-2@@ -4859,7 +4859,7 @@ static void valleyview_init_gt_powersave(struct drm_device *dev) dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;if (dev_priv->rps.min_freq_softlimit ==0 ) - dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; + dev_priv->rps.min_freq_softlimit = dev_priv->rps.efficient_freq;mutex_unlock (&dev_priv->rps.hw_lock); } --1.9.1
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Paulo Zanoni _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Chris Wilson
Acked-byRe: [PATCH v2 3/4] drm/i915/chv: Set min freq to efficient frequency on chv
Quoted 21 lines · Paulo Zanoni
2015-03-19 11:14 GMT-03:00 <[email protected]>:
Quoted 6 lines
From: Deepak S <[email protected]>
After feedback from the hardware team, now we set the GPU min/idel freq to RPe. Punit is expecting us to operate GPU between Rpe & Rp0. If we drop the frequency to RPn, punit is failing to change the input voltage to minimum :(
Since this is far away from the obvious, I am imagining some programmer from the future looking at this code and imagining
min_freq_softlimitwas "accidentally" set to RPe instead of RPn. Can't we add a comment in the code - not just the commit message -, to make it clear that we're doing this since the punit is weird?Another thing which I noticed is that your patch title mentions CHV, but your patch touches the VLV function instead of the CHV one. This also leads me to think that maybe the power measurement experiments you did were done using the non-patched CHV code... Can you please clarify your intentions here? And also maybe redo the power measurements if needed.
Quoted 2 lines
Also, I think we need at least an ACK from Chris here, especially since he was already discussing the previous version of this patch.
If you include a comment like (and note we want to set dev_priv->rps.min_freq not dev_priv->rps.min_freq_softlimit):
/* PUnit validated range is only [RPe, RP0] */ dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
and make sure that is set before we derive dev_priv->rps.idle_freq.
You can have my
-Chris
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Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH v2 3/4] drm/i915/chv: Set min freq to efficient frequency on chv
Quoted 26 lines · Chris Wilson
Quoted 20 lines · Paulo Zanoni
2015-03-19 11:14 GMT-03:00 <[email protected]>:
Quoted 6 lines
From: Deepak S <[email protected]>
After feedback from the hardware team, now we set the GPU min/idel freq to RPe. Punit is expecting us to operate GPU between Rpe & Rp0. If we drop the frequency to RPn, punit is failing to change the input voltage to minimum :(
Since this is far away from the obvious, I am imagining some programmer from the future looking at this code and imagining
min_freq_softlimitwas "accidentally" set to RPe instead of RPn. Can't we add a comment in the code - not just the commit message -, to make it clear that we're doing this since the punit is weird?Another thing which I noticed is that your patch title mentions CHV, but your patch touches the VLV function instead of the CHV one. This also leads me to think that maybe the power measurement experiments you did were done using the non-patched CHV code... Can you please clarify your intentions here? And also maybe redo the power measurements if needed.
Quoted 2 lines
Also, I think we need at least an ACK from Chris here, especially since he was already discussing the previous version of this patch.
If you include a comment like (and note we want to set
dev_priv->rps.min_freqnotdev_priv->rps.min_freq_softlimit):
Quoted 8 lines
/* PUnit validated range is only [RPe, RP0] */
dev_priv->rps.min_freq=dev_priv->rps.efficient_freq;and make sure that is set before we derive
dev_priv->rps.idle_freq.You can have my
Acked-by Chris Wilson <[email protected]>-Chris
Thanks Chris. I will address comments & rebase the patch.
Quoted 1 line
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PATCH v2 4/4 drm/i915: Setup static bias for GPU
In reply to [email protected]From: Deepak S <[email protected]>
Based on the spec, Setting up static BIAS for GPU to improve the rps performace.
--- drivers/gpu/drm/i915/i915_reg.h | 5 +++++ drivers/gpu/drm/i915/intel_pm.c | 12 ++++++++++++ 2 files changed, 17 insertions(+)
drivers/gpu/drm/i915/i915_reg.h +5 -0
@@ -670,6 +670,11 @@ enum skl_disp_power_wells {#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27#define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 +#define VLV_IOSFB_RPS_OVERRIDE 0x04 +#define VLV_OVERRIDE_RPS_MASK 1 +#define VLV_ENABLE_BIAS_SHARE (1 << 1) +#define VLV_BIAS_VAL (6 << 2) +#define VLV_CZ_CLOCK_TO_MILLI_SEC 100000#define VLV_RP_UP_EI_THRESHOLD 90#define VLV_RP_DOWN_EI_THRESHOLD 70
drivers/gpu/drm/i915/intel_pm.c +12 -0
@@ -5016,6 +5016,12 @@ static void cherryview_enable_rps(struct drm_device *dev)GEN6_RP_UP_BUSY_AVG | GEN6_RP_DOWN_IDLE_AVG); +/* Setting Fixed Bias */ + val =VLV_OVERRIDE_RPS_MASK | +VLV_ENABLE_BIAS_SHARE | +VLV_BIAS_VAL ; +vlv_punit_write (dev_priv,VLV_IOSFB_RPS_OVERRIDE , val); + val =vlv_punit_read (dev_priv,PUNIT_REG_GPU_FREQ_STS );/* RPS code assumes GPLL is used */
@@ -5100,6 +5106,12 @@ static void valleyview_enable_rps(struct drm_device *dev)I915_WRITE (GEN6_RC_CONTROL , rc6_mode); +/* Setting Fixed Bias */ + val =VLV_OVERRIDE_RPS_MASK | +VLV_ENABLE_BIAS_SHARE | +VLV_BIAS_VAL ; +vlv_punit_write (dev_priv,VLV_IOSFB_RPS_OVERRIDE , val); + val =vlv_punit_read (dev_priv,PUNIT_REG_GPU_FREQ_STS );/* RPS code assumes GPLL is used */
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Re: [PATCH v2 4/4] drm/i915: Setup static bias for GPU
Task id: 6009 -------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV -1 272/272 271/272
ILK 301/301 301/301 SNB 303/303 303/303 IVB 342/342 342/342 BYT 287/287 287/287 HSW 362/362 362/362 BDW 308/308 308/308
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
PNV igt_gem_userptr_blits_minor-sync-interruptible DMESG_WARN(1)PASS(3) DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'
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