Implement CTL flush dummy bits

PATCH New Stephane Viau 1 participant 4 messages Mar 24, 2015

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Stephane Viau

author

2015-03-24 13:30 UTC #0 lore raw

cover Implement CTL flush dummy bits

This patchset proposes in a couple of changes (separate generated header) to remove the temporary defined symbols in the code and place them into the generated header file.

Stephane Viau (2):
drm/msm/mdp5: Update headers (add CTL flush bits) drm/msm/mdp5: Remove CTL flush dummy bits

 drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | 12 ++++++++++--
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 11 -----------
 2 files changed, 10 insertions(+), 13 deletions(-)

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The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

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Stephane Viau

author

2015-03-24 13:30 UTC #1 lore raw

PATCH 1/2 drm/msm/mdp5: Update headers (add CTL flush bits)

Some upcoming targets have more bits to set in CTL_FLUSH registers.

Example: msm8x16 needs to set TIMING1 bit so that some of the INTF1's interface registers get flushed.

Signed-off-by Stephane Viau <[email protected]>

---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h +10 -2

index b4e2624..b9a4ded 100644
@@ -8,9 +8,9 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git
 
 The rules-ng-ng source files this header was generated from are:
-- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp5.xml            (  28872 bytes, from 2015-03-09 12:40:51)
+- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp5.xml            (  29312 bytes, from 2015-03-23 21:18:48)
 - /local/mnt2/workspace2/sviau/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2014-06-02 18:31:15)
-- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp_common.xml      (   2357 bytes, from 2015-01-23 16:20:19)
+- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp_common.xml      (   2357 bytes, from 2015-03-23 20:38:49)
 
 Copyright (C) 2013-2015 by the following authors:
 - Rob Clark <[email protected]> (robclark)

@@ -458,11 +458,19 @@ static inline uint32_t REG_MDP5_CTL_FLUSH(uint32_t i0) { return 0x00000018 + __o
 #define MDP5_CTL_FLUSH_DSPP0					0x00002000
 #define MDP5_CTL_FLUSH_DSPP1					0x00004000
 #define MDP5_CTL_FLUSH_DSPP2					0x00008000
+#define MDP5_CTL_FLUSH_WB					0x00010000
 #define MDP5_CTL_FLUSH_CTL					0x00020000
 #define MDP5_CTL_FLUSH_VIG3					0x00040000
 #define MDP5_CTL_FLUSH_RGB3					0x00080000
 #define MDP5_CTL_FLUSH_LM5					0x00100000
 #define MDP5_CTL_FLUSH_DSPP3					0x00200000
+#define MDP5_CTL_FLUSH_CURSOR_0					0x00400000
+#define MDP5_CTL_FLUSH_CURSOR_1					0x00800000
+#define MDP5_CTL_FLUSH_CHROMADOWN_0				0x04000000
+#define MDP5_CTL_FLUSH_TIMING_3					0x10000000
+#define MDP5_CTL_FLUSH_TIMING_2					0x20000000
+#define MDP5_CTL_FLUSH_TIMING_1					0x40000000
+#define MDP5_CTL_FLUSH_TIMING_0					0x80000000
 
 static inline uint32_t REG_MDP5_CTL_START(uint32_t i0) { return 0x0000001c + __offset_CTL(i0); }

Signature · 8 lines

Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

_______________________________________________
dri-devel mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/dri-devel

Stephane Viau

author

2015-03-24 13:30 UTC #2 lore raw

PATCH 1/1 rnndb/mdp5: Add some CTL flush bits

Some upcoming targets have more bits to set in CTL_FLUSH registers.

Example: msm8x16 needs to set TIMING1 bit so that some of the INTF1's interface registers get flushed.

Signed-off-by Stephane Viau <[email protected]>

---
 rnndb/mdp/mdp5.xml | 8 ++++++++
 1 file changed, 8 insertions(+)

rnndb/mdp/mdp5.xml +8 -0

index 423249a..03dcc3a 100644
@@ -250,11 +250,19 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 			<bitfield name="DSPP0" pos="13" type="boolean"/>
 			<bitfield name="DSPP1" pos="14" type="boolean"/>
 			<bitfield name="DSPP2" pos="15" type="boolean"/>
+			<bitfield name="WB"   pos="16" type="boolean"/>
 			<bitfield name="CTL"   pos="17" type="boolean"/>
 			<bitfield name="VIG3" pos="18"  type="boolean"/>
 			<bitfield name="RGB3" pos="19"  type="boolean"/>
 			<bitfield name="LM5"  pos="20"  type="boolean"/>
 			<bitfield name="DSPP3" pos="21" type="boolean"/>
+			<bitfield name="CURSOR_0" pos="22" type="boolean"/>
+			<bitfield name="CURSOR_1" pos="23" type="boolean"/>
+			<bitfield name="CHROMADOWN_0" pos="26" type="boolean"/>
+			<bitfield name="TIMING_3" pos="28" type="boolean"/>
+			<bitfield name="TIMING_2" pos="29" type="boolean"/>
+			<bitfield name="TIMING_1" pos="30" type="boolean"/>
+			<bitfield name="TIMING_0" pos="31" type="boolean"/>
 		</reg32>
 		<reg32 offset="0x01C" name="START"/>
 		<reg32 offset="0x020" name="PACK_3D"/>

Signature · 3 lines

Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

Stephane Viau

author

2015-03-24 13:30 UTC #3 lore raw

PATCH 2/2 drm/msm/mdp5: Remove CTL flush dummy bits

In reply to Stephane Viau

This TODO can now be removed and replaced by the previous patch "drm/msm/mdp5: Update headers (add CTL flush bits)"

Signed-off-by Stephane Viau <[email protected]>

---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 11 -----------
 1 file changed, 11 deletions(-)

drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c +0 ~~-11~~

index 0fa7fce..5488b687 100644
@@ -316,13 +316,6 @@ int mdp5_ctl_blend(struct mdp5_ctl *ctl, u32 lm, u32 blend_cfg)
 
 u32 mdp_ctl_flush_mask_encoder(struct mdp5_interface *intf)
 {
-	/* these are dummy bits for now, but will appear in next chipsets: */
-#define MDP5_CTL_FLUSH_TIMING_0		0x80000000
-#define MDP5_CTL_FLUSH_TIMING_1		0x40000000
-#define MDP5_CTL_FLUSH_TIMING_2		0x20000000
-#define MDP5_CTL_FLUSH_TIMING_3		0x10000000
-#define MDP5_CTL_FLUSH_WB		0x00010000
-
 	if (intf->type == INTF_WB)
 		return MDP5_CTL_FLUSH_WB;

@@ -337,10 +330,6 @@ u32 mdp_ctl_flush_mask_encoder(struct mdp5_interface *intf)
 
 u32 mdp_ctl_flush_mask_cursor(int cursor_id)
 {
-	/* these are dummy bits for now, but will appear in next chipsets: */
-#define MDP5_CTL_FLUSH_CURSOR_0		0x00400000
-#define MDP5_CTL_FLUSH_CURSOR_1		0x00800000
-
 	switch (cursor_id) {
 	case 0: return MDP5_CTL_FLUSH_CURSOR_0;
 	case 1: return MDP5_CTL_FLUSH_CURSOR_1;

Signature · 8 lines

Qualcomm Innovation Center, Inc.

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

_______________________________________________
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[email protected]
http://lists.freedesktop.org/mailman/listinfo/dri-devel