sunxi: sun4i: add missing 912MHz clock divisors

PATCH New Iain Paton 3 participants 7 messages Mar 27, 2015 – Mar 28, 2015

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Arm (32-bit) Arm/Allwinner sunXi SoC support

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Iain Paton

author

2015-03-27 00:10 UTC #0 lore raw

PATCH 1/3 sunxi: sun4i: add missing 912MHz clock divisors

clock divisors table was missing an entry for 912MHz. The same table is used for sun7i where the default boot clock is 912MHz, resulting in A20 boards being overclocked to 960MHz

Signed-off-by Iain Paton <[email protected]>

---
 arch/arm/cpu/armv7/sunxi/clock_sun4i.c | 1 +
 1 file changed, 1 insertion(+)

arch/arm/cpu/armv7/sunxi/clock_sun4i.c +1 -0

index 49f4032..c720e96 100644
@@ -102,6 +102,7 @@ static struct {
 	/* This array must be ordered by frequency. */
 	{ PLL1_CFG(16, 0, 0, 0), 384000000 },
 	{ PLL1_CFG(16, 1, 0, 0), 768000000 },
+	{ PLL1_CFG(19, 1, 0, 0), 912000000 },
 	{ PLL1_CFG(20, 1, 0, 0), 960000000 },
 	{ PLL1_CFG(21, 1, 0, 0), 1008000000},
 	{ PLL1_CFG(22, 1, 0, 0), 1056000000},

Signature · 1 line

2.1.3

Iain Paton

author

2015-03-27 00:12 UTC #1 lore raw

PATCH 2/3 sunxi: promote CONFIG_CLK_FULL_SPEED to be selectable through Kconfig

in order to allow for this to be set differently per board, remove the define from the associated soc headers and allow the user to choose a value through a Kconfig setting

Signed-off-by Iain Paton <[email protected]>

---
 board/sunxi/Kconfig     | 8 ++++++++
 include/configs/sun4i.h | 1 -
 include/configs/sun5i.h | 1 -
 include/configs/sun6i.h | 1 -
 include/configs/sun7i.h | 1 -
 include/configs/sun8i.h | 1 -
 6 files changed, 8 insertions(+), 5 deletions(-)

board/sunxi/Kconfig +8 -0

index 9d0eb91..d0905a7 100644
@@ -33,6 +33,14 @@ config MACH_SUN8I
 
 endchoice
 
+config CLK_FULL_SPEED
+	int "sunxi cpu clock speed"
+	default 912000000 if MACH_SUN7I
+	default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
+	---help---
+	Set the cpu clock speed in Hz, valid values 384, 768, 912, 1008 MHz 
+	must be a multiple of 48MHz
+
 config DRAM_CLK
 	int "sunxi dram clock speed"
 	default 312 if MACH_SUN6I || MACH_SUN8I

include/configs/sun4i.h +0 -1

index 1537e53..7cd5c69 100644
@@ -11,7 +11,6 @@
 /*
  * A10 specific configuration
  */
-#define CONFIG_CLK_FULL_SPEED		1008000000
 
 #ifdef CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_SUNXI

include/configs/sun5i.h +0 -1

index e755531..e0470d4 100644
@@ -11,7 +11,6 @@
 /*
  * High Level Configuration Options
  */
-#define CONFIG_CLK_FULL_SPEED		1008000000
 
 #ifdef CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_SUNXI

include/configs/sun6i.h +0 -1

index f5e11dd..617c1cd 100644
@@ -14,7 +14,6 @@
 /*
  * A31 specific configuration
  */
-#define CONFIG_CLK_FULL_SPEED		1008000000
 
 #ifdef CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_SUNXI

include/configs/sun7i.h +0 -1

index f817f73..0bb756f 100644
@@ -12,7 +12,6 @@
 /*
  * A20 specific configuration
  */
-#define CONFIG_CLK_FULL_SPEED		912000000
 
 #ifdef CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_SUNXI

include/configs/sun8i.h +0 -1

index 3bdedb3..79796d7 100644
@@ -12,7 +12,6 @@
 /*
  * A23 specific configuration
  */
-#define CONFIG_CLK_FULL_SPEED	1008000000
 
 #ifdef CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_SUNXI

Signature · 1 line

2.1.3

Hans de Goede

2015-03-27 13:57 UTC #2 lore raw

PATCH 2/3 sunxi: promote CONFIG_CLK_FULL_SPEED to be selectable through Kconfig

Hi,

Quoted 5 lines · Iain Paton

in order to allow for this to be set differently per board, remove the define from the associated soc headers and allow the user to choose a value through a Kconfig setting
Signed-off-by Iain Paton <[email protected]>

Thanks, but if we're going to do this, then can you please rename CLK_FULL_SPEED to SYS_CLK_FREQ, as that is already defined in

./Kconfig

Change the "depends on ARC" in .Kconfig to "depends on ARC || ARCH_SUNXI", and add an entry for it to board/sunxi/Kconfig only setting a default, like we do for SYS_CONFIG_NAME / SYS_BOARD / SYS_SOC already

Regards,

Hans

Quoted 89 lines

---
  board/sunxi/Kconfig     | 8 ++++++++
  include/configs/sun4i.h | 1 -
  include/configs/sun5i.h | 1 -
  include/configs/sun6i.h | 1 -
  include/configs/sun7i.h | 1 -
  include/configs/sun8i.h | 1 -
  6 files changed, 8 insertions(+), 5 deletions(-)

board/sunxi/Kconfig +8 -0

index 9d0eb91..d0905a7 100644
@@ -33,6 +33,14 @@ config MACH_SUN8I
 
  endchoice
 
+config CLK_FULL_SPEED
+	int "sunxi cpu clock speed"
+	default 912000000 if MACH_SUN7I
+	default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
+	---help---
+	Set the cpu clock speed in Hz, valid values 384, 768, 912, 1008 MHz
+	must be a multiple of 48MHz
+
  config DRAM_CLK
  	int "sunxi dram clock speed"
  	default 312 if MACH_SUN6I || MACH_SUN8I

include/configs/sun4i.h +0 -1

index 1537e53..7cd5c69 100644
@@ -11,7 +11,6 @@
  /*
   * A10 specific configuration
   */
-#define CONFIG_CLK_FULL_SPEED		1008000000
 
  #ifdef CONFIG_USB_EHCI
  #define CONFIG_USB_EHCI_SUNXI

include/configs/sun5i.h +0 -1

index e755531..e0470d4 100644
@@ -11,7 +11,6 @@
  /*
   * High Level Configuration Options
   */
-#define CONFIG_CLK_FULL_SPEED		1008000000
 
  #ifdef CONFIG_USB_EHCI
  #define CONFIG_USB_EHCI_SUNXI

include/configs/sun6i.h +0 -1

index f5e11dd..617c1cd 100644
@@ -14,7 +14,6 @@
  /*
   * A31 specific configuration
   */
-#define CONFIG_CLK_FULL_SPEED		1008000000
 
  #ifdef CONFIG_USB_EHCI
  #define CONFIG_USB_EHCI_SUNXI

include/configs/sun7i.h +0 -1

index f817f73..0bb756f 100644
@@ -12,7 +12,6 @@
  /*
   * A20 specific configuration
   */
-#define CONFIG_CLK_FULL_SPEED		912000000
 
  #ifdef CONFIG_USB_EHCI
  #define CONFIG_USB_EHCI_SUNXI

include/configs/sun8i.h +0 -1

index 3bdedb3..79796d7 100644
@@ -12,7 +12,6 @@
  /*
   * A23 specific configuration
   */
-#define CONFIG_CLK_FULL_SPEED	1008000000
 
  #ifdef CONFIG_USB_EHCI
  #define CONFIG_USB_EHCI_SUNXI

Iain Paton

author

2015-03-28 10:24 UTC #3 lore raw

PATCH 2/3 sunxi: promote CONFIG_CLK_FULL_SPEED to be selectable through Kconfig

Quoted 7 lines · Hans de Goede

Hi,
Quoted 4 lines · Iain Paton
in order to allow for this to be set differently per board, remove the define from the associated soc headers and allow the user to choose a value through a Kconfig setting

Quoted 6 lines

Quoted 1 line
Signed-off-by Iain Paton <[email protected]>
Thanks, but if we're going to do this, then can you please rename CLK_FULL_SPEED to SYS_CLK_FREQ, as that is already defined in
./Kconfig

Sure thing, I'd missed that there was already a suitable variable. Updated version on the way.

Rgds,
Iain

Iain Paton

author

2015-03-27 00:12 UTC #4 lore raw

PATCH 3/3 sunxi: a10-LIME set the cpu clock at boot to 912MHz

In reply to Iain Paton

following kernel patches to reduce the cpu clock to 912MHz due to reported instability at 1008MHz, select 912MHz as the boot speed for the a10-lime

Signed-off-by Iain Paton <[email protected]>

---
 configs/A10-OLinuXino-Lime_defconfig | 1 +
 1 file changed, 1 insertion(+)

configs/A10-OLinuXino-Lime_defconfig +1 -0

index 48a0705..d017e36 100644
@@ -7,3 +7,4 @@ CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=480
 CONFIG_DRAM_ZQ=123
 CONFIG_DRAM_EMR1=4
+CONFIG_CLK_FULL_SPEED=912000000

Signature · 1 line

2.1.3

Ian Campbell

2015-03-27 14:04 UTC #5 lore raw

PATCH 1/3 sunxi: sun4i: add missing 912MHz clock divisors

In reply to Iain Paton

Quoted 3 lines · Iain Paton

clock divisors table was missing an entry for 912MHz. The same table is used for sun7i where the default boot clock is 912MHz, resulting in A20 boards being overclocked to 960MHz

Apart from the missing entry, should it not be the case that we pick the highest frequency <= than the requested frequency, rather than the next available (potentially higher) frequency?

IOW I'd expect things to be underclocked@768MHz without this change, which would mean that clock_set_pll1 is buggy.

Ian.

Quoted 18 lines

Signed-off-by Iain Paton <[email protected]>

---
 arch/arm/cpu/armv7/sunxi/clock_sun4i.c | 1 +
 1 file changed, 1 insertion(+)

arch/arm/cpu/armv7/sunxi/clock_sun4i.c +1 -0

index 49f4032..c720e96 100644
@@ -102,6 +102,7 @@ static struct {
 	/* This array must be ordered by frequency. */
 	{ PLL1_CFG(16, 0, 0, 0), 384000000 },
 	{ PLL1_CFG(16, 1, 0, 0), 768000000 },
+	{ PLL1_CFG(19, 1, 0, 0), 912000000 },
 	{ PLL1_CFG(20, 1, 0, 0), 960000000 },
 	{ PLL1_CFG(21, 1, 0, 0), 1008000000},
 	{ PLL1_CFG(22, 1, 0, 0), 1056000000},

Iain Paton

author

2015-03-28 10:24 UTC #6 lore raw

PATCH 1/3 sunxi: sun4i: add missing 912MHz clock divisors

Quoted 11 lines · Ian Campbell

Quoted 3 lines · Iain Paton
clock divisors table was missing an entry for 912MHz. The same table is used for sun7i where the default boot clock is 912MHz, resulting in A20 boards being overclocked to 960MHz
Apart from the missing entry, should it not be the case that we pick the highest frequency <= than the requested frequency, rather than the next available (potentially higher) frequency?
IOW I'd expect things to be underclocked at 768MHz without this change, which would mean that clock_set_pll1 is buggy.

Perhaps, however the selection algorithm is so trivial that I have difficulty beleiving that picking next highest was anything other than deliberate and the intended outcome.

I'll send a revised version that changes it to next lowest.

Rgds,
Iain