pinctrl: intel: Add Intel Sunrisepoint pin controller and GPIO support
Subsystems (3)
Mika Westerberg
maintainerPATCH 1/1 pinctrl: intel: Add Intel Sunrisepoint pin controller and GPIO support
This driver supports pinctrl/GPIO hardware found on Intel Sunrisepoint (a Skylake PCH) providing users a pinctrl and GPIO interfaces (including GPIO interrupts).
The driver is split into core and platform parts so that the same core driver can be reused in other drivers for other Intel GPIO hardware that is based on the same host controller design.
--- drivers/pinctrl/intel/Kconfig | 17 + drivers/pinctrl/intel/Makefile | 2 + drivers/pinctrl/intel/pinctrl-intel.c | 1149 ++++++++++++++++++++++++++ drivers/pinctrl/intel/pinctrl-intel.h | 128 +++ drivers/pinctrl/intel/pinctrl-sunrisepoint.c | 336 ++++++++ 5 files changed, 1632 insertions(+) create mode 100644 drivers/pinctrl/intel/pinctrl-intel.c create mode 100644 drivers/pinctrl/intel/pinctrl-intel.h create mode 100644 drivers/pinctrl/intel/pinctrl-sunrisepoint.c
drivers/pinctrl/intel/Kconfig +17 -0
@@ -25,3 +25,20 @@ config PINCTRL_CHERRYVIEW help Cherryview/Braswell pinctrl driver provides an interface that allows configuring of SoC pins and using them as GPIOs. + +config PINCTRL_INTEL + tristate + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GPIOLIB + select GPIOLIB_IRQCHIP + +config PINCTRL_SUNRISEPOINT + tristate "Intel Sunrisepoint pinctrl and GPIO driver" + depends on ACPI + select PINCTRL_INTEL + help + Sunrisepoint is the PCH of Intel Skylake. This pinctrl driver + provides an interface that allows configuring of PCH pins and + using them as GPIOs.
drivers/pinctrl/intel/Makefile +2 -0
@@ -2,3 +2,5 @@ obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o obj-$(CONFIG_PINCTRL_CHERRYVIEW) += pinctrl-cherryview.o +obj-$(CONFIG_PINCTRL_INTEL) += pinctrl-intel.o +obj-$(CONFIG_PINCTRL_SUNRISEPOINT) += pinctrl-sunrisepoint.o
drivers/pinctrl/intel/pinctrl-intel.c new file +1149 -0
1,149 lines not on this page · raw message
drivers/pinctrl/intel/pinctrl-intel.h new file +128 -0
128 lines not on this page · raw message
drivers/pinctrl/intel/pinctrl-sunrisepoint.c new file +336 -0
336 lines not on this page · raw message
Signature · 1 line
2.1.4
Quoted 10 lines · Mika Westerberg
This driver supports pinctrl/GPIO hardware found on Intel Sunrisepoint (a Skylake PCH) providing users a pinctrl and GPIO interfaces (including GPIO interrupts).
The driver is split into core and platform parts so that the same core driver can be reused in other drivers for other Intel GPIO hardware that is based on the same host controller design.
Signed-off-by Mathias Nyman <[email protected]>Signed-off-by Mika Westerberg <[email protected]>
How could I possibly resist this gorgeous driver that just does everything right? Patch applied for 4.1.
drivers/pinctrl/intel/Kconfig config PINCTRL_CHERRYVIEW · line 35
Quoted 7 lines
drivers/pinctrl/intel/Kconfig +7
-0+config PINCTRL_INTEL + tristate + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GPIOLIB + select GPIOLIB_IRQCHIP
Is this opening a refactoring possibility sharing more code/infrastructure amongst the Intel drivers or just something that will be used for new SoCs going forward?
Yours,
Linus Walleij
Mika Westerberg
maintainerQuoted 11 lines · Linus Walleij
Quoted 8 lines · Mika Westerberg
This driver supports pinctrl/GPIO hardware found on Intel Sunrisepoint (a Skylake PCH) providing users a pinctrl and GPIO interfaces (including GPIO interrupts).
The driver is split into core and platform parts so that the same core driver can be reused in other drivers for other Intel GPIO hardware that is based on the same host controller design.
Quoted 5 lines
Quoted 2 lines
Signed-off-by Mathias Nyman <[email protected]>Signed-off-by Mika Westerberg <[email protected]>How could I possibly resist this gorgeous driver that just does everything right? Patch applied for 4.1.
Thanks!
Quoted 11 lines
drivers/pinctrl/intel/Kconfig config PINCTRL_CHERRYVIEW · line 35
Quoted 7 lines
drivers/pinctrl/intel/Kconfig +7
-0+config PINCTRL_INTEL + tristate + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GPIOLIB + select GPIOLIB_IRQCHIPIs this opening a refactoring possibility sharing more code/infrastructure amongst the Intel drivers or just something that will be used for new SoCs going forward?
We are going to use the same core for newer hardware as much as possible. Hopefully all new SoCs will have GPIO controller which is based on the same hardware design.
For the existing, unfortunately the hardware differentiates too much from Sunrisepoint that it does not make much sense to factor them to use this new core.
Quoted 7 lines · Mika Westerberg
We are going to use the same core for newer hardware as much as possible. Hopefully all new SoCs will have GPIO controller which is based on the same hardware design.
For the existing, unfortunately the hardware differentiates too much from Sunrisepoint that it does not make much sense to factor them to use this new core.
OK fine. I was going to enquire into the similarity of this embedded Intel HW IP to the old StrongARM, Xscale, and PXA or whatever other embedded Intel things that have been around for ages, sometimes IP is inherited in the strangest ways. Oh well I guess we might see if we look at the register maps a bit.
Yours,
Linus Walleij