Displayport compliance tests 4.2.2.7 and 4.2.2.8
Subsystems (2)
PATCH 1/1 Displayport compliance tests 4.2.2.7 and 4.2.2.8
Improve Displayport compliance support. These patches add support for the following tests in the Displayport Link CTS Core 1.2 rev1.1:
4.2.2.7: Branch Device Detection upon HPD Plug Event 4.2.2.8: EDID read on IRQ_HPD event after Branch Device detection
The patches require the initial Displayport compliance patch set in order to operate correctly.
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PATCH 1/2 drm/i915: Add support for Displayport compliance test 4.2.2.7
Adds support for complying with the requirements for test 4.2.2.7 Branch Device Detection upon HPD Plug Event in the Displayport Link CTS 1.2 Core rev1.1. This test checks to see if the source device can properly detect a downstream branch device connected to the attached sink. It does so by advertising the presence of a downstream port through the DPCD. The sink count and content protection readiness bits are saved in the intel_dp struct.
Note that as of HDCP 1.3 Displayport amendment, the CP_READY bit (bit 6) in the SINK_COUNT register (DPCD 0x200) is no longer used. This bit is stored here for compatibility for pre-HDCP 1.3 devices.
--- drivers/gpu/drm/i915/intel_dp.c | 14 +++++++++++++- drivers/gpu/drm/i915/intel_drv.h | 4 ++++ 2 files changed, 17 insertions(+), 1 deletion(-)
drivers/gpu/drm/i915/intel_dp.c +13 -1
@@ -3633,8 +3633,20 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) intel_dp->use_tps3 = false;if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT ] & -DP_DWN_STRM_PORT_PRESENT )) +DP_DWN_STRM_PORT_PRESENT )) {return true;/* native DP sink */ + } +else { +uint8_t dpcd_byte; +/* Read Sink Count - DP Link CTS 1.2a rev1.1 4.2.2.7 */ +intel_dp_dpcd_read_wake (&intel_dp->aux, +DP_SINK_COUNT , + &dpcd_byte, +1 ); + intel_dp->sink_count =DP_GET_SINK_COUNT (dpcd_byte); + intel_dp->cp_ready = (dpcd_byte &DP_SINK_CP_READY ) >>6 ; +DRM_DEBUG_DRIVER ("Sink count: %d CP: %02x\n" , intel_dp->sink_count, intel_dp->cp_ready); + }if (intel_dp->dpcd[DP_DPCD_REV ] ==0x10 )return true;/* no per-port downstream info */
drivers/gpu/drm/i915/intel_drv.h +4 -0
@@ -653,6 +653,10 @@ struct intel_dp {unsigned long compliance_test_data;bool compliance_testing_active;bool compliance_edid_invalid; + +/* Branch device support */ +uint8_t sink_count; +uint8_t cp_ready; };struct intel_digital_port {
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1.9.1 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
PATCH 2/2 drm/i915: Add support for Displayport compliance test 4.2.2.8
In reply to Todd PreviteAdds support for the test 4.2.2.8 EDID read on IRQ_HPD event after Branch Device Detection in the Displayport Link CTS Core 1.2 rev1.1. This test checks to see that the source device reads the EDID from the attached sink device upon detection of a downstream port. A short pulse is generated by the sink device to indicate a status change in the downstream ports to which the source device must respond by reading the EDID from the attached sink.
--- drivers/gpu/drm/i915/intel_dp.c | 8 ++++++++ 1 file changed, 8 insertions(+)
drivers/gpu/drm/i915/intel_dp.c +8 -0
@@ -4015,6 +4015,14 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)return ; } +/* Check for downstream port status changes +Displayport Link CTS 1.2a rev1.1 4.2.2.8 +*/ +if (link_status[2 ] &DP_DOWNSTREAM_PORT_STATUS_CHANGED ) { +/* Read EDID as required by 4.2.2.8 */ + edid_read =drm_get_edid (connector, adapter); + } +if (!drm_dp_channel_eq_ok (link_status, intel_dp->lane_count)) {DRM_DEBUG_KMS ("%s: channel EQ not ok, retraining\n" , intel_encoder->base.name);
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1.9.1 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx