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arc: AXS101 - enable data cache

PATCH New Alexey Brodkin 1 participant 3 messages Mar 31, 2015 – Apr 2, 2015 Synopsys ARC architecture

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Alexey Brodkin

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#0 lore raw

PATCH 1/1 arc: AXS101 - enable data cache

With recent changes in mother-board firmware DMA works properly with data cache enabled. So we enable data cache for the board in defconfig to gain significant improvement in performance.

Signed-off-by Alexey Brodkin <[email protected]>
---
 configs/axs101_defconfig | 1 -
 1 file changed, 1 deletion(-)
configs/axs101_defconfig +0 -1
index e5e1d87..f6ec1f1 100644
@@ -1,5 +1,4 @@
 CONFIG_ARC=y
-CONFIG_SYS_DCACHE_OFF=y
 CONFIG_ARC_CACHE_LINE_SHIFT=5
 CONFIG_TARGET_AXS101=y
 CONFIG_SYS_TEXT_BASE=0x81000000
Signature · 1 line
2.1.0
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#1 lore raw

PATCH 1/1 board: Switch Abilis TB-100 board to Driver Model for serial port

Signed-off-by Alexey Brodkin <[email protected]>
Cc Masahiro Yamada <[email protected]>
Cc Simon Glass <[email protected]>
---
 arch/arc/dts/Makefile         |  1 +
 arch/arc/dts/abilis_tb100.dts | 24 ++++++++++++++++++++++++
 configs/tb100_defconfig       |  5 +++++
 include/configs/tb100.h       |  6 +-----
 4 files changed, 31 insertions(+), 5 deletions(-)
 create mode 100644 arch/arc/dts/abilis_tb100.dts
arch/arc/dts/Makefile +1 -0
index a155311..5bc6f44 100644
@@ -1,4 +1,5 @@
 dtb-$(CONFIG_TARGET_ARCANGEL4) +=  arcangel4.dtb
+dtb-$(CONFIG_TARGET_TB100) +=  abilis_tb100.dtb
 
 targets += $(dtb-y)
arch/arc/dts/abilis_tb100.dts new file +24 -0
new file mode 100644
index 0000000..cf395c4
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2015 Synopsys, Inc. (www.synopsys.com)
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/dts-v1/;
+
+#include "skeleton.dtsi"
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		console = &uart0;
+	};
+
+	uart0: serial at ff100000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff100000 0x1000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+	};
+};
configs/tb100_defconfig +5 -0
index c964272..59f09d9 100644
@@ -1,5 +1,10 @@
 CONFIG_ARC=y
 CONFIG_ARC_CACHE_LINE_SHIFT=5
 CONFIG_TARGET_TB100=y
+CONFIG_DM=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEFAULT_DEVICE_TREE="abilis_tb100"
 CONFIG_SYS_TEXT_BASE=0x84000000
 CONFIG_SYS_CLK_FREQ=500000000
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
include/configs/tb100.h +1 -5
index 46df406..501449a 100644
@@ -35,14 +35,10 @@
 /*
  * UART configuration
  */
-#define CONFIG_CONS_INDEX		1
+#define CONFIG_DW_SERIAL
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	-4
 #define CONFIG_SYS_NS16550_CLK		166666666
-#define CONFIG_SYS_NS16550_COM1		0xFF100000
-#define CONFIG_SYS_NS16550_MEM32
-
 #define CONFIG_BAUDRATE			115200
 
 /*
Signature · 1 line
2.1.0
author
#2 lore raw

PATCH 1/1 arc: AXS101 - enable data cache

In reply to Alexey Brodkin
Quoted 3 lines · Alexey Brodkin

With recent changes in mother-board firmware DMA works properly with data cache enabled. So we enable data cache for the board in defconfig to gain significant improvement in performance.

Even though NAND controller seem to work fine now I discovered yet unknown problem with class 10 SD cards. If data cache is enabled I see error messages like "Invalid FAT entry". Once data cache is disabled I see very nice and clean reads:
--->8---
AXS# fatload mmc 0 0x83000000 uimage
reading uimage
7354948 bytes read in 315 ms (22.3 MiB/s)
--->8---

So before enabling data cache on AXS101 I'll need to fix this issue with SD-cards. Deferring this patch for now.

-Alexey