arc: add support for SLC (System Level Cache, AKA L2-cache)

ARCv2 cores may have built-in SLC (System Level Cache, AKA L2-cache). This change adds functions required for controlling SLC:
* slc_enable/disable
* slc_flush/invalidate

For now we just disable SLC to escape DMA coherency issues until either:
* SLC flush/invalidate is supported in DMA APIin U-Boot
* hardware DMA coherency is implemented (that might be board specific so probably we'll need to have a separate Kconfig option for controlling SLC explicitly)

---
 arch/arc/include/asm/arcregs.h |  4 ++++
 arch/arc/include/asm/cache.h   | 11 ++++++++++
 arch/arc/lib/cache.c           | 46 ++++++++++++++++++++++++++++++++++++++++++
 arch/arc/lib/start.S           |  4 ++++
 4 files changed, 65 insertions(+)

index 6a36a81..0e11dcc 100644
@@ -46,6 +46,10 @@
 #define ARC_AUX_DC_PTAG		0x5C
 #endif
 #define ARC_BCR_DC_BUILD	0x72
+#define ARC_BCR_SLC		0xce
+#define ARC_AUX_SLC_CONTROL	0x903
+#define ARC_AUX_SLC_FLUSH	0x904
+#define ARC_AUX_SLC_INVALIDATE	0x905
 
 #ifndef __ASSEMBLY__
 /* Accessors for auxiliary registers */

index 8a77cd9..0b3ebd9 100644
@@ -27,4 +27,15 @@
 #define CONFIG_ARC_MMU_VER 4
 #endif
 
+#ifndef __ASSEMBLY__
+
+#ifdef CONFIG_ISA_ARCV2
+void slc_enable(void);
+void slc_disable(void);
+void slc_flush(void);
+void slc_invalidate(void);
+#endif
+
+#endif /* __ASSEMBLY__ */
+
 #endif /* __ASM_ARC_CACHE_H */

index 48ee86e..e1ef19c 100644
@@ -18,6 +18,10 @@ ENTRY(_start)
 	mov	%fp, %sp
 
 	/* Unconditionally disable caches */
+#ifdef CONFIG_ISA_ARCV2
+	bl	slc_flush
+	bl	slc_disable
+#endif
 	bl	flush_dcache_all
 	bl	dcache_disable
 	bl	icache_disable

2.1.0

Applied, thanks.

-Alexey