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drm/i915/chv: Implement WaDisableShadowRegForCpd

PATCH Superseded [email protected] 4 participants 14 messages Apr 14, 2015 – Apr 28, 2015

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#0 lore raw

PATCH 1/1 drm/i915/chv: Implement WaDisableShadowRegForCpd

From: Deepak S <[email protected]>

This WA disable usage of shadow register during CPD/RC6 transactions on CHV

Signed-off-by Deepak S <[email protected]>
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_pm.c | 4 ++++
 2 files changed, 5 insertions(+)
drivers/gpu/drm/i915/i915_reg.h +1 -0
index 9c97842..bcdb16b 100644
@@ -6206,6 +6206,7 @@ enum skl_disp_power_wells {
 #define  GTFIFOCTL				0x120008
 #define    GT_FIFO_FREE_ENTRIES_MASK		0x7f
 #define    GT_FIFO_NUM_RESERVED_ENTRIES		20
+#define GT_FIFO_CTL_BLOCK_POLICY	(3<<11)
 
 #define  HSW_IDICR				0x9008
 #define    IDIHASHMSK(x)			(((x) & 0x3f) << 16)
drivers/gpu/drm/i915/intel_pm.c +4 -0
index 4dd8b41..b9d3c00 100644
@@ -6431,6 +6431,10 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
 	/* WaDisableSDEUnitClockGating:chv */
 	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
 		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
+
+	/* WaDisableShadowRegForCpd */
+	I915_WRITE(GTFIFOCTL, I915_READ(GTFIFOCTL) |
+						  GT_FIFO_CTL_BLOCK_POLICY);
 }
 
 static void g4x_init_clock_gating(struct drm_device *dev)
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#1 lore raw
Quoted 4 lines · On Tue, Apr 14, 2015 at 03:58:54PM +0530, [email protected] wrote:

From: Deepak S <[email protected]>

This WA disable usage of shadow register during CPD/RC6 transactions on CHV

I suppose is a workaround for the shadow vs. wake FIFO problem... Yeah hsd seems to agree (after a bit of extra digging).

Quoted 12 lines
Signed-off-by Deepak S <[email protected]>
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_pm.c | 4 ++++
 2 files changed, 5 insertions(+)
drivers/gpu/drm/i915/i915_reg.h +0 -0
index 9c97842..bcdb16b 100644

drivers/gpu/drm/i915/i915_reg.h enum skl_disp_power_wells { · line 6209

Quoted 4 lines
drivers/gpu/drm/i915/i915_reg.h +1 -0
@@ -6206,6 +6206,7 @@ enum skl_disp_power_wells {
 #define  GTFIFOCTL				0x120008
 #define    GT_FIFO_FREE_ENTRIES_MASK		0x7f
 #define    GT_FIFO_NUM_RESERVED_ENTRIES		20
+#define GT_FIFO_CTL_BLOCK_POLICY	(3<<11)

GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12)
GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11)

perhaps?

Quoted 8 lines
drivers/gpu/drm/i915/i915_reg.h +0 -0
 #define  HSW_IDICR				0x9008
 #define    IDIHASHMSK(x)			(((x) & 0x3f) << 16)
drivers/gpu/drm/i915/intel_pm.c +0 -0
index 4dd8b41..b9d3c00 100644

drivers/gpu/drm/i915/intel_pm.c static void cherryview_init_clock_gating(struct drm_device *dev) · line 6437

Quoted 7 lines
drivers/gpu/drm/i915/intel_pm.c +4 -0
@@ -6431,6 +6431,10 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
 	/* WaDisableSDEUnitClockGating:chv */
 	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
 		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
+
+	/* WaDisableShadowRegForCpd */
+	I915_WRITE(GTFIFOCTL, I915_READ(GTFIFOCTL) |
+						  GT_FIFO_CTL_BLOCK_POLICY);

I think __intel_uncore_early_sanitize() might be a better place for this.

Quoted 5 lines
drivers/gpu/drm/i915/intel_pm.c +0 -0
 }
 
 static void g4x_init_clock_gating(struct drm_device *dev)
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Ville Syrjälä
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author
#2 lore raw
Quoted 7 lines · Ville Syrjälä
Quoted 4 lines · On Tue, Apr 14, 2015 at 03:58:54PM +0530, [email protected] wrote:

From: Deepak S <[email protected]>

This WA disable usage of shadow register during CPD/RC6 transactions on CHV

I suppose is a workaround for the shadow vs. wake FIFO problem... Yeah hsd seems to agree (after a bit of extra digging).

Yes ville, this WA is avoid problem between shadow vs wake FIFO unload problem. I will address the comments and send new patch set

Quoted 21 lines
Quoted 11 lines
Signed-off-by Deepak S <[email protected]>
---
  drivers/gpu/drm/i915/i915_reg.h | 1 +
  drivers/gpu/drm/i915/intel_pm.c | 4 ++++
  2 files changed, 5 insertions(+)
drivers/gpu/drm/i915/i915_reg.h +0 -0
index 9c97842..bcdb16b 100644

drivers/gpu/drm/i915/i915_reg.h enum skl_disp_power_wells { · line 6209

Quoted 4 lines
drivers/gpu/drm/i915/i915_reg.h +1 -0
@@ -6206,6 +6206,7 @@ enum skl_disp_power_wells {
  #define  GTFIFOCTL				0x120008
  #define    GT_FIFO_FREE_ENTRIES_MASK		0x7f
  #define    GT_FIFO_NUM_RESERVED_ENTRIES		20
+#define GT_FIFO_CTL_BLOCK_POLICY	(3<<11)

GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12)
GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11)

perhaps?

Quoted 1 line
Quoted 22 lines
Quoted 7 lines
  #define  HSW_IDICR				0x9008
  #define    IDIHASHMSK(x)			(((x) & 0x3f) << 16)
drivers/gpu/drm/i915/intel_pm.c +0 -0
index 4dd8b41..b9d3c00 100644

drivers/gpu/drm/i915/intel_pm.c static void cherryview_init_clock_gating(struct drm_device *dev) · line 6437

Quoted 7 lines
drivers/gpu/drm/i915/intel_pm.c +4 -0
@@ -6431,6 +6431,10 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
  	/* WaDisableSDEUnitClockGating:chv */
  	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
+
+	/* WaDisableShadowRegForCpd */
+	I915_WRITE(GTFIFOCTL, I915_READ(GTFIFOCTL) |
+						  GT_FIFO_CTL_BLOCK_POLICY);

I think __intel_uncore_early_sanitize() might be a better place for this.

Quoted 5 lines
drivers/gpu/drm/i915/intel_pm.c +0 -0
  }
 
  static void g4x_init_clock_gating(struct drm_device *dev)
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author
#3 lore raw

PATCH v2 1/1 drm/i915/chv: Implement WaDisableShadowRegForCpd

From: Deepak S <[email protected]>

This WA is avoid problem between shadow vs wake FIFO unload problem during CPD/RC6 transactions on CHV.

v2: Define individual bits GTFIFOCTL (Ville)

Signed-off-by Deepak S <[email protected]>
---
 drivers/gpu/drm/i915/i915_reg.h | 2 ++
 drivers/gpu/drm/i915/intel_pm.c | 5 +++++
 2 files changed, 7 insertions(+)
drivers/gpu/drm/i915/i915_reg.h +2 -0
index 9c97842..a642a58 100644
@@ -6206,6 +6206,8 @@ enum skl_disp_power_wells {
 #define  GTFIFOCTL				0x120008
 #define    GT_FIFO_FREE_ENTRIES_MASK		0x7f
 #define    GT_FIFO_NUM_RESERVED_ENTRIES		20
+#define	   GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL	(1 << 12)
+#define	   GT_FIFO_CTL_RC6_POLICY_STALL	(1 << 11)
 
 #define  HSW_IDICR				0x9008
 #define    IDIHASHMSK(x)			(((x) & 0x3f) << 16)
drivers/gpu/drm/i915/intel_pm.c +5 -0
index 4dd8b41..2b86915 100644
@@ -6431,6 +6431,11 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
 	/* WaDisableSDEUnitClockGating:chv */
 	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
 		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
+
+	/* WaDisableShadowRegForCpd */
+	I915_WRITE(GTFIFOCTL, I915_READ(GTFIFOCTL) |
+						  GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
+						  GT_FIFO_CTL_RC6_POLICY_STALL);
 }
 
 static void g4x_init_clock_gating(struct drm_device *dev)
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#4 lore raw
Quoted 31 lines · On Wed, Apr 15, 2015 at 02:16:18PM +0530, [email protected] wrote:

From: Deepak S <[email protected]>

This WA is avoid problem between shadow vs wake FIFO unload problem during CPD/RC6 transactions on CHV.

v2: Define individual bits GTFIFOCTL (Ville)

Signed-off-by Deepak S <[email protected]>
---
 drivers/gpu/drm/i915/i915_reg.h | 2 ++
 drivers/gpu/drm/i915/intel_pm.c | 5 +++++
 2 files changed, 7 insertions(+)
drivers/gpu/drm/i915/i915_reg.h +2 -0
index 9c97842..a642a58 100644
@@ -6206,6 +6206,8 @@ enum skl_disp_power_wells {
 #define  GTFIFOCTL				0x120008
 #define    GT_FIFO_FREE_ENTRIES_MASK		0x7f
 #define    GT_FIFO_NUM_RESERVED_ENTRIES		20
+#define	   GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL	(1 << 12)
+#define	   GT_FIFO_CTL_RC6_POLICY_STALL	(1 << 11)
 
 #define  HSW_IDICR				0x9008
 #define    IDIHASHMSK(x)			(((x) & 0x3f) << 16)
drivers/gpu/drm/i915/intel_pm.c +0 -0
index 4dd8b41..2b86915 100644

drivers/gpu/drm/i915/intel_pm.c static void cherryview_init_clock_gating(struct drm_device *dev) · line 6438

Quoted 8 lines
drivers/gpu/drm/i915/intel_pm.c +5 -0
@@ -6431,6 +6431,11 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
 	/* WaDisableSDEUnitClockGating:chv */
 	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
 		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
+
+	/* WaDisableShadowRegForCpd */
+	I915_WRITE(GTFIFOCTL, I915_READ(GTFIFOCTL) |
+						  GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
+						  GT_FIFO_CTL_RC6_POLICY_STALL);

uncore early sanitize would still seem like the better place for this.

Quoted 5 lines
drivers/gpu/drm/i915/intel_pm.c +0 -0
 }
 
 static void g4x_init_clock_gating(struct drm_device *dev)
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author
#5 lore raw
Quoted 25 lines · Ville Syrjälä
Quoted 24 lines · On Wed, Apr 15, 2015 at 02:16:18PM +0530, [email protected] wrote:

From: Deepak S <[email protected]>

This WA is avoid problem between shadow vs wake FIFO unload problem during CPD/RC6 transactions on CHV.

v2: Define individual bits GTFIFOCTL (Ville)

Signed-off-by Deepak S <[email protected]>
---
  drivers/gpu/drm/i915/i915_reg.h | 2 ++
  drivers/gpu/drm/i915/intel_pm.c | 5 +++++
  2 files changed, 7 insertions(+)
drivers/gpu/drm/i915/i915_reg.h +2 -0
index 9c97842..a642a58 100644
@@ -6206,6 +6206,8 @@ enum skl_disp_power_wells {
  #define  GTFIFOCTL				0x120008
  #define    GT_FIFO_FREE_ENTRIES_MASK		0x7f
  #define    GT_FIFO_NUM_RESERVED_ENTRIES		20
+#define	   GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL	(1 << 12)
+#define	   GT_FIFO_CTL_RC6_POLICY_STALL	(1 << 11)
Quoted 16 lines
Quoted 7 lines
drivers/gpu/drm/i915/i915_reg.h +0 -0
  #define  HSW_IDICR				0x9008
  #define    IDIHASHMSK(x)			(((x) & 0x3f) << 16)
drivers/gpu/drm/i915/intel_pm.c +0 -0
index 4dd8b41..2b86915 100644

drivers/gpu/drm/i915/intel_pm.c static void cherryview_init_clock_gating(struct drm_device *dev) · line 6438

Quoted 8 lines
drivers/gpu/drm/i915/intel_pm.c +5 -0
@@ -6431,6 +6431,11 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
  	/* WaDisableSDEUnitClockGating:chv */
  	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
+
+	/* WaDisableShadowRegForCpd */
+	I915_WRITE(GTFIFOCTL, I915_READ(GTFIFOCTL) |
+						  GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
+						  GT_FIFO_CTL_RC6_POLICY_STALL);

uncore early sanitize would still seem like the better place for this.

you mean intel_uncore_early_sanitize(). But func is called during early resume right? Since GTFIFOCTL will be saved and resorted by gunit. I think programming reg in cherryview_init_clock_gating should be good enough?

Quoted 5 lines
Quoted 5 lines
drivers/gpu/drm/i915/intel_pm.c +0 -0
  }
 
  static void g4x_init_clock_gating(struct drm_device *dev)
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author
#6 lore raw

PATCH v3 1/1 drm/i915/chv: Implement WaDisableShadowRegForCpd

From: Deepak S <[email protected]>

This WA is avoid problem between shadow vs wake FIFO unload problem during CPD/RC6 transactions on CHV.

v2: Define individual bits GTFIFOCTL (Ville)

v3: move WA to uncore_early_sanitize (ville)

Signed-off-by Deepak S <[email protected]>
---
 drivers/gpu/drm/i915/i915_reg.h     | 2 ++
 drivers/gpu/drm/i915/intel_uncore.c | 8 ++++++++
 2 files changed, 10 insertions(+)
drivers/gpu/drm/i915/i915_reg.h +2 -0
index 9c97842..a642a58 100644
@@ -6206,6 +6206,8 @@ enum skl_disp_power_wells {
 #define  GTFIFOCTL				0x120008
 #define    GT_FIFO_FREE_ENTRIES_MASK		0x7f
 #define    GT_FIFO_NUM_RESERVED_ENTRIES		20
+#define	   GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL	(1 << 12)
+#define	   GT_FIFO_CTL_RC6_POLICY_STALL	(1 << 11)
 
 #define  HSW_IDICR				0x9008
 #define    IDIHASHMSK(x)			(((x) & 0x3f) << 16)
drivers/gpu/drm/i915/intel_uncore.c +8 -0
index d96d15f..26d6dda 100644
@@ -360,6 +360,14 @@ static void __intel_uncore_early_sanitize(struct drm_device *dev,
 		__raw_i915_write32(dev_priv, GTFIFODBG,
 				   __raw_i915_read32(dev_priv, GTFIFODBG));
 
+	/* WaDisableShadowRegForCpd */
+	if (IS_CHERRYVIEW(dev)) {
+		__raw_i915_write32(dev_priv, GTFIFOCTL,
+				__raw_i915_read32(dev_priv, GTFIFOCTL) |
+						GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
+						GT_FIFO_CTL_RC6_POLICY_STALL);
+	}
+
 	intel_uncore_forcewake_reset(dev, restore_forcewake);
 }
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Reviewed-by on v3 1/1
#7 lore raw
Quoted 33 lines · On Wed, Apr 15, 2015 at 07:41:39PM +0530, [email protected] wrote:

From: Deepak S <[email protected]>

This WA is avoid problem between shadow vs wake FIFO unload problem during CPD/RC6 transactions on CHV.

v2: Define individual bits GTFIFOCTL (Ville)

v3: move WA to uncore_early_sanitize (ville)

Signed-off-by Deepak S <[email protected]>
---
 drivers/gpu/drm/i915/i915_reg.h     | 2 ++
 drivers/gpu/drm/i915/intel_uncore.c | 8 ++++++++
 2 files changed, 10 insertions(+)
drivers/gpu/drm/i915/i915_reg.h +2 -0
index 9c97842..a642a58 100644
@@ -6206,6 +6206,8 @@ enum skl_disp_power_wells {
 #define  GTFIFOCTL				0x120008
 #define    GT_FIFO_FREE_ENTRIES_MASK		0x7f
 #define    GT_FIFO_NUM_RESERVED_ENTRIES		20
+#define	   GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL	(1 << 12)
+#define	   GT_FIFO_CTL_RC6_POLICY_STALL	(1 << 11)
 
 #define  HSW_IDICR				0x9008
 #define    IDIHASHMSK(x)			(((x) & 0x3f) << 16)
drivers/gpu/drm/i915/intel_uncore.c +0 -0
index d96d15f..26d6dda 100644

drivers/gpu/drm/i915/intel_uncore.c static void __intel_uncore_early_sanitize(struct drm_device *dev, · line 363

Quoted 4 lines
drivers/gpu/drm/i915/intel_uncore.c +1 -0
@@ -360,6 +360,14 @@ static void __intel_uncore_early_sanitize(struct drm_device *dev,
 		__raw_i915_write32(dev_priv, GTFIFODBG,
 				   __raw_i915_read32(dev_priv, GTFIFODBG));
 
+	/* WaDisableShadowRegForCpd */

I couldn't find this w/a name anywhere official, but I guess it's fine. Should be WaDisableShadowRegForCpd:chv though. Otherwise looks good, so

Reviewed-by Ville Syrjälä <[email protected]>
Quoted 12 lines
drivers/gpu/drm/i915/intel_uncore.c +7 -0
+	if (IS_CHERRYVIEW(dev)) {
+		__raw_i915_write32(dev_priv, GTFIFOCTL,
+				__raw_i915_read32(dev_priv, GTFIFOCTL) |
+						GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
+						GT_FIFO_CTL_RC6_POLICY_STALL);
+	}
+
 	intel_uncore_forcewake_reset(dev, restore_forcewake);
 }
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author
#8 lore raw
Quoted 37 lines · Ville Syrjälä
Quoted 36 lines · On Wed, Apr 15, 2015 at 07:41:39PM +0530, [email protected] wrote:

From: Deepak S <[email protected]>

This WA is avoid problem between shadow vs wake FIFO unload problem during CPD/RC6 transactions on CHV.

v2: Define individual bits GTFIFOCTL (Ville)

v3: move WA to uncore_early_sanitize (ville)

Signed-off-by Deepak S <[email protected]>
---
  drivers/gpu/drm/i915/i915_reg.h     | 2 ++
  drivers/gpu/drm/i915/intel_uncore.c | 8 ++++++++
  2 files changed, 10 insertions(+)
drivers/gpu/drm/i915/i915_reg.h +2 -0
index 9c97842..a642a58 100644
@@ -6206,6 +6206,8 @@ enum skl_disp_power_wells {
  #define  GTFIFOCTL				0x120008
  #define    GT_FIFO_FREE_ENTRIES_MASK		0x7f
  #define    GT_FIFO_NUM_RESERVED_ENTRIES		20
+#define	   GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL	(1 << 12)
+#define	   GT_FIFO_CTL_RC6_POLICY_STALL	(1 << 11)
 
  #define  HSW_IDICR				0x9008
  #define    IDIHASHMSK(x)			(((x) & 0x3f) << 16)
drivers/gpu/drm/i915/intel_uncore.c +0 -0
index d96d15f..26d6dda 100644
@@ -360,6 +360,14 @@ static void __intel_uncore_early_sanitize(struct drm_device *dev,
  		__raw_i915_write32(dev_priv, GTFIFODBG,
  				   __raw_i915_read32(dev_priv, GTFIFODBG));
Quoted 5 lines

drivers/gpu/drm/i915/intel_uncore.c static void __intel_uncore_early_sanitize(struct drm_device *dev, · line 363

Quoted 1 line
drivers/gpu/drm/i915/intel_uncore.c +1 -0
+	/* WaDisableShadowRegForCpd */

I couldn't find this w/a name anywhere official, but I guess it's fine. Should be WaDisableShadowRegForCpd:chv though. Otherwise looks good, so

Reviewed-by Ville Syrjälä <[email protected]>

Thanks Ville for reviewing. I this the WA still not added to the chv list.

Quoted 10 lines
Quoted 10 lines
drivers/gpu/drm/i915/intel_uncore.c +7 -0
+	if (IS_CHERRYVIEW(dev)) {
+		__raw_i915_write32(dev_priv, GTFIFOCTL,
+				__raw_i915_read32(dev_priv, GTFIFOCTL) |
+						GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
+						GT_FIFO_CTL_RC6_POLICY_STALL);
+	}
+
  	intel_uncore_forcewake_reset(dev, restore_forcewake);
  }
Quoted 2 lines
Quoted 2 lines
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author
#9 lore raw

PATCH v4 1/1 drm/i915/chv: Implement WaDisableShadowRegForCpd

From: Deepak S <[email protected]>

This WA is avoid problem between shadow vs wake FIFO unload problem during CPD/RC6 transactions on CHV.

v2: Define individual bits GTFIFOCTL (Ville)

v3: move WA to uncore_early_sanitize (ville)

Signed-off-by Deepak S <[email protected]>
Reviewed-by Ville Syrjälä <[email protected]>
---
 drivers/gpu/drm/i915/i915_reg.h     | 2 ++
 drivers/gpu/drm/i915/intel_uncore.c | 8 ++++++++
 2 files changed, 10 insertions(+)
drivers/gpu/drm/i915/i915_reg.h +2 -0
index 9c97842..a642a58 100644
@@ -6206,6 +6206,8 @@ enum skl_disp_power_wells {
 #define  GTFIFOCTL				0x120008
 #define    GT_FIFO_FREE_ENTRIES_MASK		0x7f
 #define    GT_FIFO_NUM_RESERVED_ENTRIES		20
+#define	   GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL	(1 << 12)
+#define	   GT_FIFO_CTL_RC6_POLICY_STALL	(1 << 11)
 
 #define  HSW_IDICR				0x9008
 #define    IDIHASHMSK(x)			(((x) & 0x3f) << 16)
drivers/gpu/drm/i915/intel_uncore.c +8 -0
index d96d15f..d7cfd0c 100644
@@ -360,6 +360,14 @@ static void __intel_uncore_early_sanitize(struct drm_device *dev,
 		__raw_i915_write32(dev_priv, GTFIFODBG,
 				   __raw_i915_read32(dev_priv, GTFIFODBG));
 
+	/* WaDisableShadowRegForCpd:chv */
+	if (IS_CHERRYVIEW(dev)) {
+		__raw_i915_write32(dev_priv, GTFIFOCTL,
+				__raw_i915_read32(dev_priv, GTFIFOCTL) |
+						GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
+						GT_FIFO_CTL_RC6_POLICY_STALL);
+	}
+
 	intel_uncore_forcewake_reset(dev, restore_forcewake);
 }
Signature · 6 lines
1.9.1

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Tested-by on v4 1/1
#10 lore raw
Tested-by Intel Graphics QA PRTS (Patch Regression Test System Contact: [email protected])

Task id: 6210 -------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied

PNV                                  276/276              276/276
ILK                                  302/302              302/302
SNB                                  318/318              318/318
IVB                                  341/341              341/341
BYT                                  287/287              287/287

HSW -1 395/395 394/395
BDW 318/318 318/318
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*HSW igt@gem_pwrite_pread@uncached-copy-performance PASS(3) DMESG_WARN(1)PASS(1)
(dmesg patch applied)drm:i915_hangcheck_elapsed[i915]]*ERROR*Hangcheck_timer_elapsed...blitter_ring_idle@Hangcheck timer elapsed... blitter ring idle
Note: You need to pay more attention to line start with '*'
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maintainer Applied
#11 lore raw
In reply to [email protected]
Quoted 11 lines · On Thu, 16 Apr 2015, [email protected] wrote:

From: Deepak S <[email protected]>

This WA is avoid problem between shadow vs wake FIFO unload problem during CPD/RC6 transactions on CHV.

v2: Define individual bits GTFIFOCTL (Ville)

v3: move WA to uncore_early_sanitize (ville)

Signed-off-by Deepak S <[email protected]>
Reviewed-by Ville Syrjälä <[email protected]>

Pushed to drm-intel-fixes, thanks for the patch and review.

BR,
Jani.

Quoted 44 lines
---
 drivers/gpu/drm/i915/i915_reg.h     | 2 ++
 drivers/gpu/drm/i915/intel_uncore.c | 8 ++++++++
 2 files changed, 10 insertions(+)
drivers/gpu/drm/i915/i915_reg.h +2 -0
index 9c97842..a642a58 100644
@@ -6206,6 +6206,8 @@ enum skl_disp_power_wells {
 #define  GTFIFOCTL				0x120008
 #define    GT_FIFO_FREE_ENTRIES_MASK		0x7f
 #define    GT_FIFO_NUM_RESERVED_ENTRIES		20
+#define	   GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL	(1 << 12)
+#define	   GT_FIFO_CTL_RC6_POLICY_STALL	(1 << 11)
 
 #define  HSW_IDICR				0x9008
 #define    IDIHASHMSK(x)			(((x) & 0x3f) << 16)
drivers/gpu/drm/i915/intel_uncore.c +8 -0
index d96d15f..d7cfd0c 100644
@@ -360,6 +360,14 @@ static void __intel_uncore_early_sanitize(struct drm_device *dev,
 		__raw_i915_write32(dev_priv, GTFIFODBG,
 				   __raw_i915_read32(dev_priv, GTFIFODBG));
 
+	/* WaDisableShadowRegForCpd:chv */
+	if (IS_CHERRYVIEW(dev)) {
+		__raw_i915_write32(dev_priv, GTFIFOCTL,
+				__raw_i915_read32(dev_priv, GTFIFOCTL) |
+						GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
+						GT_FIFO_CTL_RC6_POLICY_STALL);
+	}
+
 	intel_uncore_forcewake_reset(dev, restore_forcewake);
 }
Signature · 6 lines
1.9.1

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Signature · 5 lines
Jani Nikula, Intel Open Source Technology Center
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Tested-by on v3 1/1
#12 lore raw
In reply to [email protected]
Tested-by Intel Graphics QA PRTS (Patch Regression Test System Contact: [email protected])

Task id: 6201 -------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 276/276 276/276
ILK -1 302/302 301/302

SNB                                  318/318              318/318
IVB                                  341/341              341/341
BYT                                  287/287              287/287

HSW -1 395/395 394/395
BDW 318/318 318/318
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*ILK igt@gem_fenced_exec_thrash@no-spare-fences-busy PASS(2) DMESG_WARN(1)PASS(1)
(dmesg patch applied)drm:i915_hangcheck_elapsed[i915]]*ERROR*Hangcheck_timer_elapsed...bsd_ring_idle@Hangcheck timer elapsed... bsd ring idle
*HSW igt@gem_pwrite_pread@snooped-pwrite-blt-cpu_mmap-performance PASS(5) DMESG_WARN(1)PASS(1)
(dmesg patch applied)drm:i915_hangcheck_elapsed[i915]]*ERROR*Hangcheck_timer_elapsed...blitter_ring_idle@Hangcheck timer elapsed... blitter ring idle
Note: You need to pay more attention to line start with '*'
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Tested-by on v2 1/1
#13 lore raw
In reply to [email protected]
Tested-by Intel Graphics QA PRTS (Patch Regression Test System Contact: [email protected])

Task id: 6196 -------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied

PNV                                  276/276              276/276
ILK                                  302/302              302/302
SNB                                  318/318              318/318
IVB                                  341/341              341/341
BYT                                  287/287              287/287

HSW -1 395/395 394/395
BDW 318/318 318/318
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*HSW igt@gem_pwrite_pread@snooped-copy-performance PASS(2) DMESG_WARN(1)PASS(1)
(dmesg patch applied)drm:i915_hangcheck_elapsed[i915]]*ERROR*Hangcheck_timer_elapsed...blitter_ring_idle@Hangcheck timer elapsed... blitter ring idle
Note: You need to pay more attention to line start with '*'
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