Add support for QCOM GDSCs
v5 cover Add support for QCOM GDSCs
GDSCs (Global Distributed Switch Controllers) control switches that supply power to an on-chip power domain and hence can be programmed in SW to safely power collapse and restore power to the respective PDs. They are part of a considerable number of recent QCOM SoCs (This series adds support for msm8974, msm8916 and apq8084 devices) and are part of the Clock control block.
The series implements support for GDSC using the genpd framework modelling these as SW controllable power domains and uses PM clocks to control clocks within the gdsc.
* Client drivers which plan to use GDSC can refer to Documentation/devicetree/bindings/power/power_domain.txt to know how to hook up the power domain for the device through DT
* Runtime PM specific documentation can be found in Documentation/power/runtime_pm.txt
* Patches are based of latest clk-next branch
Changes since v4:
* Added clock control support using PM clocks
* Included WA to enable an RCG (needed for Oxili gdsc in 8916)
Changes since v3:
* static inline'd gdsc_register/unregister stubs
* error check fixes in gdsc_register
* dropped oxili_gdsc for 8916 as its broken and needs additional WA's not part of this series
* split dts and driver changes into seperate patches
* Updated and included Stephanes patch to add gdscs to apq8084 mmcc in the series
Changes since v2:
* gdsc_unregister added
* gdsc_register/unregister introduced in patch 1/6
Changes since v1:
* added err checks for regmap apis
* added gdsc_register() in gdsc.c
Rajendra Nayak (7):
clk: qcom: gdsc: Prepare common clk probe to register gdscs
clk: qcom: gdsc: Add GDSCs in msm8916 GCC
clk: qcom: gdsc: Add GDSCs in apq8084 GCC
arm: dts: qcom: Add #power-domain-cells property
clk: qcom: gdsc: Use PM clocks to control gdsc clocks
clk: qcom: gdsc: Enable an RCG before turning on the gdsc
clk: qcom: gdsc: Add oxili GDSC for msm8916
Stephane Viau (1):
clk: qcom: gdsc: Add GDSCs in apq8084 MMCC
Stephen Boyd (3):
clk: qcom: Add support for GDSCs
clk: qcom: gdsc: Add GDSCs in msm8974 GCC
clk: qcom: gdsc: Add GDSCs in msm8974 MMCC
arch/arm/boot/dts/qcom-apq8084.dtsi | 1 + arch/arm/boot/dts/qcom-msm8974.dtsi | 2 + drivers/clk/qcom/Kconfig | 10 ++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/common.c | 16 +- drivers/clk/qcom/common.h | 2 + drivers/clk/qcom/gcc-apq8084.c | 38 +++++ drivers/clk/qcom/gcc-msm8916.c | 47 ++++++ drivers/clk/qcom/gcc-msm8974.c | 14 ++ drivers/clk/qcom/gdsc.c | 228 ++++++++++++++++++++++++++ drivers/clk/qcom/gdsc.h | 50 ++++++ drivers/clk/qcom/mmcc-apq8084.c | 56 ++++++- drivers/clk/qcom/mmcc-msm8974.c | 54 ++++++ include/dt-bindings/clock/qcom,gcc-apq8084.h | 6 + include/dt-bindings/clock/qcom,gcc-msm8916.h | 8 + include/dt-bindings/clock/qcom,gcc-msm8974.h | 3 + include/dt-bindings/clock/qcom,mmcc-apq8084.h | 8 + include/dt-bindings/clock/qcom,mmcc-msm8974.h | 8 + 18 files changed, 550 insertions(+), 2 deletions(-) create mode 100644 drivers/clk/qcom/gdsc.c create mode 100644 drivers/clk/qcom/gdsc.h
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PATCH v5 1/11 clk: qcom: Add support for GDSCs
From: Stephen Boyd <[email protected]>
GDSCs (Global Distributed Switch Controllers) are responsible for safely collapsing and restoring power to peripherals in the SoC. These are best modelled as power domains using genpd and given the registers are scattered throughout the clock controller register space, its best to have the support added through the clock driver.
--- drivers/clk/qcom/Kconfig | 5 ++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gdsc.c | 167 ++++++++++++++++++++++++++++++++++++++++++++++ drivers/clk/qcom/gdsc.h | 45 +++++++++++++ 4 files changed, 218 insertions(+) create mode 100644 drivers/clk/qcom/gdsc.c create mode 100644 drivers/clk/qcom/gdsc.h
drivers/clk/qcom/Kconfig +5 -0
@@ -39,6 +39,11 @@ config IPQ_LCC_806X Say Y if you want to use audio devices such as i2s, pcm, S/PDIF, etc. +config QCOM_GDSC + bool + select PM_GENERIC_DOMAINS if PM + depends on COMMON_CLK_QCOM + config MSM_GCC_8660 tristate "MSM8660 Global Clock Controller" depends on COMMON_CLK_QCOM
drivers/clk/qcom/Makefile +1 -0
@@ -9,6 +9,7 @@ clk-qcom-y += clk-branch.o clk-qcom-y += clk-regmap-divider.o clk-qcom-y += clk-regmap-mux.o clk-qcom-y += reset.o +clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
drivers/clk/qcom/gdsc.c new file +167 -0
167 lines not on this page · raw message
drivers/clk/qcom/gdsc.h new file +45 -0
45 lines not on this page · raw message
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v5 2/11 clk: qcom: gdsc: Prepare common clk probe to register gdscs
In reply to Rajendra NayakThe common clk probe registers a clk provider and a reset controller. Update it to register a genpd provider using the gdsc data provided by each platform.
--- drivers/clk/qcom/common.c | 16 +++++++++++++++- drivers/clk/qcom/common.h | 2 ++ 2 files changed, 17 insertions(+), 1 deletion(-)
drivers/clk/qcom/common.c +15 -1
@@ -21,6 +21,7 @@#include "clk-rcg.h" #include "clk-regmap.h" #include "reset.h" +#include "gdsc.h" struct qcom_cc {struct qcom_reset_controller reset;
@@ -120,8 +121,20 @@ int qcom_cc_really_probe(struct platform_device *pdev, ret =reset_controller_register (&reset->rcdev);if (ret) -of_clk_del_provider (dev->of_node); + goto err_reset; +if (desc->gdscs && desc->num_gdscs) { + ret =gdsc_register (dev, desc->gdscs, desc->num_gdscs, regmap); +if (ret) + goto err_pd; + } + +return 0 ; +err_pd: +dev_err (dev,"Failed to register power domains\n" ); +reset_controller_unregister (&reset->rcdev); +err_reset: +of_clk_del_provider (dev->of_node);return ret; }EXPORT_SYMBOL_GPL (qcom_cc_really_probe);
@@ -140,6 +153,7 @@ EXPORT_SYMBOL_GPL(qcom_cc_probe);void qcom_cc_remove (struct platform_device *pdev) { +gdsc_unregister (&pdev->dev);of_clk_del_provider (pdev->dev.of_node);reset_controller_unregister (platform_get_drvdata (pdev)); }
drivers/clk/qcom/common.h +2 -0
@@ -28,6 +28,8 @@ struct qcom_cc_desc {size_t num_clks;const struct qcom_reset_map *resets;size_t num_resets; +struct gdsc **gdscs; +size_t num_gdscs; }; extern const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f,
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v5 3/11 clk: qcom: gdsc: Add GDSCs in msm8916 GCC
In reply to Rajendra NayakAdd all data for the GDSCs which are part of msm8916 GCC block.
--- drivers/clk/qcom/Kconfig | 1 + drivers/clk/qcom/gcc-msm8916.c | 38 ++++++++++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-msm8916.h | 8 ++++++ 3 files changed, 47 insertions(+)
drivers/clk/qcom/Kconfig +1 -0
@@ -54,6 +54,7 @@ config MSM_GCC_8660 config MSM_GCC_8916 tristate "MSM8916 Global Clock Controller" + select QCOM_GDSC depends on COMMON_CLK_QCOM help Support for the global clock controller on msm8916 devices.
drivers/clk/qcom/gcc-msm8916.c +38 -0
@@ -31,6 +31,7 @@#include "clk-rcg.h" #include "clk-branch.h" #include "reset.h" +#include "gdsc.h" enum {P_XO ,
@@ -2562,6 +2563,34 @@ static struct clk_branch gcc_venus0_vcodec0_clk = { }, }; +static struct gdsc venus_gdsc = { + .gdscr =0x4c018 , + .pd = { + .name ="venus" , + }, +}; + +static struct gdsc mdss_gdsc = { + .gdscr =0x4d078 , + .pd = { + .name ="mdss" , + }, +}; + +static struct gdsc jpeg_gdsc = { + .gdscr =0x5701c , + .pd = { + .name ="jpeg" , + }, +}; + +static struct gdsc vfe_gdsc = { + .gdscr =0x58034 , + .pd = { + .name ="vfe" , + }, +}; +static struct clk_regmap *gcc_msm8916_clocks[] = { [GPLL0 ] = &gpll0.clkr, [GPLL0_VOTE ] = &gpll0_vote,
@@ -2703,6 +2732,13 @@ static struct clk_regmap *gcc_msm8916_clocks[] = { [GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr, }; +static struct gdsc *gcc_msm8916_gdscs[] = { + [VENUS_GDSC ] = &venus_gdsc, + [MDSS_GDSC ] = &mdss_gdsc, + [JPEG_GDSC ] = &jpeg_gdsc, + [VFE_GDSC ] = &vfe_gdsc, +}; +static const struct qcom_reset_map gcc_msm8916_resets[] = { [GCC_BLSP1_BCR ] = {0x01000 }, [GCC_BLSP1_QUP1_BCR ] = {0x02000 },
@@ -2810,6 +2846,8 @@ static const struct qcom_cc_desc gcc_msm8916_desc = { .num_clks = ARRAY_SIZE(gcc_msm8916_clocks), .resets = gcc_msm8916_resets, .num_resets = ARRAY_SIZE(gcc_msm8916_resets), + .gdscs = gcc_msm8916_gdscs, + .num_gdscs = ARRAY_SIZE(gcc_msm8916_gdscs), };static const struct of_device_id gcc_msm8916_match_table[] = {
include/dt-bindings/clock/qcom,gcc-msm8916.h +8 -0
@@ -153,4 +153,12 @@#define GCC_VENUS0_AXI_CLK 136#define GCC_VENUS0_VCODEC0_CLK 137 +/* Indexes for GDSCs */ +#define BIMC_GDSC 0 +#define VENUS_GDSC 1 +#define MDSS_GDSC 2 +#define JPEG_GDSC 3 +#define VFE_GDSC 4 +#define OXILI_GDSC 5 +#endif
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QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v5 4/11 clk: qcom: gdsc: Add GDSCs in msm8974 GCC
In reply to Rajendra NayakFrom: Stephen Boyd <[email protected]>
Theres just one GDSC as part of the msm8974 GCC block.
--- drivers/clk/qcom/Kconfig | 1 + drivers/clk/qcom/gcc-msm8974.c | 14 ++++++++++++++ include/dt-bindings/clock/qcom,gcc-msm8974.h | 3 +++ 3 files changed, 18 insertions(+)
drivers/clk/qcom/Kconfig +1 -0
@@ -89,6 +89,7 @@ config MSM_MMCC_8960 config MSM_GCC_8974 tristate "MSM8974 Global Clock Controller" + select QCOM_GDSC depends on COMMON_CLK_QCOM help Support for the global clock controller on msm8974 devices.
drivers/clk/qcom/gcc-msm8974.c +14 -0
@@ -31,6 +31,7 @@#include "clk-rcg.h" #include "clk-branch.h" #include "reset.h" +#include "gdsc.h" enum {P_XO ,
@@ -2431,6 +2432,13 @@ static struct clk_branch gcc_usb_hsic_system_clk = { }, }; +static struct gdsc usb_hs_hsic_gdsc = { + .gdscr =0x404 , + .pd = { + .name ="usb_hs_hsic" , + }, +}; +static struct clk_regmap *gcc_msm8974_clocks[] = { [GPLL0 ] = &gpll0.clkr, [GPLL0_VOTE ] = &gpll0_vote,
@@ -2660,6 +2668,10 @@ static const struct qcom_reset_map gcc_msm8974_resets[] = { [GCC_VENUS_RESTART] = { 0x1740 }, }; +static struct gdsc *gcc_msm8974_gdscs[] = { + [USB_HS_HSIC_GDSC ] = &usb_hs_hsic_gdsc, +}; +static const struct regmap_config gcc_msm8974_regmap_config = { .reg_bits =32 , .reg_stride =4 ,
@@ -2674,6 +2686,8 @@ static const struct qcom_cc_desc gcc_msm8974_desc = { .num_clks = ARRAY_SIZE(gcc_msm8974_clocks), .resets = gcc_msm8974_resets, .num_resets = ARRAY_SIZE(gcc_msm8974_resets), + .gdscs = gcc_msm8974_gdscs, + .num_gdscs = ARRAY_SIZE(gcc_msm8974_gdscs), };static const struct of_device_id gcc_msm8974_match_table[] = {
include/dt-bindings/clock/qcom,gcc-msm8974.h +3 -0
@@ -321,4 +321,7 @@#define GCC_SDCC1_CDCCAL_SLEEP_CLK 304#define GCC_SDCC1_CDCCAL_FF_CLK 305 +/* gdscs */ +#define USB_HS_HSIC_GDSC 0 +#endif
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v5 5/11 clk: qcom: gdsc: Add GDSCs in msm8974 MMCC
In reply to Rajendra NayakFrom: Stephen Boyd <[email protected]>
Add the GDSC instances that exist as part of msm8974 MMCC block
--- drivers/clk/qcom/Kconfig | 1 + drivers/clk/qcom/mmcc-msm8974.c | 54 +++++++++++++++++++++++++++ include/dt-bindings/clock/qcom,mmcc-msm8974.h | 8 ++++ 3 files changed, 63 insertions(+)
drivers/clk/qcom/Kconfig +1 -0
@@ -99,6 +99,7 @@ config MSM_GCC_8974 config MSM_MMCC_8974 tristate "MSM8974 Multimedia Clock Controller" select MSM_GCC_8974 + select QCOM_GDSC depends on COMMON_CLK_QCOM help Support for the multimedia clock controller on msm8974 devices.
drivers/clk/qcom/mmcc-msm8974.c +54 -0
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include/dt-bindings/clock/qcom,mmcc-msm8974.h +8 -0
@@ -158,4 +158,12 @@#define SPDM_RM_AXI 141#define SPDM_RM_OCMEMNOC 142 +/* gdscs */ +#define VENUS0_GDSC 0 +#define MDSS_GDSC 1 +#define CAMSS_JPEG_GDSC 2 +#define CAMSS_VFE_GDSC 3 +#define OXILI_GDSC 4 +#define OXILICX_GDSC 5 +#endif
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v5 6/11 clk: qcom: gdsc: Add GDSCs in apq8084 GCC
In reply to Rajendra NayakAdd the GDSC instances that exist as part of apq8084 GCC block
--- drivers/clk/qcom/Kconfig | 1 + drivers/clk/qcom/gcc-apq8084.c | 38 ++++++++++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-apq8084.h | 6 +++++ 3 files changed, 45 insertions(+)
drivers/clk/qcom/Kconfig +1 -0
@@ -7,6 +7,7 @@ config COMMON_CLK_QCOM config APQ_GCC_8084 tristate "APQ8084 Global Clock Controller" + select QCOM_GDSC depends on COMMON_CLK_QCOM help Support for the global clock controller on apq8084 devices.
drivers/clk/qcom/gcc-apq8084.c +38 -0
@@ -31,6 +31,7 @@#include "clk-rcg.h" #include "clk-branch.h" #include "reset.h" +#include "gdsc.h" enum {P_XO ,
@@ -3253,6 +3254,34 @@ static struct clk_branch gcc_usb_hsic_system_clk = { }, }; +static struct gdsc usb_hs_hsic_gdsc = { + .gdscr =0x404 , + .pd = { + .name ="usb_hs_hsic" , + }, +}; + +static struct gdsc pcie0_gdsc = { + .gdscr =0x1ac4 , + .pd = { + .name ="pcie0" , + }, +}; + +static struct gdsc pcie1_gdsc = { + .gdscr =0x1b44 , + .pd = { + .name ="pcie1" , + }, +}; + +static struct gdsc usb30_gdsc = { + .gdscr =0x1e84 , + .pd = { + .name ="usb30" , + }, +}; +static struct clk_regmap *gcc_apq8084_clocks[] = { [GPLL0 ] = &gpll0.clkr, [GPLL0_VOTE ] = &gpll0_vote,
@@ -3446,6 +3475,13 @@ static struct clk_regmap *gcc_apq8084_clocks[] = { [GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr, }; +static struct gdsc *gcc_apq8084_gdscs[] = { + [USB_HS_HSIC_GDSC ] = &usb_hs_hsic_gdsc, + [PCIE0_GDSC ] = &pcie0_gdsc, + [PCIE1_GDSC ] = &pcie1_gdsc, + [USB30_GDSC ] = &usb30_gdsc, +}; +static const struct qcom_reset_map gcc_apq8084_resets[] = { [GCC_SYSTEM_NOC_BCR ] = {0x0100 }, [GCC_CONFIG_NOC_BCR ] = {0x0140 },
@@ -3554,6 +3590,8 @@ static const struct qcom_cc_desc gcc_apq8084_desc = { .num_clks = ARRAY_SIZE(gcc_apq8084_clocks), .resets = gcc_apq8084_resets, .num_resets = ARRAY_SIZE(gcc_apq8084_resets), + .gdscs = gcc_apq8084_gdscs, + .num_gdscs = ARRAY_SIZE(gcc_apq8084_gdscs), };static const struct of_device_id gcc_apq8084_match_table[] = {
include/dt-bindings/clock/qcom,gcc-apq8084.h +6 -0
@@ -348,4 +348,10 @@#define GCC_PCIE_1_PIPE_CLK 331#define GCC_PCIE_1_SLV_AXI_CLK 332 +/* gdscs */ +#define USB_HS_HSIC_GDSC 0 +#define PCIE0_GDSC 1 +#define PCIE1_GDSC 2 +#define USB30_GDSC 3 +#endif
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QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v5 7/11 clk: qcom: gdsc: Add GDSCs in apq8084 MMCC
In reply to Rajendra NayakFrom: Stephane Viau <[email protected]>
Add the GDSC instances that exist as part of apq8084 MMCC block.
--- drivers/clk/qcom/Kconfig | 1 + drivers/clk/qcom/mmcc-apq8084.c | 56 ++++++++++++++++++++++++++- include/dt-bindings/clock/qcom,mmcc-apq8084.h | 8 ++++ 3 files changed, 64 insertions(+), 1 deletion(-)
drivers/clk/qcom/Kconfig +1 -0
@@ -17,6 +17,7 @@ config APQ_GCC_8084 config APQ_MMCC_8084 tristate "APQ8084 Multimedia Clock Controller" select APQ_GCC_8084 + select QCOM_GDSC depends on COMMON_CLK_QCOM help Support for the multimedia clock controller on apq8084 devices.
drivers/clk/qcom/mmcc-apq8084.c +55 -1
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include/dt-bindings/clock/qcom,mmcc-apq8084.h +8 -0
@@ -180,4 +180,12 @@#define VPU_SLEEP_CLK 163#define VPU_VDP_CLK 164 +/* GDSCs */ +#define VENUS0_GDSC 0 +#define MDSS_GDSC 1 +#define CAMSS_JPEG_GDSC 2 +#define CAMSS_VFE_GDSC 3 +#define OXILI_GDSC 4 +#define OXILICX_GDSC 5 +#endif
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v5 8/11 arm: dts: qcom: Add #power-domain-cells property
In reply to Rajendra Nayakmsm8974 has gcc and mmcc nodes, and apq8084 has a gcc node which implement gdsc powerdomains. Add the #power-domain-cells property to them.
--- arch/arm/boot/dts/qcom-apq8084.dtsi | 1 + arch/arm/boot/dts/qcom-msm8974.dtsi | 2 ++ 2 files changed, 3 insertions(+)
arch/arm/boot/dts/qcom-apq8084.dtsi +1 -0
@@ -183,6 +183,7 @@ compatible = "qcom,gcc-apq8084"; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; reg = <0xfc400000 0x4000>; };
arch/arm/boot/dts/qcom-msm8974.dtsi +2 -0
@@ -179,6 +179,7 @@ compatible = "qcom,gcc-msm8974"; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; reg = <0xfc400000 0x4000>; };
@@ -186,6 +187,7 @@ compatible = "qcom,mmcc-msm8974"; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; reg = <0xfd8c0000 0x6000>; };
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v5 8/11 arm: dts: qcom: Add #power-domain-cells property
Quoted 15 lines · Rajendra Nayak
msm8974 has gcc and mmcc nodes, and apq8084 has a gcc node which implement gdsc powerdomains. Add the #power-domain-cells property to them.
Signed-off-by Rajendra Nayak <[email protected]>--- arch/arm/boot/dts/qcom-apq8084.dtsi | 1 + arch/arm/boot/dts/qcom-msm8974.dtsi | 2 ++ 2 files changed, 3 insertions(+)arch/arm/boot/dts/qcom-apq8084.dtsi +0
-0
arch/arm/boot/dts/qcom-apq8084.dtsi line 186
Quoted 4 lines
arch/arm/boot/dts/qcom-apq8084.dtsi +1
-0@@ -183,6 +183,7 @@ compatible = "qcom,gcc-apq8084"; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>;
So the PM domain will be apart of the clock-controller. That's a bit odd, but I guess the hardware is like that!?
Anyway, what I fail to understand from this patchset is who will be the actual consumer of the PM domain? In other words, what devices will hold the below property in its DT node?
power_domains = <phandle index>;
This is needed for genpd to have the device at probe time, attached to its PM domain.
Quoted 16 lines
arch/arm/boot/dts/qcom-apq8084.dtsi +0
-0reg = <0xfc400000 0x4000>; };arch/arm/boot/dts/qcom-msm8974.dtsi +1
-0@@ -179,6 +179,7 @@ compatible = "qcom,gcc-msm8974"; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; reg = <0xfc400000 0x4000>; };
arch/arm/boot/dts/qcom-msm8974.dtsi line 193
Quoted 7 lines
arch/arm/boot/dts/qcom-msm8974.dtsi +1
-0@@ -186,6 +187,7 @@ compatible = "qcom,mmcc-msm8974"; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; reg = <0xfd8c0000 0x6000>; };
Kind regards
Uffe
PATCH v5 8/11 arm: dts: qcom: Add #power-domain-cells property
Quoted 11 lines · Ulf Hansson
Quoted 10 lines · Rajendra Nayak
msm8974 has gcc and mmcc nodes, and apq8084 has a gcc node which implement gdsc powerdomains. Add the #power-domain-cells property to them.
Signed-off-by Rajendra Nayak <[email protected]>--- arch/arm/boot/dts/qcom-apq8084.dtsi | 1 + arch/arm/boot/dts/qcom-msm8974.dtsi | 2 ++ 2 files changed, 3 insertions(+)
Quoted 12 lines
arch/arm/boot/dts/qcom-apq8084.dtsi line 186
Quoted 9 lines
arch/arm/boot/dts/qcom-apq8084.dtsi +1
-0@@ -183,6 +183,7 @@ compatible = "qcom,gcc-apq8084"; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>;So the PM domain will be apart of the clock-controller. That's a bit odd, but I guess the hardware is like that!?
Yes, the gdscs are all part of GCC controller.
Quoted 9 lines
Anyway, what I fail to understand from this patchset is who will be the actual consumer of the PM domain? In other words, what devices will hold the below property in its DT node?
power_domains= <phandle index>;This is needed for genpd to have the device at probe time, attached to its PM domain.
Any device which belongs to the collapsible power domain (gdsc) Examples are graphics, camera, video encode/decode block (venus) etc
Quoted 28 lines
Quoted 17 lines
arch/arm/boot/dts/qcom-apq8084.dtsi +0
-0reg = <0xfc400000 0x4000>; };arch/arm/boot/dts/qcom-msm8974.dtsi +1
-0@@ -179,6 +179,7 @@ compatible = "qcom,gcc-msm8974"; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; reg = <0xfc400000 0x4000>; };arch/arm/boot/dts/qcom-msm8974.dtsi line 193
Quoted 7 lines
arch/arm/boot/dts/qcom-msm8974.dtsi +1
-0@@ -186,6 +187,7 @@ compatible = "qcom,mmcc-msm8974"; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; reg = <0xfd8c0000 0x6000>; };Kind regards
Uffe
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Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v5 8/11 arm: dts: qcom: Add #power-domain-cells property
Quoted 26 lines · Rajendra Nayak
Quoted 13 lines · Ulf Hansson
Quoted 12 lines · Rajendra Nayak
msm8974 has gcc and mmcc nodes, and apq8084 has a gcc node which implement gdsc powerdomains. Add the #power-domain-cells property to them.
Signed-off-by Rajendra Nayak <[email protected]>--- arch/arm/boot/dts/qcom-apq8084.dtsi | 1 + arch/arm/boot/dts/qcom-msm8974.dtsi | 2 ++ 2 files changed, 3 insertions(+)arch/arm/boot/dts/qcom-apq8084.dtsi +0
-0Quoted 11 lines
arch/arm/boot/dts/qcom-apq8084.dtsi line 186
Quoted 8 lines
index 1f130bc..55c281c 100644
arch/arm/boot/dts/qcom-apq8084.dtsi +1
-0@@ -183,6 +183,7 @@ compatible = "qcom,gcc-apq8084"; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>;So the PM domain will be apart of the clock-controller. That's a bit odd, but I guess the hardware is like that!?
Quoted 1 line
Yes, the gdscs are all part of GCC controller.
correction. and other clock controllers too, like MMCC.
PATCH v5 8/11 arm: dts: qcom: Add #power-domain-cells property
In reply to Rajendra NayakQuoted 37 lines · Rajendra Nayak
Quoted 13 lines · Ulf Hansson
Quoted 11 lines · Rajendra Nayak
msm8974 has gcc and mmcc nodes, and apq8084 has a gcc node which implement gdsc powerdomains. Add the #power-domain-cells property to them.
Signed-off-by Rajendra Nayak <[email protected]>--- arch/arm/boot/dts/qcom-apq8084.dtsi | 1 + arch/arm/boot/dts/qcom-msm8974.dtsi | 2 ++ 2 files changed, 3 insertions(+)Quoted 14 lines
arch/arm/boot/dts/qcom-apq8084.dtsi line 186
Quoted 10 lines
arch/arm/boot/dts/qcom-apq8084.dtsi +1
-0@@ -183,6 +183,7 @@ compatible = "qcom,gcc-apq8084"; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>;So the PM domain will be apart of the clock-controller. That's a bit odd, but I guess the hardware is like that!?
Yes, the gdscs are all part of GCC controller.
Quoted 5 lines
Anyway, what I fail to understand from this patchset is who will be the actual consumer of the PM domain? In other words, what devices will hold the below property in its DT node?
Quoted 8 lines
Quoted 4 lines
power_domains= <phandle index>;This is needed for genpd to have the device at probe time, attached to its PM domain.
Any device which belongs to the collapsible power domain (gdsc) Examples are graphics, camera, video encode/decode block (venus) etc
Then I expect those drivers to deploy runtime PM (if not already) and thus gdsc's PM domain will come into play.
But how will that relate to the GCC controller?
For example when the gdsc's PM domain is about to be powered off, since all the devices within it has be runtime PM suspended. What happens with the GCC controller then?
Kind regards
Uffe
PATCH v5 8/11 arm: dts: qcom: Add #power-domain-cells property
Quoted 44 lines · Ulf Hansson
Quoted 43 lines · Rajendra Nayak
Quoted 13 lines · Ulf Hansson
Quoted 11 lines · Rajendra Nayak
msm8974 has gcc and mmcc nodes, and apq8084 has a gcc node which implement gdsc powerdomains. Add the #power-domain-cells property to them.
Signed-off-by Rajendra Nayak <[email protected]>--- arch/arm/boot/dts/qcom-apq8084.dtsi | 1 + arch/arm/boot/dts/qcom-msm8974.dtsi | 2 ++ 2 files changed, 3 insertions(+)Quoted 14 lines
arch/arm/boot/dts/qcom-apq8084.dtsi line 186
Quoted 10 lines
arch/arm/boot/dts/qcom-apq8084.dtsi +1
-0@@ -183,6 +183,7 @@ compatible = "qcom,gcc-apq8084"; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>;So the PM domain will be apart of the clock-controller. That's a bit odd, but I guess the hardware is like that!?
Yes, the gdscs are all part of GCC controller.
Quoted 9 lines
Anyway, what I fail to understand from this patchset is who will be the actual consumer of the PM domain? In other words, what devices will hold the below property in its DT node?
power_domains= <phandle index>;This is needed for genpd to have the device at probe time, attached to its PM domain.
Quoted 5 lines
Quoted 2 lines
Any device which belongs to the collapsible power domain (gdsc) Examples are graphics, camera, video encode/decode block (venus) etc
Then I expect those drivers to deploy runtime PM (if not already) and thus gdsc's PM domain will come into play.
Most of these drivers aren;t upstream yet. And one of the reasons I am trying to get gdsc support upstream is so these drivers can then be pushed upstream, with runtime support.
Quoted 6 lines
But how will that relate to the GCC controller?
For example when the gdsc's PM domain is about to be powered off, since all the devices within it has be runtime PM suspended. What happens with the GCC controller then?
I don;t seem to completely understand what you are asking. Are you asking if the GCC controller itself is part of a collapsible power domain?
Quoted 4 lines
Kind regards
Uffe
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v5 8/11 arm: dts: qcom: Add #power-domain-cells property
Quoted 56 lines · Rajendra Nayak
Quoted 55 lines · Ulf Hansson
Quoted 51 lines · Rajendra Nayak
Quoted 15 lines · Ulf Hansson
Quoted 12 lines · Rajendra Nayak
msm8974 has gcc and mmcc nodes, and apq8084 has a gcc node which implement gdsc powerdomains. Add the #power-domain-cells property to them.
Signed-off-by Rajendra Nayak <[email protected]>--- arch/arm/boot/dts/qcom-apq8084.dtsi | 1 + arch/arm/boot/dts/qcom-msm8974.dtsi | 2 ++ 2 files changed, 3 insertions(+)Quoted 15 lines
arch/arm/boot/dts/qcom-apq8084.dtsi line 186
Quoted 10 lines
arch/arm/boot/dts/qcom-apq8084.dtsi +1
-0@@ -183,6 +183,7 @@ compatible = "qcom,gcc-apq8084"; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>;So the PM domain will be apart of the clock-controller. That's a bit odd, but I guess the hardware is like that!?
Yes, the gdscs are all part of GCC controller.
Quoted 9 lines
Anyway, what I fail to understand from this patchset is who will be the actual consumer of the PM domain? In other words, what devices will hold the below property in its DT node?
power_domains= <phandle index>;This is needed for genpd to have the device at probe time, attached to its PM domain.
Any device which belongs to the collapsible power domain (gdsc) Examples are graphics, camera, video encode/decode block (venus) etc
Quoted 7 lines
Quoted 2 lines
Then I expect those drivers to deploy runtime PM (if not already) and thus gdsc's PM domain will come into play.
Most of these drivers aren;t upstream yet. And one of the reasons I am trying to get gdsc support upstream is so these drivers can then be pushed upstream, with runtime support.
That's great news! I am happy to help reviewing, if you like.
Quoted 4 lines
Quoted 4 lines
But how will that relate to the GCC controller?
Quoted 8 lines
Quoted 3 lines
For example when the gdsc's PM domain is about to be powered off, since all the devices within it has be runtime PM suspended. What happens with the GCC controller then?
I don;t seem to completely understand what you are asking. Are you asking if the GCC controller itself is part of a collapsible power domain?
Yes. Sorry for being a bit vague...
If the gdsc's PM domain is powered off, what happens with the GCC's clocks?
Kind regards
Uffe
PATCH v5 8/11 arm: dts: qcom: Add #power-domain-cells property
Quoted 76 lines · Ulf Hansson
Quoted 56 lines · Rajendra Nayak
Quoted 55 lines · Ulf Hansson
Quoted 51 lines · Rajendra Nayak
Quoted 15 lines · Ulf Hansson
Quoted 12 lines · Rajendra Nayak
msm8974 has gcc and mmcc nodes, and apq8084 has a gcc node which implement gdsc powerdomains. Add the #power-domain-cells property to them.
Signed-off-by Rajendra Nayak <[email protected]>--- arch/arm/boot/dts/qcom-apq8084.dtsi | 1 + arch/arm/boot/dts/qcom-msm8974.dtsi | 2 ++ 2 files changed, 3 insertions(+)Quoted 15 lines
arch/arm/boot/dts/qcom-apq8084.dtsi line 186
Quoted 10 lines
arch/arm/boot/dts/qcom-apq8084.dtsi +1
-0@@ -183,6 +183,7 @@ compatible = "qcom,gcc-apq8084"; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>;So the PM domain will be apart of the clock-controller. That's a bit odd, but I guess the hardware is like that!?
Yes, the gdscs are all part of GCC controller.
Quoted 9 lines
Anyway, what I fail to understand from this patchset is who will be the actual consumer of the PM domain? In other words, what devices will hold the below property in its DT node?
power_domains= <phandle index>;This is needed for genpd to have the device at probe time, attached to its PM domain.
Any device which belongs to the collapsible power domain (gdsc) Examples are graphics, camera, video encode/decode block (venus) etc
Quoted 7 lines
Quoted 2 lines
Then I expect those drivers to deploy runtime PM (if not already) and thus gdsc's PM domain will come into play.
Most of these drivers aren;t upstream yet. And one of the reasons I am trying to get gdsc support upstream is so these drivers can then be pushed upstream, with runtime support.
That's great news! I am happy to help reviewing, if you like.
Quoted 9 lines
Quoted 7 lines
But how will that relate to the GCC controller?
For example when the gdsc's PM domain is about to be powered off, since all the devices within it has be runtime PM suspended. What happens with the GCC controller then?
Quoted 7 lines
Quoted 3 lines
I don;t seem to completely understand what you are asking. Are you asking if the GCC controller itself is part of a collapsible power domain?
Yes. Sorry for being a bit vague...
If the gdsc's PM domain is powered off, what happens with the GCC's clocks?
The clocks need to be turned off explicitly. So for a device to be functional the driver would turn the power switch on, and then enable the needed clocks and the other way around when the device is no longer needed and can be turned off.
Quoted 8 lines
Kind regards
Uffe
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Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v5 9/11 clk: qcom: gdsc: Use PM clocks to control gdsc clocks
In reply to Rajendra NayakThe devices within a gdsc power domain, quite often have additional clocks to be turned on/off along with the power domain itself. Once the drivers for these devices are converted to use runtime PM, it would be possible to remove all clock handling from the drivers if the gdsc driver can handle it.
Use PM clocks to add support for this. A list of con_ids[] specified per gdsc would be the clocks turned on/off on every device start/stop callbacks.
--- drivers/clk/qcom/gdsc.c | 43 +++++++++++++++++++++++++++++++++++++++++++ drivers/clk/qcom/gdsc.h | 2 ++ 2 files changed, 45 insertions(+)
drivers/clk/qcom/gdsc.c +43 -0
@@ -14,6 +14,7 @@#include <linux/delay.h> #include <linux/err.h> #include <linux/jiffies.h> +#include <linux/pm_clock.h> #include <linux/slab.h> #include "gdsc.h"
@@ -104,6 +105,45 @@ static int gdsc_disable(struct generic_pm_domain *domain)return gdsc_toggle_logic (sc, false); } +static int gdsc_attach (struct generic_pm_domain *domain,struct device *dev) +{ +int ret; +struct gdsc *sc =domain_to_gdsc (domain); +char **con_id; + +if (!sc->con_ids[0 ]) +return 0 ; + + ret =pm_clk_create (dev); +if (ret) { +dev_err (dev,"pm_clk_create failed %d\n" , ret); +return ret; + } + +for (con_id = sc->con_ids; *con_id; con_id++) { + ret =pm_clk_add (dev, *con_id); +if (ret) { +dev_err (dev,"pm_clk_add failed %d\n" , ret); + goto fail; + } + } +return 0 ; +fail: +pm_clk_destroy (dev); +return ret; +}; + +static void gdsc_detach (struct generic_pm_domain *domain,struct device *dev) +{ +struct gdsc *sc =domain_to_gdsc (domain); + +if (!sc->con_ids[0 ]) +return ; + +pm_clk_destroy (dev); +return ; +}; +static int gdsc_init (struct gdsc *sc) {u32 mask, val;
@@ -127,6 +167,9 @@ static int gdsc_init(struct gdsc *sc) sc->pd.power_off = gdsc_disable; sc->pd.power_on = gdsc_enable; + sc->pd.attach_dev = gdsc_attach; + sc->pd.detach_dev = gdsc_detach; + sc->pd.flags =GENPD_FLAG_PM_CLK ;pm_genpd_init (&sc->pd,NULL , !on);return 0 ;
drivers/clk/qcom/gdsc.h +2 -0
@@ -22,11 +22,13 @@* @pd: generic power domain * @regmap: regmap for MMIO accesses * @gdscr: gsdc control register +* @con_ids: List of clocks to be controlled for the gdsc */ struct gdsc {struct generic_pm_domain pd;struct regmap *regmap;unsigned int gdscr; +char *con_ids[]; };#ifdef CONFIG_QCOM_GDSC
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v5 9/11 clk: qcom: gdsc: Use PM clocks to control gdsc clocks
Hi, Rajendra,
Quoted 14 lines · Rajendra Nayak
The devices within a gdsc power domain, quite often have additional clocks to be turned on/off along with the power domain itself. Once the drivers for these devices are converted to use runtime PM, it would be possible to remove all clock handling from the drivers if the gdsc driver can handle it.
Use PM clocks to add support for this. A list of con_ids[] specified per gdsc would be the clocks turned on/off on every device start/stop callbacks.Signed-off-by Rajendra Nayak <[email protected]>--- drivers/clk/qcom/gdsc.c | 43 +++++++++++++++++++++++++++++++++++++++++++ drivers/clk/qcom/gdsc.h | 2 ++ 2 files changed, 45 insertions(+)
<snip>
drivers/clk/qcom/gdsc.c static int gdsc_disable(struct generic_pm_domain *domain) · line 115
Quoted 9 lines
drivers/clk/qcom/gdsc.c +8
-0+static int gdsc_attach (struct generic_pm_domain *domain,struct device *dev) +{ +int ret; +struct gdsc *sc =domain_to_gdsc (domain); +char **con_id; + +if (!sc->con_ids[0 ]) +return 0 ;
Did you test this on your side? It panic kernel badly cause the flexible array is not initialised.
Could you revisit the above check. Or you could add below initialisation for every gdsc structure in gcc-xxx.c files.
static struct gdsc venus_gdsc = {
.gdscr = 0x4c018,
.pd = {
.name = "venus",
},
.con_ids = { NULL },
};Quoted 20 lines
drivers/clk/qcom/gdsc.c +20
-0+ + ret =pm_clk_create (dev); +if (ret) { +dev_err (dev,"pm_clk_create failed %d\n" , ret); +return ret; + } + +for (con_id = sc->con_ids; *con_id; con_id++) { + ret =pm_clk_add (dev, *con_id); +if (ret) { +dev_err (dev,"pm_clk_add failed %d\n" , ret); + goto fail; + } + } +return 0 ; +fail: +pm_clk_destroy (dev); +return ret; +}; +
<snip>
Signature · 2 lines
regards, Stan
PATCH v5 9/11 clk: qcom: gdsc: Use PM clocks to control gdsc clocks
[]
Quoted 13 lines
drivers/clk/qcom/gdsc.c static int gdsc_disable(struct generic_pm_domain *domain) · line 115
Quoted 9 lines
drivers/clk/qcom/gdsc.c +8
-0+static int gdsc_attach (struct generic_pm_domain *domain,struct device *dev) +{ +int ret; +struct gdsc *sc =domain_to_gdsc (domain); +char **con_id; + +if (!sc->con_ids[0 ]) +return 0 ;Did you test this on your side? It panic kernel badly cause the flexible array is not initialised.
Quoted 2 lines
Could you revisit the above check. Or you could add below initialisation for every gdsc structure in
gcc-xxx.cfiles.
Hey, that does seem like a problem. Not sure how I did not end up seeing it. I'll fix it up, thanks.
Quoted 34 lines
static struct gdsc venus_gdsc = { .gdscr = 0x4c018, .pd = { .name = "venus", }, .con_ids = { NULL }, };Quoted 20 lines
drivers/clk/qcom/gdsc.c +20
-0+ + ret =pm_clk_create (dev); +if (ret) { +dev_err (dev,"pm_clk_create failed %d\n" , ret); +return ret; + } + +for (con_id = sc->con_ids; *con_id; con_id++) { + ret =pm_clk_add (dev, *con_id); +if (ret) { +dev_err (dev,"pm_clk_add failed %d\n" , ret); + goto fail; + } + } +return 0 ; +fail: +pm_clk_destroy (dev); +return ret; +}; +<snip>
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v5 10/11 clk: qcom: gdsc: Enable an RCG before turning on the gdsc
In reply to Rajendra NayakSome gdsc instances require a certain root clock (RCG) to be turned on *before* the power domain itself can be turned on. Handle this as part of the gdsc enable/disable callbacks.
--- drivers/clk/qcom/gdsc.c | 20 +++++++++++++++++++- drivers/clk/qcom/gdsc.h | 3 +++ 2 files changed, 22 insertions(+), 1 deletion(-)
drivers/clk/qcom/gdsc.c +19 -1
@@ -83,6 +83,9 @@ static int gdsc_enable(struct generic_pm_domain *domain)struct gdsc *sc =domain_to_gdsc (domain);int ret; +if (sc->root_clk) +clk_prepare_enable (sc->root_clk); + ret =gdsc_toggle_logic (sc, true);if (ret)return ret;
@@ -100,9 +103,15 @@ static int gdsc_enable(struct generic_pm_domain *domain)static int gdsc_disable (struct generic_pm_domain *domain) { +int ret;struct gdsc *sc =domain_to_gdsc (domain); -return gdsc_toggle_logic (sc, false); + ret =gdsc_toggle_logic (sc, false); + +if (sc->root_clk) +clk_disable_unprepare (sc->root_clk); + +return ret; }static int gdsc_attach (struct generic_pm_domain *domain,struct device *dev)
@@ -127,6 +136,15 @@ static int gdsc_attach(struct generic_pm_domain *domain, struct device *dev) goto fail; } } + +if (sc->root_con_id) { + sc->root_clk =clk_get (dev, sc->root_con_id); +if (IS_ERR (sc->root_clk)) { +dev_err (dev,"failed to get root clock\n" ); +return PTR_ERR (sc->root_clk); + } + } +return 0 ; fail:pm_clk_destroy (dev);
drivers/clk/qcom/gdsc.h +3 -0
@@ -14,6 +14,7 @@#ifndef __QCOM_GDSC_H__#define __QCOM_GDSC_H__ +#include <linux/clk.h> #include <linux/pm_domain.h> #include <linux/regmap.h>
@@ -28,6 +29,8 @@ struct gdsc {struct generic_pm_domain pd;struct regmap *regmap;unsigned int gdscr; +char *root_con_id; +struct clk *root_clk;char *con_ids[]; };
Signature · 2 lines
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PATCH v5 11/11 clk: qcom: gdsc: Add oxili GDSC for msm8916
In reply to Rajendra NayakWith the support to control root clk along with the gdsc powerdomain now added, add the gdsc data for oxili on msm8916.
--- drivers/clk/qcom/gcc-msm8916.c | 9 +++++++++ 1 file changed, 9 insertions(+)
drivers/clk/qcom/gcc-msm8916.c +9 -0
@@ -2591,6 +2591,14 @@ static struct gdsc vfe_gdsc = { }, }; +static struct gdsc oxili_gdsc = { + .gdscr =0x5901c , + .pd = { + .name ="oxili" , + }, + .root_con_id ="gfx3d_clk_src" , +}; +static struct clk_regmap *gcc_msm8916_clocks[] = { [GPLL0 ] = &gpll0.clkr, [GPLL0_VOTE ] = &gpll0_vote,
@@ -2737,6 +2745,7 @@ static struct gdsc *gcc_msm8916_gdscs[] = { [MDSS_GDSC] = &mdss_gdsc, [JPEG_GDSC] = &jpeg_gdsc, [VFE_GDSC] = &vfe_gdsc, + [OXILI_GDSC] = &oxili_gdsc, };static const struct qcom_reset_map gcc_msm8916_resets[] = {
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation