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mx6sabresd: Fix SPL memory description

PATCH New Fabio Estevam 2 participants 4 messages Apr 17, 2015 – Apr 22, 2015

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Fabio Estevam

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#0 lore raw

PATCH 1/2 mx6sabresd: Fix SPL memory description

From: Fabio Estevam <[email protected]>

mx6sabresd has four MT41K128M16JT-125 chips. Each memory has 16-bit bus and 2GiB, so fix the width and density fields accordingly.

Signed-off-by Fabio Estevam <[email protected]>
---
 board/freescale/mx6sabresd/mx6sabresd.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)
board/freescale/mx6sabresd/mx6sabresd.c +5 -4
index bb2dd96..a4f3a94 100644
@@ -753,10 +753,11 @@ const struct mx6_mmdc_calibration mx6_mmcd_calib = {
 	.p1_mpwrdlctl =  0x48254A36,
 };
 
+/* MT41K128M16JT-125 */
 static struct mx6_ddr3_cfg mem_ddr = {
 	.mem_speed = 1600,
-	.density = 4,
-	.width = 64,
+	.density = 2,
+	.width = 16,
 	.banks = 8,
 	.rowaddr = 14,
 	.coladdr = 10,

@@ -798,7 +799,7 @@ static void spl_dram_init(void)
 {
 	struct mx6_ddr_sysinfo sysinfo = {
 		/* width of data bus:0=16,1=32,2=64 */
-		.dsize = mem_ddr.width/32,
+		.dsize = 2,
 		/* config for full 4GB range so that get_mem_size() works */
 		.cs_density = 32, /* 32Gb per CS */
 		/* single chip select */

@@ -818,7 +819,7 @@ static void spl_dram_init(void)
 		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
 	};
 
-	mx6dq_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+	mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 	mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
 }
Signature · 1 line
1.9.1
author
#1 lore raw

PATCH 2/2 mx6sabresd: Remove uneeded ifdef

From: Fabio Estevam <[email protected]>

RTT_NOM_120OHM is not defined, so remove its ifdef.

Signed-off-by Fabio Estevam <[email protected]>
---
 board/freescale/mx6sabresd/mx6sabresd.c | 4 ----
 1 file changed, 4 deletions(-)
board/freescale/mx6sabresd/mx6sabresd.c +0 -4
index a4f3a94..23f8f6b 100644
@@ -806,11 +806,7 @@ static void spl_dram_init(void)
 		.ncs = 1,
 		.cs1_mirror = 0,
 		.rtt_wr = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Wr = RZQ/4 */
-#ifdef RTT_NOM_120OHM
-		.rtt_nom = 2 /*DDR3_RTT_120_OHM*/,	/* RTT_Nom = RZQ/2 */
-#else
 		.rtt_nom = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Nom = RZQ/4 */
-#endif
 		.walat = 1,	/* Write additional latency */
 		.ralat = 5,	/* Read additional latency */
 		.mif3_mode = 3,	/* Command prediction working mode */
Signature · 1 line
1.9.1
#2 lore raw

PATCH 2/2 mx6sabresd: Remove uneeded ifdef

Quoted 6 lines · Fabio Estevam

From: Fabio Estevam <[email protected]>

RTT_NOM_120OHM is not defined, so remove its ifdef.

Signed-off-by Fabio Estevam <[email protected]>

---

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

Signature · 5 lines
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
#3 lore raw

PATCH 1/2 mx6sabresd: Fix SPL memory description

In reply to Fabio Estevam
Quoted 7 lines · Fabio Estevam

From: Fabio Estevam <[email protected]>

mx6sabresd has four MT41K128M16JT-125 chips. Each memory has 16-bit bus and 2GiB, so fix the width and density fields accordingly.

Signed-off-by Fabio Estevam <[email protected]>

---

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

Signature · 5 lines
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================