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i.MX6 PU power domain support

PATCH Superseded Philipp Zabel 3 participants 10 messages Feb 23, 2015 – Apr 22, 2015

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Philipp Zabel

author
#0 lore raw

v9 cover i.MX6 PU power domain support

this is a rebased and updated version of the series I sent previously:

http://www.spinics.net/lists/arm-kernel/msg360709.html

Changes since v8:
- Updated DT documentation example with IRQ_TYPE_... and IMX6QDL_CLK_... defines
- Made PU regulator optional to support i.MX6SX, suggested by Robin Gong
- Removed regulator_enable() call in the probe function, stopped disabling the regulator in imx6q_pm_pu_power_off() - the regulator framework will disable unused regulators.
- Changed the GPC driver to enable pu power if CONFIG_PM is not enabled, as some bootloaders disable pu power on boot.

regards
Philipp

Philipp Zabel (6):
Documentation: Add device tree bindings for Freescale i.MX GPC
ARM: imx6: gpc: Add PU power domain for GPU/VPU
ARM: dts: imx6qdl: Add power-domain information to gpc node
ARM: dts: imx6sl: Add power-domain information to gpc node
ARM: dts: imx6qdl: Allow disabling the PU regulator, add a enable ramp
delay
ARM: imx6: gpc: Allow PU regulator bypass

 .../devicetree/bindings/power/fsl,imx-gpc.txt      |  59 ++++++
 arch/arm/boot/dts/imx6qdl.dtsi                     |  10 +-
 arch/arm/boot/dts/imx6sl.dtsi                      |   4 +
 arch/arm/mach-imx/Kconfig                          |   1 +
 arch/arm/mach-imx/gpc.c                            | 216 +++++++++++++++++++++
 5 files changed, 289 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/power/fsl,imx-gpc.txt
Signature · 1 line
2.1.4
author
#1 lore raw

PATCH v9 1/5 Documentation: Add device tree bindings for Freescale i.MX GPC

The i.MX6 contains a power controller that controls power gating and sequencing for the SoC's power domains.

Signed-off-by Philipp Zabel <[email protected]>

---
Changes since v8:
- Updated example with IRQ_TYPE_... and IMX6QDL_CLK_... defines

---
 .../devicetree/bindings/power/fsl,imx-gpc.txt      | 59 ++++++++++++++++++++++
 1 file changed, 59 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/power/fsl,imx-gpc.txt
Documentation/devicetree/bindings/power/fsl,imx-gpc.txt new file +59 -0
new file mode 100644
index 0000000..65cc034
@@ -0,0 +1,59 @@
+Freescale i.MX General Power Controller
+=======================================
+
+The i.MX6Q General Power Control (GPC) block contains DVFS load tracking
+counters and Power Gating Control (PGC) for the CPU and PU (GPU/VPU) power
+domains.
+
+Required properties:
+- compatible: Should be "fsl,imx6q-gpc" or "fsl,imx6sl-gpc"
+- reg: should be register base and length as documented in the
+  datasheet
+- interrupts: Should contain GPC interrupt request 1
+- pu-supply: Link to the LDO regulator powering the PU power domain
+- clocks: Clock phandles to devices in the PU power domain that need
+	  to be enabled during domain power-up for reset propagation.
+- #power-domain-cells: Should be 1, see below:
+
+The gpc node is a power-controller as documented by the generic power domain
+bindings in Documentation/devicetree/bindings/power/power_domain.txt.
+
+Example:
+
+	gpc: gpc at 020dc000 {
+		compatible = "fsl,imx6q-gpc";
+		reg = <0x020dc000 0x4000>;
+		interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
+			     <0 90 IRQ_TYPE_LEVEL_HIGH>;
+		pu-supply = <&reg_pu>;
+		clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
+			 <&clks IMX6QDL_CLK_GPU3D_SHADER>,
+			 <&clks IMX6QDL_CLK_GPU2D_CORE>,
+			 <&clks IMX6QDL_CLK_GPU2D_AXI>,
+			 <&clks IMX6QDL_CLK_OPENVG_AXI>,
+			 <&clks IMX6QDL_CLK_VPU_AXI>;
+		#power-domain-cells = <1>;
+	};
+
+
+Specifying power domain for IP modules
+======================================
+
+IP cores belonging to a power domain should contain a 'power-domains' property
+that is a phandle pointing to the gpc device node and a DOMAIN_INDEX specifying
+the power domain the device belongs to.
+
+Example of a device that is part of the PU power domain:
+
+	vpu: vpu at 02040000 {
+		reg = <0x02040000 0x3c000>;
+		/* ... */
+		power-domains = <&gpc 1>;
+		/* ... */
+	};
+
+The following DOMAIN_INDEX values are valid for i.MX6Q:
+ARM_DOMAIN     0
+PU_DOMAIN      1
+The following additional DOMAIN_INDEX value is valid for i.MX6SL:
+DISPLAY_DOMAIN 2
Signature · 1 line
2.1.4
#2 lore raw

PATCH v9 1/5 Documentation: Add device tree bindings for Freescale i.MX GPC

Quoted 4 lines · Philipp Zabel

The i.MX6 contains a power controller that controls power gating and sequencing for the SoC's power domains.

Signed-off-by Philipp Zabel <[email protected]>

The patch (series) looks fine to me. Can we get DT maintainer's ACK on this, so that I can apply the series for 4.1?

Shawn

Quoted 76 lines

---
Changes since v8:
- Updated example with IRQ_TYPE_... and IMX6QDL_CLK_... defines

---
 .../devicetree/bindings/power/fsl,imx-gpc.txt      | 59 ++++++++++++++++++++++
 1 file changed, 59 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/power/fsl,imx-gpc.txt
Documentation/devicetree/bindings/power/fsl,imx-gpc.txt new file +59 -0
new file mode 100644
index 0000000..65cc034
@@ -0,0 +1,59 @@
+Freescale i.MX General Power Controller
+=======================================
+
+The i.MX6Q General Power Control (GPC) block contains DVFS load tracking
+counters and Power Gating Control (PGC) for the CPU and PU (GPU/VPU) power
+domains.
+
+Required properties:
+- compatible: Should be "fsl,imx6q-gpc" or "fsl,imx6sl-gpc"
+- reg: should be register base and length as documented in the
+  datasheet
+- interrupts: Should contain GPC interrupt request 1
+- pu-supply: Link to the LDO regulator powering the PU power domain
+- clocks: Clock phandles to devices in the PU power domain that need
+	  to be enabled during domain power-up for reset propagation.
+- #power-domain-cells: Should be 1, see below:
+
+The gpc node is a power-controller as documented by the generic power domain
+bindings in Documentation/devicetree/bindings/power/power_domain.txt.
+
+Example:
+
+	gpc: gpc at 020dc000 {
+		compatible = "fsl,imx6q-gpc";
+		reg = <0x020dc000 0x4000>;
+		interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
+			     <0 90 IRQ_TYPE_LEVEL_HIGH>;
+		pu-supply = <&reg_pu>;
+		clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
+			 <&clks IMX6QDL_CLK_GPU3D_SHADER>,
+			 <&clks IMX6QDL_CLK_GPU2D_CORE>,
+			 <&clks IMX6QDL_CLK_GPU2D_AXI>,
+			 <&clks IMX6QDL_CLK_OPENVG_AXI>,
+			 <&clks IMX6QDL_CLK_VPU_AXI>;
+		#power-domain-cells = <1>;
+	};
+
+
+Specifying power domain for IP modules
+======================================
+
+IP cores belonging to a power domain should contain a 'power-domains' property
+that is a phandle pointing to the gpc device node and a DOMAIN_INDEX specifying
+the power domain the device belongs to.
+
+Example of a device that is part of the PU power domain:
+
+	vpu: vpu at 02040000 {
+		reg = <0x02040000 0x3c000>;
+		/* ... */
+		power-domains = <&gpc 1>;
+		/* ... */
+	};
+
+The following DOMAIN_INDEX values are valid for i.MX6Q:
+ARM_DOMAIN     0
+PU_DOMAIN      1
+The following additional DOMAIN_INDEX value is valid for i.MX6SL:
+DISPLAY_DOMAIN 2
Signature · 1 line
2.1.4
#3 lore raw

PATCH v9 1/5 Documentation: Add device tree bindings for Freescale i.MX GPC

Am Dienstag, den 03.03.2015, 10:35 +0800 schrieb Shawn Guo:

Quoted 11 lines · Philipp Zabel
Quoted 4 lines

The i.MX6 contains a power controller that controls power gating and sequencing for the SoC's power domains.

Signed-off-by Philipp Zabel <[email protected]>

The patch (series) looks fine to me. Can we get DT maintainer's ACK on this, so that I can apply the series for 4.1?

Shawn

I'm formally NACKing this series.

I've talked to Philipp and we decided to change the DT binding slightly to better accommodate SoCs with multiple domains like the imx6sx.

I will send a new version of this series shortly.

Regards,
Lucas

Quoted 81 lines
Quoted 76 lines

---
Changes since v8:
- Updated example with IRQ_TYPE_... and IMX6QDL_CLK_... defines

---
 .../devicetree/bindings/power/fsl,imx-gpc.txt      | 59 ++++++++++++++++++++++
 1 file changed, 59 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/power/fsl,imx-gpc.txt
Documentation/devicetree/bindings/power/fsl,imx-gpc.txt new file +59 -0
new file mode 100644
index 0000000..65cc034
@@ -0,0 +1,59 @@
+Freescale i.MX General Power Controller
+=======================================
+
+The i.MX6Q General Power Control (GPC) block contains DVFS load tracking
+counters and Power Gating Control (PGC) for the CPU and PU (GPU/VPU) power
+domains.
+
+Required properties:
+- compatible: Should be "fsl,imx6q-gpc" or "fsl,imx6sl-gpc"
+- reg: should be register base and length as documented in the
+  datasheet
+- interrupts: Should contain GPC interrupt request 1
+- pu-supply: Link to the LDO regulator powering the PU power domain
+- clocks: Clock phandles to devices in the PU power domain that need
+	  to be enabled during domain power-up for reset propagation.
+- #power-domain-cells: Should be 1, see below:
+
+The gpc node is a power-controller as documented by the generic power domain
+bindings in Documentation/devicetree/bindings/power/power_domain.txt.
+
+Example:
+
+	gpc: gpc at 020dc000 {
+		compatible = "fsl,imx6q-gpc";
+		reg = <0x020dc000 0x4000>;
+		interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
+			     <0 90 IRQ_TYPE_LEVEL_HIGH>;
+		pu-supply = <&reg_pu>;
+		clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
+			 <&clks IMX6QDL_CLK_GPU3D_SHADER>,
+			 <&clks IMX6QDL_CLK_GPU2D_CORE>,
+			 <&clks IMX6QDL_CLK_GPU2D_AXI>,
+			 <&clks IMX6QDL_CLK_OPENVG_AXI>,
+			 <&clks IMX6QDL_CLK_VPU_AXI>;
+		#power-domain-cells = <1>;
+	};
+
+
+Specifying power domain for IP modules
+======================================
+
+IP cores belonging to a power domain should contain a 'power-domains' property
+that is a phandle pointing to the gpc device node and a DOMAIN_INDEX specifying
+the power domain the device belongs to.
+
+Example of a device that is part of the PU power domain:
+
+	vpu: vpu at 02040000 {
+		reg = <0x02040000 0x3c000>;
+		/* ... */
+		power-domains = <&gpc 1>;
+		/* ... */
+	};
+
+The following DOMAIN_INDEX values are valid for i.MX6Q:
+ARM_DOMAIN     0
+PU_DOMAIN      1
+The following additional DOMAIN_INDEX value is valid for i.MX6SL:
+DISPLAY_DOMAIN 2
Signature · 1 line
2.1.4

_______________________________________________
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linux-arm-kernel at lists.infradead.org
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Signature · 2 lines
Pengutronix e.K.             | Lucas Stach                 |
Industrial Linux Solutions   | http://www.pengutronix.de/  |
author
#4 lore raw

PATCH v9 2/5 ARM: imx6: gpc: Add PU power domain for GPU/VPU

In reply to Philipp Zabel

When generic pm domain support is enabled, the PGC can be used to completely gate power to the PU power domain containing GPU3D, GPU2D, and VPU cores.
This code triggers the PGC powerdown sequence to disable the GPU/VPU isolation cells and gate power and then disables the PU regulator. To reenable, the reverse powerup sequence is triggered after the PU regulator is enabled again.
The GPU and VPU devices in the PU power domain temporarily need to be clocked during powerup, so that the reset machinery can work.

[Avoid explicit regulator enabling in probe, unless !PM]
Signed-off-by Markus Pargmann <[email protected]>
Signed-off-by Philipp Zabel <[email protected]>

---
Changes since v8:
- Made PU regulator optional to support i.MX6SX, suggested by Robin Gong
- Removed regulator_enable() call in the probe function, stopped disabling the regulator in imx6q_pm_pu_power_off() - the regulator framework will disable unused regulators.
- Enable pu power if CONFIG_PM is not enabled, as some bootloaders disable pu power on boot, causing it to stay always disabled.

---
 arch/arm/mach-imx/Kconfig |   1 +
 arch/arm/mach-imx/gpc.c   | 213 ++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 214 insertions(+)
arch/arm/mach-imx/Kconfig +1 -0
index e8627e0..d988d41 100644
@@ -50,6 +50,7 @@ config HAVE_IMX_ANATOP
 
 config HAVE_IMX_GPC
 	bool
+	select PM_GENERIC_DOMAINS if PM
 
 config HAVE_IMX_MMDC
 	bool
arch/arm/mach-imx/gpc.c +213 -0

237 lines not on this page · raw message

Signature · 1 line
2.1.4
author
#5 lore raw

PATCH v9 3/5 ARM: dts: imx6qdl: Add power-domain information to gpc node

In reply to Philipp Zabel

The PGC that is part of GPC controls isolation and power sequencing of the power domains. The PU power domain will be handled by the generic pm domain framework. It needs a phandle to the PU regulator to turn off power when the domain is disabled, and a list of phandles to all clocks that must be enabled during powerup for reset propagation.

Signed-off-by Philipp Zabel <[email protected]>
---
 arch/arm/boot/dts/imx6qdl.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)
arch/arm/boot/dts/imx6qdl.dtsi +8 -0
index d6c69ec..7ab00a4 100644
@@ -695,6 +695,14 @@
 				reg = <0x020dc000 0x4000>;
 				interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
 					     <0 90 IRQ_TYPE_LEVEL_HIGH>;
+				pu-supply = <&reg_pu>;
+				clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
+					 <&clks IMX6QDL_CLK_GPU3D_SHADER>,
+					 <&clks IMX6QDL_CLK_GPU2D_CORE>,
+					 <&clks IMX6QDL_CLK_GPU2D_AXI>,
+					 <&clks IMX6QDL_CLK_OPENVG_AXI>,
+					 <&clks IMX6QDL_CLK_VPU_AXI>;
+				#power-domain-cells = <1>;
 			};
 
 			gpr: iomuxc-gpr at 020e0000 {
Signature · 1 line
2.1.4
author
#6 lore raw

PATCH v9 4/5 ARM: dts: imx6sl: Add power-domain information to gpc node

In reply to Philipp Zabel

The PGC that is part of GPC controls isolation and power sequencing of the power domains. The PU power domain will be handled by the generic pm domain framework. It needs a phandle to the PU regulator to turn off power when the domain is disabled and a list of clocks to be enabled during powerup for reset propagation.

Signed-off-by Philipp Zabel <[email protected]>
---
 arch/arm/boot/dts/imx6sl.dtsi | 4 ++++
 1 file changed, 4 insertions(+)
arch/arm/boot/dts/imx6sl.dtsi +4 -0
index 36ab8e0..79d2007 100644
@@ -604,6 +604,10 @@
 				compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
 				reg = <0x020dc000 0x4000>;
 				interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
+				pu-supply = <&reg_pu>;
+				clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
+					 <&clks IMX6SL_CLK_GPU2D_PODF>;
+				#power-domain-cells = <1>;
 			};
 
 			gpr: iomuxc-gpr at 020e0000 {
Signature · 1 line
2.1.4
author
#7 lore raw

PATCH v9 5/5 ARM: dts: imx6qdl: Allow disabling the PU regulator, add a enable ramp delay

In reply to Philipp Zabel

The PU regulator is enabled during boot, but not necessarily always-on. It can be disabled by the generic pm domain framework when the PU power domain is shut down. The ramp delay of 150 us might be a bit conservative, the value is taken from the Freescale kernel.

Signed-off-by Philipp Zabel <[email protected]>

---
Changes since v8:
- Removed regulator-boot-on, this depends on the bootloader

---
 arch/arm/boot/dts/imx6qdl.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/boot/dts/imx6qdl.dtsi +1 -1
index 7ab00a4..4b12ac0 100644
@@ -598,7 +598,7 @@
 					regulator-name = "vddpu";
 					regulator-min-microvolt = <725000>;
 					regulator-max-microvolt = <1450000>;
-					regulator-always-on;
+					regulator-enable-ramp-delay = <150>;
 					anatop-reg-offset = <0x140>;
 					anatop-vol-bit-shift = <9>;
 					anatop-vol-bit-width = <5>;
Signature · 1 line
2.1.4
#8 lore raw

v9 cover i.MX6 PU power domain support

In reply to Philipp Zabel
Quoted 7 lines · Philipp Zabel

Philipp Zabel (6):
Documentation: Add device tree bindings for Freescale i.MX GPC
ARM: imx6: gpc: Add PU power domain for GPU/VPU
ARM: dts: imx6qdl: Add power-domain information to gpc node
ARM: dts: imx6sl: Add power-domain information to gpc node
ARM: dts: imx6qdl: Allow disabling the PU regulator, add a enable ramp
delay

Applied above 5.

Quoted 1 line

ARM: imx6: gpc: Allow PU regulator bypass

I only received 5 patches in the series.

Shawn

author
#9 lore raw

v9 cover i.MX6 PU power domain support

Hi Shawn,

Am Mittwoch, den 11.03.2015, 09:12 +0800 schrieb Shawn Guo:

Quoted 9 lines · Philipp Zabel
Quoted 7 lines

Philipp Zabel (6):
Documentation: Add device tree bindings for Freescale i.MX GPC
ARM: imx6: gpc: Add PU power domain for GPU/VPU
ARM: dts: imx6qdl: Add power-domain information to gpc node
ARM: dts: imx6sl: Add power-domain information to gpc node
ARM: dts: imx6qdl: Allow disabling the PU regulator, add a enable ramp
delay

Quoted 5 lines

Applied above 5.

Quoted 1 line

ARM: imx6: gpc: Allow PU regulator bypass

I only received 5 patches in the series.

Thank you, this shouldn't have appeared in the list at all.

Allowing regulator bypass isn't part of the series because I still didn't manage to get rid of race conditions when enabling bypass on the regulator used in two places (gpc and imx6q-cpufreq).

regards
Philipp