ARM: cache-cp15: Make sure EAE is not enabled
PATCH 1/1 ARM: cache-cp15: Make sure EAE is not enabled
This could happen if we are being chainloaded by Coreboot with LPAE enabled, as is the case on the Tegra-based Chromebooks.
--- arch/arm/lib/cache-cp15.c | 4 ++++ 1 file changed, 4 insertions(+)
arch/arm/lib/cache-cp15.c +4 -0
@@ -96,6 +96,10 @@ static inline void mmu_setup(void)dram_bank_mmu_setup (i); } +/* Make sure EAE is not enabled */ + asmvolatile ("mcr p15, 0, %0, c2, c0, 2" + : :"r" (0 ) :"memory" ); +/* Copy the page table address to cp15 */ asmvolatile ("mcr p15, 0, %0, c2, c0, 0" : :"r" (gd->arch.tlb_addr) :"memory" );
Signature · 1 line
2.3.6
PATCH 1/1 ARM: cache-cp15: Make sure EAE is not enabled
+Albert, +Marek,
Quoted 4 lines · Tomeu Vizoso
This could happen if we are being chainloaded by Coreboot with LPAE enabled, as is the case on the Tegra-based Chromebooks.
Signed-off-by Tomeu Vizoso <[email protected]>
From the documentation of recent ARM cores it looks like 0 is the reset value for that register, so explicitly ensuring it has that value seems sane. I'm wary of giving a reviewed-by though as i don't know that part of u-boot well enough to say it's the right spot.
However, as we're now using successfully using a Nyan big board with this u-boot patch in kernelci[0] i can happily say:
0: http://kernelci.org/boot/tegra124-nyan-big/
Quoted 19 lines
--- arch/arm/lib/cache-cp15.c | 4 ++++ 1 file changed, 4 insertions(+)arch/arm/lib/cache-cp15.c +4
-0@@ -96,6 +96,10 @@ static inline void mmu_setup(void)dram_bank_mmu_setup (i); } +/* Make sure EAE is not enabled */ + asmvolatile ("mcr p15, 0, %0, c2, c0, 2" + : :"r" (0 ) :"memory" ); +/* Copy the page table address to cp15 */ asmvolatile ("mcr p15, 0, %0, c2, c0, 0" : :"r" (gd->arch.tlb_addr) :"memory" );
PATCH 1/1 ARM: cache-cp15: Make sure EAE is not enabled
Hello,
any news on this one?
Thanks,
Tomeu
Quoted 46 lines · Sjoerd Simons
+Albert, +Marek,
Quoted 4 lines · Tomeu Vizoso
This could happen if we are being chainloaded by Coreboot with LPAE enabled, as is the case on the Tegra-based Chromebooks.
Signed-off-by Tomeu Vizoso <[email protected]>From the documentation of recent ARM cores it looks like 0 is the reset value for that register, so explicitly ensuring it has that value seems sane. I'm wary of giving a reviewed-by though as i don't know that part of u-boot well enough to say it's the right spot.
However, as we're now using successfully using a Nyan big board with this u-boot patch in kernelci[0] i can happily say:
Tested-by Sjoerd Simons <[email protected]>0: http://kernelci.org/boot/tegra124-nyan-big/
Quoted 9 lines
--- arch/arm/lib/cache-cp15.c | 4 ++++ 1 file changed, 4 insertions(+)arch/arm/lib/cache-cp15.c +0
-0arch/arm/lib/cache-cp15.c static inline void mmu_setup(void) · line 105
Quoted 10 lines
arch/arm/lib/cache-cp15.c +4
-0@@ -96,6 +96,10 @@ static inline void mmu_setup(void)dram_bank_mmu_setup (i); } +/* Make sure EAE is not enabled */ + asmvolatile ("mcr p15, 0, %0, c2, c0, 2" + : :"r" (0 ) :"memory" ); +/* Copy the page table address to cp15 */ asmvolatile ("mcr p15, 0, %0, c2, c0, 0" : :"r" (gd->arch.tlb_addr) :"memory" );_______________________________________________
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PATCH 1/1 ARM: cache-cp15: Make sure EAE is not enabled
Hi,
Quoted 43 lines · Tomeu Vizoso
Hello,
any news on this one?
Thanks,
Tomeu
Quoted 33 lines · Sjoerd Simons
+Albert, +Marek,
Quoted 4 lines · Tomeu Vizoso
This could happen if we are being chainloaded by Coreboot with LPAE enabled, as is the case on the Tegra-based Chromebooks.
Signed-off-by Tomeu Vizoso <[email protected]>From the documentation of recent ARM cores it looks like 0 is the reset value for that register, so explicitly ensuring it has that value seems sane. I'm wary of giving a reviewed-by though as i don't know that part of u-boot well enough to say it's the right spot.
However, as we're now using successfully using a Nyan big board with this u-boot patch in kernelci[0] i can happily say:
Tested-by Sjoerd Simons <[email protected]>0: http://kernelci.org/boot/tegra124-nyan-big/
Quoted 12 lines
--- arch/arm/lib/cache-cp15.c | 4 ++++ 1 file changed, 4 insertions(+)arch/arm/lib/cache-cp15.c +0
-0@@ -96,6 +96,10 @@ static inline void mmu_setup(void)dram_bank_mmu_setup (i); }
Quoted 7 lines
Quoted 7 lines
arch/arm/lib/cache-cp15.c static inline void mmu_setup(void) · line 105
Quoted 7 lines
arch/arm/lib/cache-cp15.c +4
-0+/* Make sure EAE is not enabled */ + asmvolatile ("mcr p15, 0, %0, c2, c0, 2" + : :"r" (0 ) :"memory" ); +/* Copy the page table address to cp15 */ asmvolatile ("mcr p15, 0, %0, c2, c0, 0" : :"r" (gd->arch.tlb_addr) :"memory" );
Does this apply to all ARM cores? Should it have #ifdef CONFIG_ARMV7 or similar?
Regards,
Simon
PATCH 1/1 ARM: cache-cp15: Make sure EAE is not enabled
Quoted 46 lines · Simon Glass
Hi,
Quoted 43 lines · Tomeu Vizoso
Hello,
any news on this one?
Thanks,
Tomeu
Quoted 33 lines · Sjoerd Simons
+Albert, +Marek,
Quoted 4 lines · Tomeu Vizoso
This could happen if we are being chainloaded by Coreboot with LPAE enabled, as is the case on the Tegra-based Chromebooks.
Signed-off-by Tomeu Vizoso <[email protected]>From the documentation of recent ARM cores it looks like 0 is the reset value for that register, so explicitly ensuring it has that value seems sane. I'm wary of giving a reviewed-by though as i don't know that part of u-boot well enough to say it's the right spot.
However, as we're now using successfully using a Nyan big board with this u-boot patch in kernelci[0] i can happily say:
Tested-by Sjoerd Simons <[email protected]>0: http://kernelci.org/boot/tegra124-nyan-big/
Quoted 12 lines
--- arch/arm/lib/cache-cp15.c | 4 ++++ 1 file changed, 4 insertions(+)arch/arm/lib/cache-cp15.c +0
-0@@ -96,6 +96,10 @@ static inline void mmu_setup(void)dram_bank_mmu_setup (i); }
Quoted 9 lines
Quoted 7 lines
Quoted 7 lines
arch/arm/lib/cache-cp15.c static inline void mmu_setup(void) · line 105
Quoted 7 lines
arch/arm/lib/cache-cp15.c +4
-0+/* Make sure EAE is not enabled */ + asmvolatile ("mcr p15, 0, %0, c2, c0, 2" + : :"r" (0 ) :"memory" ); +/* Copy the page table address to cp15 */ asmvolatile ("mcr p15, 0, %0, c2, c0, 0" : :"r" (gd->arch.tlb_addr) :"memory" );Does this apply to all ARM cores? Should it have #ifdef
CONFIG_ARMV7or similar?
Don't know, TBH. Resetting that register will select the TTBR0 and a page table boundary size of 16KB, which AFAICS is expected in U-Boot anyways.
On ARMv6, there isn't a EAE bit, so only the above will happen.
I cannot say if it's a good idea or not to reset the TTBCR just in case.
Thanks,
Tomeu
Quoted 6 lines
Regards,
Simon
_______________________________________________
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PATCH 1/1 ARM: cache-cp15: Make sure EAE is not enabled
Hello Tomeu,
Quoted 57 lines · Tomeu Vizoso
Quoted 46 lines · Simon Glass
Hi,
Quoted 43 lines · Tomeu Vizoso
Hello,
any news on this one?
Thanks,
Tomeu
Quoted 33 lines · Sjoerd Simons
+Albert, +Marek,
Quoted 4 lines · Tomeu Vizoso
This could happen if we are being chainloaded by Coreboot with LPAE enabled, as is the case on the Tegra-based Chromebooks.
Signed-off-by Tomeu Vizoso <[email protected]>From the documentation of recent ARM cores it looks like 0 is the reset value for that register, so explicitly ensuring it has that value seems sane. I'm wary of giving a reviewed-by though as i don't know that part of u-boot well enough to say it's the right spot.
However, as we're now using successfully using a Nyan big board with this u-boot patch in kernelci[0] i can happily say:
Tested-by Sjoerd Simons <[email protected]>0: http://kernelci.org/boot/tegra124-nyan-big/
Quoted 12 lines
--- arch/arm/lib/cache-cp15.c | 4 ++++ 1 file changed, 4 insertions(+)arch/arm/lib/cache-cp15.c +0
-0@@ -96,6 +96,10 @@ static inline void mmu_setup(void)dram_bank_mmu_setup (i); }Quoted 9 lines
Quoted 7 lines
Quoted 7 lines
arch/arm/lib/cache-cp15.c static inline void mmu_setup(void) · line 105
Quoted 7 lines
arch/arm/lib/cache-cp15.c +4
-0+/* Make sure EAE is not enabled */ + asmvolatile ("mcr p15, 0, %0, c2, c0, 2" + : :"r" (0 ) :"memory" ); +/* Copy the page table address to cp15 */ asmvolatile ("mcr p15, 0, %0, c2, c0, 0" : :"r" (gd->arch.tlb_addr) :"memory" );Does this apply to all ARM cores? Should it have #ifdef
CONFIG_ARMV7or similar?
Quoted 7 lines
Don't know, TBH. Resetting that register will select the TTBR0 and a page table boundary size of 16KB, which AFAICS is expected in U-Boot anyways.
On ARMv6, there isn't a EAE bit, so only the above will happen.
I cannot say if it's a good idea or not to reset the TTBCR just in case.
Then the best is to just change in that register what must be changed. If EAE is the only bit in TTBCR that needs resetting for the Nyan big board to boot properly, then I would prefer that all other bits be left untouched.
Quoted 3 lines
Thanks,
Tomeu
Amicalement,
Signature · 1 line
Albert.