Patch "MIPS: asm: asm-eva: Introduce kernel load/store variants" has been added to the 3.19-stable tree
Subsystems (2)
This is a note to let you know that I've just added the patch titled
MIPS: asm: asm-eva: Introduce kernel load/store variants
to the 3.19-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
mips-asm-asm-eva-introduce-kernel-load-store-variants.patch
and it can be found in the queue-3.19 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From
60cd7e08e453bc6828ac4b539f949e4acd80f143Mon Sep 17 00:00:00 2001
From: Markos Chandras <[email protected]>
Date: Mon, 9 Mar 2015 14:54:49 +0000
Subject: MIPS: asm: asm-eva: Introduce kernel load/store variants
From: Markos Chandras <[email protected]>
commit 60cd7e08e453bc6828ac4b539f949e4acd80f143 upstream.
Introduce new macros for kernel load/store variants which will be used to perform regular kernel space load/store operations in EVA mode.
Signed-off-by Markos Chandras <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/9500/
Signed-off-by Ralf Baechle <[email protected]>
Signed-off-by Greg Kroah-Hartman <[email protected]>
--- arch/mips/include/asm/asm-eva.h | 137 +++++++++++++++++++++++++++------------- 1 file changed, 93 insertions(+), 44 deletions(-)
arch/mips/include/asm/asm-eva.h +93 -44
@@ -11,6 +11,36 @@#define __ASM_ASM_EVA_H#ifndef __ASSEMBLY__ + +/* Kernel variants */ + +#define kernel_cache (op, base) "cache " op ", " base "\n" +#define kernel_ll (reg, addr) "ll " reg ", " addr "\n" +#define kernel_sc (reg, addr) "sc " reg ", " addr "\n" +#define kernel_lw (reg, addr) "lw " reg ", " addr "\n" +#define kernel_lwl (reg, addr) "lwl " reg ", " addr "\n" +#define kernel_lwr (reg, addr) "lwr " reg ", " addr "\n" +#define kernel_lh (reg, addr) "lh " reg ", " addr "\n" +#define kernel_lb (reg, addr) "lb " reg ", " addr "\n" +#define kernel_lbu (reg, addr) "lbu " reg ", " addr "\n" +#define kernel_sw (reg, addr) "sw " reg ", " addr "\n" +#define kernel_swl (reg, addr) "swl " reg ", " addr "\n" +#define kernel_swr (reg, addr) "swr " reg ", " addr "\n" +#define kernel_sh (reg, addr) "sh " reg ", " addr "\n" +#define kernel_sb (reg, addr) "sb " reg ", " addr "\n" + +#ifdef CONFIG_32BIT +/* +* No 'sd' or 'ld' instructions in 32-bit but the code will +* do the correct thing +*/ +#define kernel_sd (reg, addr) user_sw(reg, addr) +#define kernel_ld (reg, addr) user_lw(reg, addr) +#else +#define kernel_sd (reg, addr) "sd " reg", " addr "\n" +#define kernel_ld (reg, addr) "ld " reg", " addr "\n" +#endif /* CONFIG_32BIT */ +#ifdef CONFIG_EVA #define __BUILD_EVA_INSN (insn, reg, addr) \
@@ -41,37 +71,60 @@#else -#define user_cache (op, base) "cache " op ", " base "\n" -#define user_ll (reg, addr) "ll " reg ", " addr "\n" -#define user_sc (reg, addr) "sc " reg ", " addr "\n" -#define user_lw (reg, addr) "lw " reg ", " addr "\n" -#define user_lwl (reg, addr) "lwl " reg ", " addr "\n" -#define user_lwr (reg, addr) "lwr " reg ", " addr "\n" -#define user_lh (reg, addr) "lh " reg ", " addr "\n" -#define user_lb (reg, addr) "lb " reg ", " addr "\n" -#define user_lbu (reg, addr) "lbu " reg ", " addr "\n" -#define user_sw (reg, addr) "sw " reg ", " addr "\n" -#define user_swl (reg, addr) "swl " reg ", " addr "\n" -#define user_swr (reg, addr) "swr " reg ", " addr "\n" -#define user_sh (reg, addr) "sh " reg ", " addr "\n" -#define user_sb (reg, addr) "sb " reg ", " addr "\n" +#define user_cache (op, base) kernel_cache(op, base) +#define user_ll (reg, addr) kernel_ll(reg, addr) +#define user_sc (reg, addr) kernel_sc(reg, addr) +#define user_lw (reg, addr) kernel_lw(reg, addr) +#define user_lwl (reg, addr) kernel_lwl(reg, addr) +#define user_lwr (reg, addr) kernel_lwr(reg, addr) +#define user_lh (reg, addr) kernel_lh(reg, addr) +#define user_lb (reg, addr) kernel_lb(reg, addr) +#define user_lbu (reg, addr) kernel_lbu(reg, addr) +#define user_sw (reg, addr) kernel_sw(reg, addr) +#define user_swl (reg, addr) kernel_swl(reg, addr) +#define user_swr (reg, addr) kernel_swr(reg, addr) +#define user_sh (reg, addr) kernel_sh(reg, addr) +#define user_sb (reg, addr) kernel_sb(reg, addr)#ifdef CONFIG_32BIT -/* -* No 'sd' or 'ld' instructions in 32-bit but the code will -* do the correct thing -*/ -#define user_sd (reg, addr) user_sw(reg, addr) -#define user_ld (reg, addr) user_lw(reg, addr) +#define user_sd (reg, addr) kernel_sw(reg, addr) +#define user_ld (reg, addr) kernel_lw(reg, addr)#else -#define user_sd (reg, addr) "sd " reg", " addr "\n" -#define user_ld (reg, addr) "ld " reg", " addr "\n" +#define user_sd (reg, addr) kernel_sd(reg, addr) +#define user_ld (reg, addr) kernel_ld(reg, addr)#endif /* CONFIG_32BIT */ #endif /* CONFIG_EVA */ #else /* __ASSEMBLY__ */ +#define kernel_cache (op, base) cache op, base +#define kernel_ll (reg, addr) ll reg, addr +#define kernel_sc (reg, addr) sc reg, addr +#define kernel_lw (reg, addr) lw reg, addr +#define kernel_lwl (reg, addr) lwl reg, addr +#define kernel_lwr (reg, addr) lwr reg, addr +#define kernel_lh (reg, addr) lh reg, addr +#define kernel_lb (reg, addr) lb reg, addr +#define kernel_lbu (reg, addr) lbu reg, addr +#define kernel_sw (reg, addr) sw reg, addr +#define kernel_swl (reg, addr) swl reg, addr +#define kernel_swr (reg, addr) swr reg, addr +#define kernel_sh (reg, addr) sh reg, addr +#define kernel_sb (reg, addr) sb reg, addr + +#ifdef CONFIG_32BIT +/* +* No 'sd' or 'ld' instructions in 32-bit but the code will +* do the correct thing +*/ +#define kernel_sd (reg, addr) user_sw(reg, addr) +#define kernel_ld (reg, addr) user_lw(reg, addr) +#else +#define kernel_sd (reg, addr) sd reg, addr +#define kernel_ld (reg, addr) ld reg, addr +#endif /* CONFIG_32BIT */ +#ifdef CONFIG_EVA #define __BUILD_EVA_INSN (insn, reg, addr) \
@@ -101,31 +154,27 @@#define user_sd (reg, addr) user_sw(reg, addr)#else -#define user_cache (op, base) cache op, base -#define user_ll (reg, addr) ll reg, addr -#define user_sc (reg, addr) sc reg, addr -#define user_lw (reg, addr) lw reg, addr -#define user_lwl (reg, addr) lwl reg, addr -#define user_lwr (reg, addr) lwr reg, addr -#define user_lh (reg, addr) lh reg, addr -#define user_lb (reg, addr) lb reg, addr -#define user_lbu (reg, addr) lbu reg, addr -#define user_sw (reg, addr) sw reg, addr -#define user_swl (reg, addr) swl reg, addr -#define user_swr (reg, addr) swr reg, addr -#define user_sh (reg, addr) sh reg, addr -#define user_sb (reg, addr) sb reg, addr +#define user_cache (op, base) kernel_cache(op, base) +#define user_ll (reg, addr) kernel_ll(reg, addr) +#define user_sc (reg, addr) kernel_sc(reg, addr) +#define user_lw (reg, addr) kernel_lw(reg, addr) +#define user_lwl (reg, addr) kernel_lwl(reg, addr) +#define user_lwr (reg, addr) kernel_lwr(reg, addr) +#define user_lh (reg, addr) kernel_lh(reg, addr) +#define user_lb (reg, addr) kernel_lb(reg, addr) +#define user_lbu (reg, addr) kernel_lbu(reg, addr) +#define user_sw (reg, addr) kernel_sw(reg, addr) +#define user_swl (reg, addr) kernel_swl(reg, addr) +#define user_swr (reg, addr) kernel_swr(reg, addr) +#define user_sh (reg, addr) kernel_sh(reg, addr) +#define user_sb (reg, addr) kernel_sb(reg, addr)#ifdef CONFIG_32BIT -/* -* No 'sd' or 'ld' instructions in 32-bit but the code will -* do the correct thing -*/ -#define user_sd (reg, addr) user_sw(reg, addr) -#define user_ld (reg, addr) user_lw(reg, addr) +#define user_sd (reg, addr) kernel_sw(reg, addr) +#define user_ld (reg, addr) kernel_lw(reg, addr)#else -#define user_sd (reg, addr) sd reg, addr -#define user_ld (reg, addr) ld reg, addr +#define user_sd (reg, addr) kernel_sd(reg, addr) +#define user_ld (reg, addr) kernel_sd(reg, addr)#endif /* CONFIG_32BIT */ #endif /* CONFIG_EVA */
Patches currently in stable-queue which might be from [email protected] are
queue-3.19/mips-unaligned-fix-regular-load-store-instruction-emulation-for-eva.patch queue-3.19/mips-malta-detect-and-fix-bad-memsize-values.patch queue-3.19/mips-asm-asm-eva-introduce-kernel-load-store-variants.patch