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Patch "arm64: head.S: ensure visibility of page tables" has been added to the 4.0-stable tree

PATCH [email protected] 1 participant 1 message May 2, 2015

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This is a note to let you know that I've just added the patch titled

arm64: head.S: ensure visibility of page tables

to the 4.0-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
arm64-head.s-ensure-visibility-of-page-tables.patch
and it can be found in the queue-4.0 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

Quoted 1 line

From 91d57155dc5ab4b311624b7ee570339b6af19ad5 Mon Sep 17 00:00:00 2001

From: Mark Rutland <[email protected]>
Date: Tue, 24 Mar 2015 13:50:27 +0000
Subject: arm64: head.S: ensure visibility of page tables

From: Mark Rutland <[email protected]>

commit 91d57155dc5ab4b311624b7ee570339b6af19ad5 upstream.

After writing the page tables, we use __inval_cache_range to invalidate any stale cache entries. Strongly Ordered memory accesses are not ordered w.r.t. cache maintenance instructions, and hence explicit memory barriers are required to provide this ordering. However, __inval_cache_range was written to be used on Normal Cacheable memory once the MMU and caches are on, and does not have any barriers prior to the DC instructions.

This patch adds a DMB between the page tables being written and the corresponding cachelines being invalidated, ensuring that the invalidation makes the new data visible to subsequent cacheable accesses. A barrier is not required before the prior invalidate as we do not access the page table memory area prior to this, and earlier barriers in preserve_boot_args and set_cpu_boot_mode_flag ensures ordering w.r.t. any stores performed prior to entering Linux.

Cc Catalin Marinas <[email protected]>
Cc Will Deacon <[email protected]>
Fixes c218bca74eeafa2f ("arm64: Relax the kernel cache requirements for boot")
---
 arch/arm64/kernel/head.S |    1 +
 1 file changed, 1 insertion(+)
arch/arm64/kernel/head.S +1 -0
@@ -426,6 +426,7 @@ __create_page_tables:
 	 */
 	mov	x0, x25
 	add	x1, x26, #SWAPPER_DIR_SIZE
+	dmb	sy
 	bl	__inval_cache_range
 
 	mov	lr, x27

Patches currently in stable-queue which might be from [email protected] are

queue-4.0/arm64-head.s-ensure-visibility-of-page-tables.patch queue-4.0/arm64-apply-alternatives-for-smp-kernels.patch queue-4.0/arm64-errata-add-workaround-for-cortex-a53-erratum-845719.patch queue-4.0/drivers-base-cacheinfo-validate-device-node-for-all-the-caches.patch