drm/amdkfd: Use new struct for asic specific ops

PATCH In review Oded Gabbay 2 participants 4 messages May 5, 2015 – May 7, 2015

Subsystems (3)

DRM drivers Radeon and amdgpu DRM drivers AMD KFD

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Oded Gabbay

author

2015-05-05 09:03 UTC #0 lore raw

PATCH 1/2 drm/amdkfd: Use new struct for asic specific ops

This patch creates a new structure for asic specific operations, instead of using the existing structure of operations.

This is done to make the code flow more logic, readable and maintainable.

The change is done only to the device queue manager module at this point.

Signed-off-by Oded Gabbay <[email protected]>

---
 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h  | 18 +++++++++++++++---
 .../gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c  |  2 +-
 .../gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c   |  2 +-
 3 files changed, 17 insertions(+), 5 deletions(-)

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +15 -3

index 488f51d..650ae1c 100644
@@ -120,6 +120,18 @@ struct device_queue_manager_ops {
 					   uint64_t alternate_aperture_size);
 };
 
+struct device_queue_manager_asic_ops {
+	int	(*register_process)(struct device_queue_manager *dqm,
+					struct qcm_process_device *qpd);
+	int	(*initialize)(struct device_queue_manager *dqm);
+	bool	(*set_cache_memory_policy)(struct device_queue_manager *dqm,
+					   struct qcm_process_device *qpd,
+					   enum cache_policy default_policy,
+					   enum cache_policy alternate_policy,
+					   void __user *alternate_aperture_base,
+					   uint64_t alternate_aperture_size);
+};
+
 /**
  * struct device_queue_manager
  *

@@ -134,7 +146,7 @@ struct device_queue_manager_ops {
 
 struct device_queue_manager {
 	struct device_queue_manager_ops ops;
-	struct device_queue_manager_ops ops_asic_specific;
+	struct device_queue_manager_asic_ops ops_asic_specific;
 
 	struct mqd_manager	*mqds[KFD_MQD_TYPE_MAX];
 	struct packet_manager	packets;

@@ -157,8 +169,8 @@ struct device_queue_manager {
 	bool			active_runlist;
 };
 
-void device_queue_manager_init_cik(struct device_queue_manager_ops *ops);
-void device_queue_manager_init_vi(struct device_queue_manager_ops *ops);
+void device_queue_manager_init_cik(struct device_queue_manager_asic_ops *ops);
+void device_queue_manager_init_vi(struct device_queue_manager_asic_ops *ops);
 void program_sh_mem_settings(struct device_queue_manager *dqm,
 					struct qcm_process_device *qpd);
 int init_pipelines(struct device_queue_manager *dqm,

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c +1 -1

index 5469efe..292d13f 100644
@@ -34,7 +34,7 @@ static int register_process_cik(struct device_queue_manager *dqm,
 					struct qcm_process_device *qpd);
 static int initialize_cpsch_cik(struct device_queue_manager *dqm);
 
-void device_queue_manager_init_cik(struct device_queue_manager_ops *ops)
+void device_queue_manager_init_cik(struct device_queue_manager_asic_ops *ops)
 {
 	ops->set_cache_memory_policy = set_cache_memory_policy_cik;
 	ops->register_process = register_process_cik;

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c +1 -1

index 20553dc..8b00ccf 100644
@@ -33,7 +33,7 @@ static int register_process_vi(struct device_queue_manager *dqm,
 					struct qcm_process_device *qpd);
 static int initialize_cpsch_vi(struct device_queue_manager *dqm);
 
-void device_queue_manager_init_vi(struct device_queue_manager_ops *ops)
+void device_queue_manager_init_vi(struct device_queue_manager_asic_ops *ops)
 {
 	pr_warn("amdkfd: VI DQM is not currently supported\n");

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1.9.1

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Oded Gabbay

author

2015-05-05 09:03 UTC #1 lore raw

PATCH 2/2 drm/amdkfd: make the sdma vm init to be asic specific

Signed-off-by Oded Gabbay <[email protected]>

---
 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c    | 15 +--------------
 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h    |  3 +++
 .../gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c    | 16 ++++++++++++++++
 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c |  8 ++++++++
 4 files changed, 28 insertions(+), 14 deletions(-)

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +1 ~~-14~~

index 69af73f..1eb1022 100644
@@ -614,19 +614,6 @@ static void deallocate_sdma_queue(struct device_queue_manager *dqm,
 	set_bit(sdma_queue_id, (unsigned long *)&dqm->sdma_bitmap);
 }
 
-static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q,
-				struct qcm_process_device *qpd)
-{
-	uint32_t value = SDMA_ATC;
-
-	if (q->process->is_32bit_user_mode)
-		value |= SDMA_VA_PTR32 | get_sh_mem_bases_32(qpd_to_pdd(qpd));
-	else
-		value |= SDMA_VA_SHARED_BASE(get_sh_mem_bases_nybble_64(
-							qpd_to_pdd(qpd)));
-	q->properties.sdma_vm_addr = value;
-}
-
 static int create_sdma_queue_nocpsch(struct device_queue_manager *dqm,
 					struct queue *q,
 					struct qcm_process_device *qpd)

@@ -649,7 +636,7 @@ static int create_sdma_queue_nocpsch(struct device_queue_manager *dqm,
 	pr_debug("     sdma queue id: %d\n", q->properties.sdma_queue_id);
 	pr_debug("     sdma engine id: %d\n", q->properties.sdma_engine_id);
 
-	init_sdma_vm(dqm, q, qpd);
+	dqm->ops_asic_specific.init_sdma_vm(dqm, q, qpd);
 	retval = mqd->init_mqd(mqd, &q->mqd, &q->mqd_mem_obj,
 				&q->gart_mqd_addr, &q->properties);
 	if (retval != 0) {

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +3 -0

index 650ae1c..57278e2 100644
@@ -130,6 +130,9 @@ struct device_queue_manager_asic_ops {
 					   enum cache_policy alternate_policy,
 					   void __user *alternate_aperture_base,
 					   uint64_t alternate_aperture_size);
+	void	(*init_sdma_vm)(struct device_queue_manager *dqm,
+				struct queue *q,
+				struct qcm_process_device *qpd);
 };
 
 /**

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c +16 -0

index 292d13f..9ce8a20 100644
@@ -33,12 +33,15 @@ static bool set_cache_memory_policy_cik(struct device_queue_manager *dqm,
 static int register_process_cik(struct device_queue_manager *dqm,
 					struct qcm_process_device *qpd);
 static int initialize_cpsch_cik(struct device_queue_manager *dqm);
+static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q,
+				struct qcm_process_device *qpd);
 
 void device_queue_manager_init_cik(struct device_queue_manager_asic_ops *ops)
 {
 	ops->set_cache_memory_policy = set_cache_memory_policy_cik;
 	ops->register_process = register_process_cik;
 	ops->initialize = initialize_cpsch_cik;
+	ops->init_sdma_vm = init_sdma_vm;
 }
 
 static uint32_t compute_sh_mem_bases_64bit(unsigned int top_address_nybble)

@@ -129,6 +132,19 @@ static int register_process_cik(struct device_queue_manager *dqm,
 	return 0;
 }
 
+static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q,
+				struct qcm_process_device *qpd)
+{
+	uint32_t value = SDMA_ATC;
+
+	if (q->process->is_32bit_user_mode)
+		value |= SDMA_VA_PTR32 | get_sh_mem_bases_32(qpd_to_pdd(qpd));
+	else
+		value |= SDMA_VA_SHARED_BASE(get_sh_mem_bases_nybble_64(
+							qpd_to_pdd(qpd)));
+	q->properties.sdma_vm_addr = value;
+}
+
 static int initialize_cpsch_cik(struct device_queue_manager *dqm)
 {
 	return init_pipelines(dqm, get_pipes_num(dqm), get_first_pipe(dqm));

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c +8 -0

index 8b00ccf..4c15212 100644
@@ -32,6 +32,8 @@ static bool set_cache_memory_policy_vi(struct device_queue_manager *dqm,
 static int register_process_vi(struct device_queue_manager *dqm,
 					struct qcm_process_device *qpd);
 static int initialize_cpsch_vi(struct device_queue_manager *dqm);
+static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q,
+				struct qcm_process_device *qpd);
 
 void device_queue_manager_init_vi(struct device_queue_manager_asic_ops *ops)
 {

@@ -40,6 +42,7 @@ void device_queue_manager_init_vi(struct device_queue_manager_asic_ops *ops)
 	ops->set_cache_memory_policy = set_cache_memory_policy_vi;
 	ops->register_process = register_process_vi;
 	ops->initialize = initialize_cpsch_vi;
+	ops->init_sdma_vm = init_sdma_vm;
 }
 
 static bool set_cache_memory_policy_vi(struct device_queue_manager *dqm,

@@ -58,6 +61,11 @@ static int register_process_vi(struct device_queue_manager *dqm,
 	return -1;
 }
 
+static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q,
+				struct qcm_process_device *qpd)
+{
+}
+
 static int initialize_cpsch_vi(struct device_queue_manager *dqm)
 {
 	return 0;

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Alex Deucher

Reviewed-by on v1 2/2

2015-05-05 16:28 UTC #2 lore raw

Re: [PATCH 2/2] drm/amdkfd: make the sdma vm init to be asic specific

Quoted 46 lines · Oded Gabbay

Signed-off-by Oded Gabbay <[email protected]>

---
 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c    | 15 +--------------
 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h    |  3 +++
 .../gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c    | 16 ++++++++++++++++
 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c |  8 ++++++++
 4 files changed, 28 insertions(+), 14 deletions(-)

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +1 ~~-14~~

index 69af73f..1eb1022 100644
@@ -614,19 +614,6 @@ static void deallocate_sdma_queue(struct device_queue_manager *dqm,
        set_bit(sdma_queue_id, (unsigned long *)&dqm->sdma_bitmap);
 }
 
-static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q,
-                               struct qcm_process_device *qpd)
-{
-       uint32_t value = SDMA_ATC;
-
-       if (q->process->is_32bit_user_mode)
-               value |= SDMA_VA_PTR32 | get_sh_mem_bases_32(qpd_to_pdd(qpd));
-       else
-               value |= SDMA_VA_SHARED_BASE(get_sh_mem_bases_nybble_64(
-                                                       qpd_to_pdd(qpd)));
-       q->properties.sdma_vm_addr = value;
-}
-
 static int create_sdma_queue_nocpsch(struct device_queue_manager *dqm,
                                        struct queue *q,
                                        struct qcm_process_device *qpd)

@@ -649,7 +636,7 @@ static int create_sdma_queue_nocpsch(struct device_queue_manager *dqm,
        pr_debug("     sdma queue id: %d\n", q->properties.sdma_queue_id);
        pr_debug("     sdma engine id: %d\n", q->properties.sdma_engine_id);
 
-       init_sdma_vm(dqm, q, qpd);
+       dqm->ops_asic_specific.init_sdma_vm(dqm, q, qpd);
        retval = mqd->init_mqd(mqd, &q->mqd, &q->mqd_mem_obj,
                                &q->gart_mqd_addr, &q->properties);
        if (retval != 0) {

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +0 -0

index 650ae1c..57278e2 100644

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h struct device_queue_manager_asic_ops { · line 135

Quoted 6 lines

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +3 -0

@@ -130,6 +130,9 @@ struct device_queue_manager_asic_ops {
                                           enum cache_policy alternate_policy,
                                           void __user *alternate_aperture_base,
                                           uint64_t alternate_aperture_size);
+       void    (*init_sdma_vm)(struct device_queue_manager *dqm,
+                               struct queue *q,
+                               struct qcm_process_device *qpd);

Maybe call it, init_vm() in cause you need to do something queue specific for other rings? Either way, this series is:

Reviewed-by Alex Deucher <[email protected]>

Quoted 79 lines

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +0 -0

 };
 
 /**

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c +16 -0

index 292d13f..9ce8a20 100644
@@ -33,12 +33,15 @@ static bool set_cache_memory_policy_cik(struct device_queue_manager *dqm,
 static int register_process_cik(struct device_queue_manager *dqm,
                                        struct qcm_process_device *qpd);
 static int initialize_cpsch_cik(struct device_queue_manager *dqm);
+static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q,
+                               struct qcm_process_device *qpd);
 
 void device_queue_manager_init_cik(struct device_queue_manager_asic_ops *ops)
 {
        ops->set_cache_memory_policy = set_cache_memory_policy_cik;
        ops->register_process = register_process_cik;
        ops->initialize = initialize_cpsch_cik;
+       ops->init_sdma_vm = init_sdma_vm;
 }
 
 static uint32_t compute_sh_mem_bases_64bit(unsigned int top_address_nybble)

@@ -129,6 +132,19 @@ static int register_process_cik(struct device_queue_manager *dqm,
        return 0;
 }
 
+static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q,
+                               struct qcm_process_device *qpd)
+{
+       uint32_t value = SDMA_ATC;
+
+       if (q->process->is_32bit_user_mode)
+               value |= SDMA_VA_PTR32 | get_sh_mem_bases_32(qpd_to_pdd(qpd));
+       else
+               value |= SDMA_VA_SHARED_BASE(get_sh_mem_bases_nybble_64(
+                                                       qpd_to_pdd(qpd)));
+       q->properties.sdma_vm_addr = value;
+}
+
 static int initialize_cpsch_cik(struct device_queue_manager *dqm)
 {
        return init_pipelines(dqm, get_pipes_num(dqm), get_first_pipe(dqm));

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c +8 -1

index 8b00ccf..4c15212 100644
@@ -32,6 +32,8 @@ static bool set_cache_memory_policy_vi(struct device_queue_manager *dqm,
 static int register_process_vi(struct device_queue_manager *dqm,
                                        struct qcm_process_device *qpd);
 static int initialize_cpsch_vi(struct device_queue_manager *dqm);
+static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q,
+                               struct qcm_process_device *qpd);
 
 void device_queue_manager_init_vi(struct device_queue_manager_asic_ops *ops)
 {

@@ -40,6 +42,7 @@ void device_queue_manager_init_vi(struct device_queue_manager_asic_ops *ops)
        ops->set_cache_memory_policy = set_cache_memory_policy_vi;
        ops->register_process = register_process_vi;
        ops->initialize = initialize_cpsch_vi;
+       ops->init_sdma_vm = init_sdma_vm;
 }
 
 static bool set_cache_memory_policy_vi(struct device_queue_manager *dqm,

@@ -58,6 +61,11 @@ static int register_process_vi(struct device_queue_manager *dqm,
        return -1;
 }
 
+static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q,
+                               struct qcm_process_device *qpd)
+{
+}
+
 static int initialize_cpsch_vi(struct device_queue_manager *dqm)
 {
        return 0;
--

1.9.1

Quoted 4 lines

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Oded Gabbay

author

2015-05-07 14:45 UTC #3 lore raw

Re: [PATCH 2/2] drm/amdkfd: make the sdma vm init to be asic specific

Quoted 10 lines · Alex Deucher

Quoted 2 lines · Oded Gabbay
Signed-off-by Oded Gabbay <[email protected]>
---
Maybe call it, init_vm() in cause you need to do something queue specific for other rings? Either way, this series is:
Reviewed-by Alex Deucher <[email protected]>
Quoted 2 lines
};

From what I currently know, this is only required for sdma queues, because the vm info is in a register per queue. In compute queues, there are shared registers (sh_mem_*) so we don't need to init something per queue.

Signature · 5 lines

          Oded
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