MIPS and SSB fixes for 4.0-stable
Subsystems (7)
v2 cover MIPS and SSB fixes for 4.0-stable
This is a large number of fixes for MIPS plus one patch for the SSB bus that didn't make 4.0. All of these patches are in 4.1
Changes from v1:
- Dropped patches that got already applied to v4.0.2.
Aaro Koskinen (2):
MIPS: OCTEON: dma-octeon: fix OHCI USB config check
MIPS: OCTEON: fix PCI interrupt mapping for D-Link DSR-1000N
Adrien Schildknecht (1):
SSB: fix Kconfig dependencies
Alexander Sverdlin (1):
MIPS: Octeon: Remove udelay() causing huge IRQ latency
Chandrakala Chavva (1):
MIPS: OCTEON: Use correct CSR to soft reset
Ganesan Ramalingam (1):
MIPS: Netlogic: Fix for SATA PHY init
John Crispin (2):
MIPS: ralink: Fix bad config symbol in PCI makefile.
MIPS: ralink: add missing symbol for RALINK_ILL_ACC
Lars Persson (2):
Revert "MIPS: Remove race window in page fault handling"
MIPS: Fix race condition in lazy cache flushing.
Markos Chandras (7):
MIPS: Kconfig: Fix typo for the r2-to-r6 emulator kernel parameter
MIPS: r4kcache: Use correct base register for MIPS R6 cache flushes
MIPS: asm: spinlock: Fix addiu instruction for R10000_LLSC_WAR case
MIPS: kernel: entry.S: Set correct ISA level for mips_ihb
MIPS: Kconfig: Disable SMP/CPS for 64-bit
MIPS: asm: elf: Set O32 default FPU flags
MIPS: Makefile: Fix MIPS ASE detection code
Nicolas Schichan (1):
MIPS: BCM63xx: Move bcm63xx_gpio_init() to bcm63xx_register_devices().
Niklas Cassel (1):
MIPS: smp-cps: cpu_set FPU mask if FPU present
Rafał Miłecki (1):
MIPS: BCM47XX: Fix detecting Microsoft MN-700 & Asus WL500G
Ralf Baechle (3):
MIPS: Fix cpu_has_mips_r2_exec_hazard.
MIPS: Octeon: Delete override of cpu_has_mips_r2_exec_hazard. Revert "MIPS: Avoid pipeline stalls on some MIPS32R2 cores."
arch/mips/Kconfig | 4 +- arch/mips/Makefile | 14 +++- arch/mips/bcm47xx/board.c | 4 +- arch/mips/bcm63xx/prom.c | 4 - arch/mips/bcm63xx/setup.c | 4 + arch/mips/cavium-octeon/dma-octeon.c | 2 +- arch/mips/cavium-octeon/setup.c | 5 +- arch/mips/include/asm/cacheflush.h | 38 +++++---- arch/mips/include/asm/cpu-features.h | 33 +++++++- arch/mips/include/asm/elf.h | 5 ++ .../asm/mach-cavium-octeon/cpu-feature-overrides.h | 1 - arch/mips/include/asm/octeon/cvmx.h | 8 -- arch/mips/include/asm/octeon/pci-octeon.h | 3 - arch/mips/include/asm/pgtable.h | 9 ++- arch/mips/include/asm/r4kcache.h | 89 +++++++++++----------- arch/mips/include/asm/spinlock.h | 2 +- arch/mips/kernel/entry.S | 3 +- arch/mips/kernel/smp-cps.c | 6 ++ arch/mips/mm/cache.c | 39 +++++----- arch/mips/mm/tlbex.c | 21 +---- arch/mips/netlogic/xlp/ahci-init-xlp2.c | 13 ++++ arch/mips/pci/Makefile | 2 +- arch/mips/pci/pci-octeon.c | 8 +- arch/mips/pci/pcie-octeon.c | 8 -- arch/mips/ralink/Kconfig | 5 ++ drivers/ssb/Kconfig | 1 + 26 files changed, 186 insertions(+), 145 deletions(-)
Signature · 1 line
1.9.3
PATCH v2 1/23 MIPS: BCM63xx: Move bcm63xx_gpio_init() to bcm63xx_register_devices().
From: Nicolas Schichan <[email protected]>
Commit 2ec459f2a77b808c1e5a3616c88b613d3f720c8d upstream.
When called from prom init code, bcm63xx_gpio_init() will fail as it will call gpiochip_add() which relies on a working kmalloc() to alloc the gpio_desc array and kmalloc is not useable yet at prom init time.
Move bcm63xx_gpio_init() to bcm63xx_register_devices() (an arch_initcall) where kmalloc works.
Patchwork: https://patchwork.linux-mips.org/patch/9530/
--- arch/mips/bcm63xx/prom.c | 4 ---- arch/mips/bcm63xx/setup.c | 4 ++++ 2 files changed, 4 insertions(+), 4 deletions(-)
arch/mips/bcm63xx/prom.c +0 -4
@@ -17,7 +17,6 @@#include <bcm63xx_cpu.h> #include <bcm63xx_io.h> #include <bcm63xx_regs.h> -#include <bcm63xx_gpio.h> void __init prom_init (void ) {
@@ -53,9 +52,6 @@ void __init prom_init(void) reg &= ~mask;bcm_perf_writel (reg,PERF_CKCTL_REG ); -/* register gpiochip */ -bcm63xx_gpio_init (); -/* do low level board init */ board_prom_init ();
arch/mips/bcm63xx/setup.c +4 -0
@@ -20,6 +20,7 @@#include <bcm63xx_cpu.h> #include <bcm63xx_regs.h> #include <bcm63xx_io.h> +#include <bcm63xx_gpio.h> void bcm63xx_machine_halt (void ) {
@@ -160,6 +161,9 @@ void __init plat_mem_setup(void)int __init bcm63xx_register_devices (void ) { +/* register gpiochip */ +bcm63xx_gpio_init (); +return board_register_devices (); }
Signature · 1 line
1.9.3
Patch "MIPS: BCM63xx: Move bcm63xx_gpio_init() to bcm63xx_register_devices()." has been added to the 4.0-stable tree
This is a note to let you know that I've just added the patch titled
MIPS: BCM63xx: Move bcm63xx_gpio_init() to bcm63xx_register_devices().
to the 4.0-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
mips-bcm63xx-move-bcm63xx_gpio_init-to-bcm63xx_register_devices.patch
and it can be found in the queue-4.0 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From [email protected] Fri May 8 16:23:10 2015
From: Ralf Baechle <[email protected]>
Date: Thu, 12 Mar 2015 17:00:58 +0100
Subject: MIPS: BCM63xx: Move bcm63xx_gpio_init() to bcm63xx_register_devices().
To: [email protected]
Message-ID: <9a195d2d1a1ae559288322adbe2c19a837e31d7e.1431087908.git.ralf@linux-mips.org>
From: Nicolas Schichan <[email protected]>
Commit 2ec459f2a77b808c1e5a3616c88b613d3f720c8d upstream.
When called from prom init code, bcm63xx_gpio_init() will fail as it will call gpiochip_add() which relies on a working kmalloc() to alloc the gpio_desc array and kmalloc is not useable yet at prom init time.
Move bcm63xx_gpio_init() to bcm63xx_register_devices() (an arch_initcall) where kmalloc works.
Patchwork: https://patchwork.linux-mips.org/patch/9530/
--- arch/mips/bcm63xx/prom.c | 4 ---- arch/mips/bcm63xx/setup.c | 4 ++++ 2 files changed, 4 insertions(+), 4 deletions(-)
arch/mips/bcm63xx/prom.c +0 -4
@@ -17,7 +17,6 @@#include <bcm63xx_cpu.h> #include <bcm63xx_io.h> #include <bcm63xx_regs.h> -#include <bcm63xx_gpio.h> void __init prom_init (void ) {
@@ -53,9 +52,6 @@ void __init prom_init(void) reg &= ~mask;bcm_perf_writel (reg,PERF_CKCTL_REG ); -/* register gpiochip */ -bcm63xx_gpio_init (); -/* do low level board init */ board_prom_init ();
arch/mips/bcm63xx/setup.c +4 -0
@@ -20,6 +20,7 @@#include <bcm63xx_cpu.h> #include <bcm63xx_regs.h> #include <bcm63xx_io.h> +#include <bcm63xx_gpio.h> void bcm63xx_machine_halt (void ) {
@@ -160,6 +161,9 @@ void __init plat_mem_setup(void)int __init bcm63xx_register_devices (void ) { +/* register gpiochip */ +bcm63xx_gpio_init (); +return board_register_devices (); }
Patches currently in stable-queue which might be from [email protected] are
queue-4.0/mips-octeon-remove-udelay-causing-huge-irq-latency.patch queue-4.0/mips-makefile-fix-mips-ase-detection-code.patch queue-4.0/mips-r4kcache-use-correct-base-register-for-mips-r6-cache-flushes.patch queue-4.0/mips-fix-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-ralink-fix-bad-config-symbol-in-pci-makefile.patch queue-4.0/revert-mips-remove-race-window-in-page-fault-handling.patch queue-4.0/mips-fix-race-condition-in-lazy-cache-flushing.patch queue-4.0/mips-bcm63xx-move-bcm63xx_gpio_init-to-bcm63xx_register_devices.patch queue-4.0/mips-octeon-delete-override-of-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-asm-spinlock-fix-addiu-instruction-for-r10000_llsc_war-case.patch queue-4.0/mips-kconfig-disable-smp-cps-for-64-bit.patch queue-4.0/mips-bcm47xx-fix-detecting-microsoft-mn-700-asus-wl500g.patch queue-4.0/mips-octeon-use-correct-csr-to-soft-reset.patch queue-4.0/revert-mips-avoid-pipeline-stalls-on-some-mips32r2-cores.patch queue-4.0/mips-octeon-dma-octeon-fix-ohci-usb-config-check.patch queue-4.0/mips-octeon-fix-pci-interrupt-mapping-for-d-link-dsr-1000n.patch queue-4.0/mips-kconfig-fix-typo-for-the-r2-to-r6-emulator-kernel-parameter.patch queue-4.0/ssb-fix-kconfig-dependencies.patch queue-4.0/mips-kernel-entry.s-set-correct-isa-level-for-mips_ihb.patch queue-4.0/mips-netlogic-fix-for-sata-phy-init.patch queue-4.0/mips-ralink-add-missing-symbol-for-ralink_ill_acc.patch queue-4.0/mips-asm-elf-set-o32-default-fpu-flags.patch queue-4.0/mips-smp-cps-cpu_set-fpu-mask-if-fpu-present.patch
PATCH v2 2/23 MIPS: OCTEON: dma-octeon: fix OHCI USB config check
In reply to Ralf BaechleFrom: Aaro Koskinen <[email protected]>
Commit a8667d706dfa394ef9fe5f9013dee92d40a096e8 upstream.
CONFIG_USB_OCTEON_OHCI is deprecated and no longer needed to use OHCI on OCTEON II. Instead, CONFIG_USB_OHCI_HCD_PLATFORM should be used.
Patchwork: https://patchwork.linux-mips.org/patch/9421/
--- arch/mips/cavium-octeon/dma-octeon.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/mips/cavium-octeon/dma-octeon.c +1 -1
@@ -306,7 +306,7 @@ void __init plat_swiotlb_setup(void) swiotlbsize = 64 * (1<<20); }#endif -#ifdef CONFIG_USB_OCTEON_OHCI +#ifdef CONFIG_USB_OHCI_HCD_PLATFORM /* OCTEON II ohci is only 32-bit. */ if (OCTEON_IS_OCTEON2 () && max_addr >=0x100000000ul ) swiotlbsize =64 * (1 <<20 );
Signature · 1 line
1.9.3
Patch "MIPS: OCTEON: dma-octeon: fix OHCI USB config check" has been added to the 4.0-stable tree
This is a note to let you know that I've just added the patch titled
MIPS: OCTEON: dma-octeon: fix OHCI USB config check
to the 4.0-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
mips-octeon-dma-octeon-fix-ohci-usb-config-check.patch
and it can be found in the queue-4.0 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From [email protected] Fri May 8 16:23:47 2015
From: Ralf Baechle <[email protected]>
Date: Wed, 4 Mar 2015 23:08:49 +0200
Subject: MIPS: OCTEON: dma-octeon: fix OHCI USB config check
To: [email protected]
Message-ID: <d89963272898b14eb99f248a3e9df97795952e53.1431087908.git.ralf@linux-mips.org>
From: Aaro Koskinen <[email protected]>
Commit a8667d706dfa394ef9fe5f9013dee92d40a096e8 upstream.
CONFIG_USB_OCTEON_OHCI is deprecated and no longer needed to use OHCI on OCTEON II. Instead, CONFIG_USB_OHCI_HCD_PLATFORM should be used.
Patchwork: https://patchwork.linux-mips.org/patch/9421/
--- arch/mips/cavium-octeon/dma-octeon.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/mips/cavium-octeon/dma-octeon.c +1 -1
@@ -306,7 +306,7 @@ void __init plat_swiotlb_setup(void) swiotlbsize = 64 * (1<<20); }#endif -#ifdef CONFIG_USB_OCTEON_OHCI +#ifdef CONFIG_USB_OHCI_HCD_PLATFORM /* OCTEON II ohci is only 32-bit. */ if (OCTEON_IS_OCTEON2 () && max_addr >=0x100000000ul ) swiotlbsize =64 * (1 <<20 );
Patches currently in stable-queue which might be from [email protected] are
queue-4.0/mips-octeon-remove-udelay-causing-huge-irq-latency.patch queue-4.0/mips-makefile-fix-mips-ase-detection-code.patch queue-4.0/mips-r4kcache-use-correct-base-register-for-mips-r6-cache-flushes.patch queue-4.0/mips-fix-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-ralink-fix-bad-config-symbol-in-pci-makefile.patch queue-4.0/revert-mips-remove-race-window-in-page-fault-handling.patch queue-4.0/mips-fix-race-condition-in-lazy-cache-flushing.patch queue-4.0/mips-bcm63xx-move-bcm63xx_gpio_init-to-bcm63xx_register_devices.patch queue-4.0/mips-octeon-delete-override-of-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-asm-spinlock-fix-addiu-instruction-for-r10000_llsc_war-case.patch queue-4.0/mips-kconfig-disable-smp-cps-for-64-bit.patch queue-4.0/mips-bcm47xx-fix-detecting-microsoft-mn-700-asus-wl500g.patch queue-4.0/mips-octeon-use-correct-csr-to-soft-reset.patch queue-4.0/revert-mips-avoid-pipeline-stalls-on-some-mips32r2-cores.patch queue-4.0/mips-octeon-dma-octeon-fix-ohci-usb-config-check.patch queue-4.0/mips-octeon-fix-pci-interrupt-mapping-for-d-link-dsr-1000n.patch queue-4.0/mips-kconfig-fix-typo-for-the-r2-to-r6-emulator-kernel-parameter.patch queue-4.0/ssb-fix-kconfig-dependencies.patch queue-4.0/mips-kernel-entry.s-set-correct-isa-level-for-mips_ihb.patch queue-4.0/mips-netlogic-fix-for-sata-phy-init.patch queue-4.0/mips-ralink-add-missing-symbol-for-ralink_ill_acc.patch queue-4.0/mips-asm-elf-set-o32-default-fpu-flags.patch queue-4.0/mips-smp-cps-cpu_set-fpu-mask-if-fpu-present.patch
PATCH v2 3/23 MIPS: OCTEON: Use correct CSR to soft reset
In reply to Ralf BaechleFrom: Chandrakala Chavva <[email protected]>
Commit 9a49899eb88803dcc0ef437f09912f9a7b7a66fd upstream.
Also delete unused cvmx_reset_octeon()
This fixes reboot for Octeon III boards
Patchwork: https://patchwork.linux-mips.org/patch/9471/
--- arch/mips/cavium-octeon/setup.c | 5 ++++- arch/mips/include/asm/octeon/cvmx.h | 8 -------- 2 files changed, 4 insertions(+), 9 deletions(-)
arch/mips/cavium-octeon/setup.c +4 -1
@@ -413,7 +413,10 @@ static void octeon_restart(char *command)mb ();while (1 ) -cvmx_write_csr (CVMX_CIU_SOFT_RST ,1 ); +if (OCTEON_IS_OCTEON3 ()) +cvmx_write_csr (CVMX_RST_SOFT_RST ,1 ); +else +cvmx_write_csr (CVMX_CIU_SOFT_RST ,1 ); }
arch/mips/include/asm/octeon/cvmx.h +0 -8
@@ -436,14 +436,6 @@ static inline uint64_t cvmx_get_cycle_global(void)/***************************************************************************/ -static inline void cvmx_reset_octeon (void ) -{ -union cvmx_ciu_soft_rst ciu_soft_rst; - ciu_soft_rst.u64 =0 ; - ciu_soft_rst.s.soft_rst =1 ; -cvmx_write_csr (CVMX_CIU_SOFT_RST , ciu_soft_rst.u64); -} -/* Return the number of cores available in the chip */ static inline uint32_t cvmx_octeon_num_cores (void ) {
Signature · 1 line
1.9.3
Patch "MIPS: OCTEON: Use correct CSR to soft reset" has been added to the 4.0-stable tree
This is a note to let you know that I've just added the patch titled
MIPS: OCTEON: Use correct CSR to soft reset
to the 4.0-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
mips-octeon-use-correct-csr-to-soft-reset.patch
and it can be found in the queue-4.0 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From [email protected] Fri May 8 16:24:22 2015
From: Ralf Baechle <[email protected]>
Date: Fri, 6 Mar 2015 14:02:21 +0300
Subject: MIPS: OCTEON: Use correct CSR to soft reset
To: [email protected]
Message-ID: <149fba8b175539836c311d54b41cb93778c49a82.1431087908.git.ralf@linux-mips.org>
From: Chandrakala Chavva <[email protected]>
Commit 9a49899eb88803dcc0ef437f09912f9a7b7a66fd upstream.
Also delete unused cvmx_reset_octeon()
This fixes reboot for Octeon III boards
Patchwork: https://patchwork.linux-mips.org/patch/9471/
--- arch/mips/cavium-octeon/setup.c | 5 ++++- arch/mips/include/asm/octeon/cvmx.h | 8 -------- 2 files changed, 4 insertions(+), 9 deletions(-)
arch/mips/cavium-octeon/setup.c +4 -1
@@ -413,7 +413,10 @@ static void octeon_restart(char *commandmb ();while (1 ) -cvmx_write_csr (CVMX_CIU_SOFT_RST ,1 ); +if (OCTEON_IS_OCTEON3 ()) +cvmx_write_csr (CVMX_RST_SOFT_RST ,1 ); +else +cvmx_write_csr (CVMX_CIU_SOFT_RST ,1 ); }
arch/mips/include/asm/octeon/cvmx.h +0 -8
@@ -436,14 +436,6 @@ static inline uint64_t cvmx_get_cycle_gl/***************************************************************************/ -static inline void cvmx_reset_octeon (void ) -{ -union cvmx_ciu_soft_rst ciu_soft_rst; - ciu_soft_rst.u64 =0 ; - ciu_soft_rst.s.soft_rst =1 ; -cvmx_write_csr (CVMX_CIU_SOFT_RST , ciu_soft_rst.u64); -} -/* Return the number of cores available in the chip */ static inline uint32_t cvmx_octeon_num_cores (void ) {
Patches currently in stable-queue which might be from [email protected] are
queue-4.0/mips-octeon-remove-udelay-causing-huge-irq-latency.patch queue-4.0/mips-makefile-fix-mips-ase-detection-code.patch queue-4.0/mips-r4kcache-use-correct-base-register-for-mips-r6-cache-flushes.patch queue-4.0/mips-fix-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-ralink-fix-bad-config-symbol-in-pci-makefile.patch queue-4.0/revert-mips-remove-race-window-in-page-fault-handling.patch queue-4.0/mips-fix-race-condition-in-lazy-cache-flushing.patch queue-4.0/mips-bcm63xx-move-bcm63xx_gpio_init-to-bcm63xx_register_devices.patch queue-4.0/mips-octeon-delete-override-of-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-asm-spinlock-fix-addiu-instruction-for-r10000_llsc_war-case.patch queue-4.0/mips-kconfig-disable-smp-cps-for-64-bit.patch queue-4.0/mips-bcm47xx-fix-detecting-microsoft-mn-700-asus-wl500g.patch queue-4.0/mips-octeon-use-correct-csr-to-soft-reset.patch queue-4.0/revert-mips-avoid-pipeline-stalls-on-some-mips32r2-cores.patch queue-4.0/mips-octeon-dma-octeon-fix-ohci-usb-config-check.patch queue-4.0/mips-octeon-fix-pci-interrupt-mapping-for-d-link-dsr-1000n.patch queue-4.0/mips-kconfig-fix-typo-for-the-r2-to-r6-emulator-kernel-parameter.patch queue-4.0/ssb-fix-kconfig-dependencies.patch queue-4.0/mips-kernel-entry.s-set-correct-isa-level-for-mips_ihb.patch queue-4.0/mips-netlogic-fix-for-sata-phy-init.patch queue-4.0/mips-ralink-add-missing-symbol-for-ralink_ill_acc.patch queue-4.0/mips-asm-elf-set-o32-default-fpu-flags.patch queue-4.0/mips-smp-cps-cpu_set-fpu-mask-if-fpu-present.patch
PATCH v2 4/23 Revert "MIPS: Remove race window in page fault handling"
In reply to Ralf BaechleFrom: Lars Persson <[email protected]>
Commit 5b9593f3bccb9904f260f9ad7f184e1d2921bd1e upstream.
Revert commit 2a4a8b1e5d9d ("MIPS: Remove race window in page fault handling") because it increased the number of flushed dcache pages and became a performance problem for some workloads.
Patchwork: https://patchwork.linux-mips.org/patch/9345/
--- arch/mips/include/asm/pgtable.h | 9 +++++---- arch/mips/mm/cache.c | 27 ++++++++------------------- 2 files changed, 13 insertions(+), 23 deletions(-)
arch/mips/include/asm/pgtable.h +5 -4
@@ -127,10 +127,6 @@ do { \ } \ } while(0) - -extern void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, -pte_t pteval); -#if defined(CONFIG_PHYS_ADDR_T_64BIT ) && defined(CONFIG_CPU_MIPS32 )#define pte_none (pte) (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL))
@@ -154,6 +150,7 @@ static inline void set_pte(pte_t *ptep, pte_t pte) } } } +#define set_pte_at (mm, addr, ptep, pteval) set_pte(ptep, pteval)static inline void pte_clear (struct mm_struct *mm,unsigned long addr,pte_t *ptep) {
@@ -192,6 +189,7 @@ static inline void set_pte(pte_t *ptep, pte_t pteval) }#endif } +#define set_pte_at (mm, addr, ptep, pteval) set_pte(ptep, pteval)static inline void pte_clear (struct mm_struct *mm,unsigned long addr,pte_t *ptep) {
@@ -407,12 +405,15 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)extern void __update_tlb (struct vm_area_struct *vma,unsigned long address,pte_t pte); +extern void __update_cache (struct vm_area_struct *vma,unsigned long address, +pte_t pte);static inline void update_mmu_cache (struct vm_area_struct *vma,unsigned long address,pte_t *ptep) {pte_t pte = *ptep;__update_tlb (vma, address, pte); +__update_cache (vma, address, pte); } static inline void update_mmu_cache_pmd(struct vm_area_struct *vma,
arch/mips/mm/cache.c +8 -19
@@ -119,36 +119,25 @@ void __flush_anon_page(struct page *page, unsigned long vmaddr)EXPORT_SYMBOL (__flush_anon_page); -static void mips_flush_dcache_from_pte (pte_t pteval,unsigned long address) +void __update_cache (struct vm_area_struct *vma,unsigned long address, +pte_t pte) {struct page *page; -unsigned long pfn =pte_pfn (pteval); +unsigned long pfn, addr; +int exec = (vma->vm_flags &VM_EXEC ) && !cpu_has_ic_fills_f_dc; + pfn =pte_pfn (pte);if (unlikely (!pfn_valid (pfn)))return ; - page =pfn_to_page (pfn);if (page_mapping (page) &&Page_dcache_dirty (page)) { -unsigned long page_addr = (unsigned long )page_address (page); - -if (!cpu_has_ic_fills_f_dc || -pages_do_alias (page_addr, address &PAGE_MASK )) -flush_data_cache_page (page_addr); + addr = (unsigned long )page_address (page); +if (exec ||pages_do_alias (addr, address &PAGE_MASK )) +flush_data_cache_page (addr);ClearPageDcacheDirty (page); } } -void set_pte_at (struct mm_struct *mm,unsigned long addr, -pte_t *ptep,pte_t pteval) -{ -if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc) { -if (pte_present (pteval)) -mips_flush_dcache_from_pte (pteval, addr); - } - -set_pte (ptep, pteval); -} -unsigned long _page_cachable_default;EXPORT_SYMBOL (_page_cachable_default);
Signature · 1 line
1.9.3
Patch "Revert "MIPS: Remove race window in page fault handling"" has been added to the 4.0-stable tree
This is a note to let you know that I've just added the patch titled
Revert "MIPS: Remove race window in page fault handling"
to the 4.0-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
revert-mips-remove-race-window-in-page-fault-handling.patch
and it can be found in the queue-4.0 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From [email protected] Fri May 8 16:24:33 2015
From: Ralf Baechle <[email protected]>
Date: Thu, 26 Feb 2015 14:16:02 +0100
Subject: Revert "MIPS: Remove race window in page fault handling"
To: [email protected]
Message-ID: <dd9d42c457f61da9fc4224b06cccb584f290c17b.1431087908.git.ralf@linux-mips.org>
From: Lars Persson <[email protected]>
Commit 5b9593f3bccb9904f260f9ad7f184e1d2921bd1e upstream.
Revert commit 2a4a8b1e5d9d ("MIPS: Remove race window in page fault handling") because it increased the number of flushed dcache pages and became a performance problem for some workloads.
Patchwork: https://patchwork.linux-mips.org/patch/9345/
--- arch/mips/include/asm/pgtable.h | 9 +++++---- arch/mips/mm/cache.c | 27 ++++++++------------------- 2 files changed, 13 insertions(+), 23 deletions(-)
arch/mips/include/asm/pgtable.h +5 -4
@@ -127,10 +127,6 @@ do { \ } \ } while(0) - -extern void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, -pte_t pteval); -#if defined(CONFIG_PHYS_ADDR_T_64BIT ) && defined(CONFIG_CPU_MIPS32 )#define pte_none (pte) (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL))
@@ -154,6 +150,7 @@ static inline void set_pte(pte_t *ptep, } } } +#define set_pte_at (mm, addr, ptep, pteval) set_pte(ptep, pteval)static inline void pte_clear (struct mm_struct *mm,unsigned long addr,pte_t *ptep) {
@@ -192,6 +189,7 @@ static inline void set_pte(pte_t *ptep, }#endif } +#define set_pte_at (mm, addr, ptep, pteval) set_pte(ptep, pteval)static inline void pte_clear (struct mm_struct *mm,unsigned long addr,pte_t *ptep) {
@@ -407,12 +405,15 @@ static inline pte_t pte_modify(pte_t pteextern void __update_tlb (struct vm_area_struct *vma,unsigned long address,pte_t pte); +extern void __update_cache (struct vm_area_struct *vma,unsigned long address, +pte_t pte);static inline void update_mmu_cache (struct vm_area_struct *vma,unsigned long address,pte_t *ptep) {pte_t pte = *ptep;__update_tlb (vma, address, pte); +__update_cache (vma, address, pte); } static inline void update_mmu_cache_pmd(struct vm_area_struct *vma,
arch/mips/mm/cache.c +8 -19
@@ -119,36 +119,25 @@ void __flush_anon_page(struct page *pageEXPORT_SYMBOL (__flush_anon_page); -static void mips_flush_dcache_from_pte (pte_t pteval,unsigned long address) +void __update_cache (struct vm_area_struct *vma,unsigned long address, +pte_t pte) {struct page *page; -unsigned long pfn =pte_pfn (pteval); +unsigned long pfn, addr; +int exec = (vma->vm_flags &VM_EXEC ) && !cpu_has_ic_fills_f_dc; + pfn =pte_pfn (pte);if (unlikely (!pfn_valid (pfn)))return ; - page =pfn_to_page (pfn);if (page_mapping (page) &&Page_dcache_dirty (page)) { -unsigned long page_addr = (unsigned long )page_address (page); - -if (!cpu_has_ic_fills_f_dc || -pages_do_alias (page_addr, address &PAGE_MASK )) -flush_data_cache_page (page_addr); + addr = (unsigned long )page_address (page); +if (exec ||pages_do_alias (addr, address &PAGE_MASK )) +flush_data_cache_page (addr);ClearPageDcacheDirty (page); } } -void set_pte_at (struct mm_struct *mm,unsigned long addr, -pte_t *ptep,pte_t pteval) -{ -if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc) { -if (pte_present (pteval)) -mips_flush_dcache_from_pte (pteval, addr); - } - -set_pte (ptep, pteval); -} -unsigned long _page_cachable_default;EXPORT_SYMBOL (_page_cachable_default);
Patches currently in stable-queue which might be from [email protected] are
queue-4.0/mips-octeon-remove-udelay-causing-huge-irq-latency.patch queue-4.0/mips-makefile-fix-mips-ase-detection-code.patch queue-4.0/mips-r4kcache-use-correct-base-register-for-mips-r6-cache-flushes.patch queue-4.0/mips-fix-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-ralink-fix-bad-config-symbol-in-pci-makefile.patch queue-4.0/revert-mips-remove-race-window-in-page-fault-handling.patch queue-4.0/mips-fix-race-condition-in-lazy-cache-flushing.patch queue-4.0/mips-bcm63xx-move-bcm63xx_gpio_init-to-bcm63xx_register_devices.patch queue-4.0/mips-octeon-delete-override-of-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-asm-spinlock-fix-addiu-instruction-for-r10000_llsc_war-case.patch queue-4.0/mips-kconfig-disable-smp-cps-for-64-bit.patch queue-4.0/mips-bcm47xx-fix-detecting-microsoft-mn-700-asus-wl500g.patch queue-4.0/mips-octeon-use-correct-csr-to-soft-reset.patch queue-4.0/revert-mips-avoid-pipeline-stalls-on-some-mips32r2-cores.patch queue-4.0/mips-octeon-dma-octeon-fix-ohci-usb-config-check.patch queue-4.0/mips-octeon-fix-pci-interrupt-mapping-for-d-link-dsr-1000n.patch queue-4.0/mips-kconfig-fix-typo-for-the-r2-to-r6-emulator-kernel-parameter.patch queue-4.0/ssb-fix-kconfig-dependencies.patch queue-4.0/mips-kernel-entry.s-set-correct-isa-level-for-mips_ihb.patch queue-4.0/mips-netlogic-fix-for-sata-phy-init.patch queue-4.0/mips-ralink-add-missing-symbol-for-ralink_ill_acc.patch queue-4.0/mips-asm-elf-set-o32-default-fpu-flags.patch queue-4.0/mips-smp-cps-cpu_set-fpu-mask-if-fpu-present.patch
PATCH v2 5/23 MIPS: Fix race condition in lazy cache flushing.
In reply to Ralf BaechleFrom: Lars Persson <[email protected]>
Commit 4d46a67a3eb827ccf1125959936fd51ba318dabc upstream.
The lazy cache flushing implemented in the MIPS kernel suffers from a race condition that is exposed by do_set_pte() in mm/memory.c.
A pre-condition is a file-system that writes to the page from the CPU in its readpage method and then calls flush_dcache_page(). One example is ubifs. Another pre-condition is that the dcache flush is postponed in __flush_dcache_page().
Upon a page fault for an executable mapping not existing in the page-cache, the following will happen:
1. Write to the page
2. flush_dcache_page
3. flush_icache_page
4. set_pte_at
5. update_mmu_cache (commits the flush of a dcache-dirty page)
Between steps 4 and 5 another thread can hit the same page and it will encounter a valid pte. Because the data still is in the L1 dcache the CPU will fetch stale data from L2 into the icache and execute garbage.
This fix moves the commit of the cache flush to step 3 to close the race window. It also reduces the amount of flushes on non-executable mappings because we never enter __flush_dcache_page() for non-aliasing CPUs.
Regressions can occur in drivers that mistakenly relies on the flush_dcache_page() in get_user_pages() for DMA operations.
[[email protected]: Folded in patch 9346 to fix highmem issue.]
Patchwork: https://patchwork.linux-mips.org/patch/9346/
Patchwork: https://patchwork.linux-mips.org/patch/9738/
--- arch/mips/include/asm/cacheflush.h | 38 +++++++++++++++++++++++--------------- arch/mips/mm/cache.c | 12 ++++++++++++ 2 files changed, 35 insertions(+), 15 deletions(-)
arch/mips/include/asm/cacheflush.h +23 -15
@@ -29,6 +29,20 @@* - flush_icache_all() flush the entire instruction cache * - flush_data_cache_page() flushes a page from the data cache */ + +/* +* This flag is used to indicate that the page pointed to by a pte +* is dirty and requires cleaning before returning it to the user. +*/ +#define PG_dcache_dirty PG_arch_1 + +#define Page_dcache_dirty (page) \ + test_bit(PG_dcache_dirty, &(page)->flags) +#define SetPageDcacheDirty (page) \ + set_bit(PG_dcache_dirty, &(page)->flags) +#define ClearPageDcacheDirty (page) \ + clear_bit(PG_dcache_dirty, &(page)->flags) +extern void (*flush_cache_all)(void );extern void (*__flush_cache_all)(void );extern void (*flush_cache_mm)(struct mm_struct *mm);
@@ -37,13 +51,15 @@ extern void (*flush_cache_range)(struct vm_area_struct *vma, unsigned long start, unsigned long end);extern void (*flush_cache_page)(struct vm_area_struct *vma,unsigned long page,unsigned long pfn);extern void __flush_dcache_page (struct page *page); +extern void __flush_icache_page (struct vm_area_struct *vma,struct page *page);#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1static inline void flush_dcache_page (struct page *page) { -if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc) +if (cpu_has_dc_aliases)__flush_dcache_page (page); - +else if (!cpu_has_ic_fills_f_dc) +SetPageDcacheDirty (page); }#define flush_dcache_mmap_lock (mapping) do { } while (0)
@@ -61,6 +77,11 @@ static inline void flush_anon_page(struct vm_area_struct *vma,static inline void flush_icache_page (struct vm_area_struct *vma,struct page *page) { +if (!cpu_has_ic_fills_f_dc && (vma->vm_flags &VM_EXEC ) && +Page_dcache_dirty (page)) { +__flush_icache_page (vma, page); +ClearPageDcacheDirty (page); + } }extern void (*flush_icache_range)(unsigned long start,unsigned long end);
@@ -95,19 +116,6 @@ extern void (*flush_icache_all)(void);extern void (*local_flush_data_cache_page)(void * addr);extern void (*flush_data_cache_page)(unsigned long addr); -/* -* This flag is used to indicate that the page pointed to by a pte -* is dirty and requires cleaning before returning it to the user. -*/ -#define PG_dcache_dirty PG_arch_1 - -#define Page_dcache_dirty (page) \ - test_bit(PG_dcache_dirty, &(page)->flags) -#define SetPageDcacheDirty (page) \ - set_bit(PG_dcache_dirty, &(page)->flags) -#define ClearPageDcacheDirty (page) \ - clear_bit(PG_dcache_dirty, &(page)->flags) -/* Run kernel code uncached, useful for cache probing functions. */ unsigned long run_uncached (void *func);
arch/mips/mm/cache.c +12 -0
@@ -119,6 +119,18 @@ void __flush_anon_page(struct page *page, unsigned long vmaddr)EXPORT_SYMBOL (__flush_anon_page); +void __flush_icache_page (struct vm_area_struct *vma,struct page *page) +{ +unsigned long addr; + +if (PageHighMem (page)) +return ; + + addr = (unsigned long )page_address (page); +flush_data_cache_page (addr); +} +EXPORT_SYMBOL_GPL (__flush_icache_page); +void __update_cache (struct vm_area_struct *vma,unsigned long address,pte_t pte) {
Signature · 1 line
1.9.3
Patch "MIPS: Fix race condition in lazy cache flushing." has been added to the 4.0-stable tree
This is a note to let you know that I've just added the patch titled
MIPS: Fix race condition in lazy cache flushing.
to the 4.0-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
mips-fix-race-condition-in-lazy-cache-flushing.patch
and it can be found in the queue-4.0 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From [email protected] Fri May 8 16:24:43 2015
From: Ralf Baechle <[email protected]>
Date: Thu, 26 Feb 2015 14:16:03 +0100
Subject: MIPS: Fix race condition in lazy cache flushing.
To: [email protected]
Message-ID: <f751d1abbb63d80e96cadcb06f7c527457cab01c.1431087908.git.ralf@linux-mips.org>
From: Lars Persson <[email protected]>
Commit 4d46a67a3eb827ccf1125959936fd51ba318dabc upstream.
The lazy cache flushing implemented in the MIPS kernel suffers from a race condition that is exposed by do_set_pte() in mm/memory.c.
A pre-condition is a file-system that writes to the page from the CPU in its readpage method and then calls flush_dcache_page(). One example is ubifs. Another pre-condition is that the dcache flush is postponed in __flush_dcache_page().
Upon a page fault for an executable mapping not existing in the page-cache, the following will happen:
1. Write to the page
2. flush_dcache_page
3. flush_icache_page
4. set_pte_at
5. update_mmu_cache (commits the flush of a dcache-dirty page)
Between steps 4 and 5 another thread can hit the same page and it will encounter a valid pte. Because the data still is in the L1 dcache the CPU will fetch stale data from L2 into the icache and execute garbage.
This fix moves the commit of the cache flush to step 3 to close the race window. It also reduces the amount of flushes on non-executable mappings because we never enter __flush_dcache_page() for non-aliasing CPUs.
Regressions can occur in drivers that mistakenly relies on the flush_dcache_page() in get_user_pages() for DMA operations.
[[email protected]: Folded in patch 9346 to fix highmem issue.]
Patchwork: https://patchwork.linux-mips.org/patch/9346/
Patchwork: https://patchwork.linux-mips.org/patch/9738/
--- arch/mips/include/asm/cacheflush.h | 38 ++++++++++++++++++++++--------------- arch/mips/mm/cache.c | 12 +++++++++++ 2 files changed, 35 insertions(+), 15 deletions(-)
arch/mips/include/asm/cacheflush.h +23 -15
@@ -29,6 +29,20 @@* - flush_icache_all() flush the entire instruction cache * - flush_data_cache_page() flushes a page from the data cache */ + +/* +* This flag is used to indicate that the page pointed to by a pte +* is dirty and requires cleaning before returning it to the user. +*/ +#define PG_dcache_dirty PG_arch_1 + +#define Page_dcache_dirty (page) \ + test_bit(PG_dcache_dirty, &(page)->flags) +#define SetPageDcacheDirty (page) \ + set_bit(PG_dcache_dirty, &(page)->flags) +#define ClearPageDcacheDirty (page) \ + clear_bit(PG_dcache_dirty, &(page)->flags) +extern void (*flush_cache_all)(void );extern void (*__flush_cache_all)(void );extern void (*flush_cache_mm)(struct mm_struct *mm);
@@ -37,13 +51,15 @@ extern void (*flush_cache_range)(struct unsigned long start, unsigned long end);extern void (*flush_cache_page)(struct vm_area_struct *vma,unsigned long page,unsigned long pfn);extern void __flush_dcache_page (struct page *page); +extern void __flush_icache_page (struct vm_area_struct *vma,struct page *page);#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1static inline void flush_dcache_page (struct page *page) { -if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc) +if (cpu_has_dc_aliases)__flush_dcache_page (page); - +else if (!cpu_has_ic_fills_f_dc) +SetPageDcacheDirty (page); }#define flush_dcache_mmap_lock (mapping) do { } while (0)
@@ -61,6 +77,11 @@ static inline void flush_anon_page(strucstatic inline void flush_icache_page (struct vm_area_struct *vma,struct page *page) { +if (!cpu_has_ic_fills_f_dc && (vma->vm_flags &VM_EXEC ) && +Page_dcache_dirty (page)) { +__flush_icache_page (vma, page); +ClearPageDcacheDirty (page); + } }extern void (*flush_icache_range)(unsigned long start,unsigned long end);
@@ -95,19 +116,6 @@ extern void (*flush_icache_all)(void);extern void (*local_flush_data_cache_page)(void * addr);extern void (*flush_data_cache_page)(unsigned long addr); -/* -* This flag is used to indicate that the page pointed to by a pte -* is dirty and requires cleaning before returning it to the user. -*/ -#define PG_dcache_dirty PG_arch_1 - -#define Page_dcache_dirty (page) \ - test_bit(PG_dcache_dirty, &(page)->flags) -#define SetPageDcacheDirty (page) \ - set_bit(PG_dcache_dirty, &(page)->flags) -#define ClearPageDcacheDirty (page) \ - clear_bit(PG_dcache_dirty, &(page)->flags) -/* Run kernel code uncached, useful for cache probing functions. */ unsigned long run_uncached (void *func);
arch/mips/mm/cache.c +12 -0
@@ -119,6 +119,18 @@ void __flush_anon_page(struct page *pageEXPORT_SYMBOL (__flush_anon_page); +void __flush_icache_page (struct vm_area_struct *vma,struct page *page) +{ +unsigned long addr; + +if (PageHighMem (page)) +return ; + + addr = (unsigned long )page_address (page); +flush_data_cache_page (addr); +} +EXPORT_SYMBOL_GPL (__flush_icache_page); +void __update_cache (struct vm_area_struct *vma,unsigned long address,pte_t pte) {
Patches currently in stable-queue which might be from [email protected] are
queue-4.0/mips-octeon-remove-udelay-causing-huge-irq-latency.patch queue-4.0/mips-makefile-fix-mips-ase-detection-code.patch queue-4.0/mips-r4kcache-use-correct-base-register-for-mips-r6-cache-flushes.patch queue-4.0/mips-fix-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-ralink-fix-bad-config-symbol-in-pci-makefile.patch queue-4.0/revert-mips-remove-race-window-in-page-fault-handling.patch queue-4.0/mips-fix-race-condition-in-lazy-cache-flushing.patch queue-4.0/mips-bcm63xx-move-bcm63xx_gpio_init-to-bcm63xx_register_devices.patch queue-4.0/mips-octeon-delete-override-of-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-asm-spinlock-fix-addiu-instruction-for-r10000_llsc_war-case.patch queue-4.0/mips-kconfig-disable-smp-cps-for-64-bit.patch queue-4.0/mips-bcm47xx-fix-detecting-microsoft-mn-700-asus-wl500g.patch queue-4.0/mips-octeon-use-correct-csr-to-soft-reset.patch queue-4.0/revert-mips-avoid-pipeline-stalls-on-some-mips32r2-cores.patch queue-4.0/mips-octeon-dma-octeon-fix-ohci-usb-config-check.patch queue-4.0/mips-octeon-fix-pci-interrupt-mapping-for-d-link-dsr-1000n.patch queue-4.0/mips-kconfig-fix-typo-for-the-r2-to-r6-emulator-kernel-parameter.patch queue-4.0/ssb-fix-kconfig-dependencies.patch queue-4.0/mips-kernel-entry.s-set-correct-isa-level-for-mips_ihb.patch queue-4.0/mips-netlogic-fix-for-sata-phy-init.patch queue-4.0/mips-ralink-add-missing-symbol-for-ralink_ill_acc.patch queue-4.0/mips-asm-elf-set-o32-default-fpu-flags.patch queue-4.0/mips-smp-cps-cpu_set-fpu-mask-if-fpu-present.patch
Ben Hutchings
AppliedRe: [PATCH v2 05/23] MIPS: Fix race condition in lazy cache flushing.
In reply to Ralf BaechleQuoted 3 lines · Ralf Baechle
From: Lars Persson <[email protected]>
Commit
4d46a67a3eb827ccf1125959936fd51ba318dabcupstream.
[...]
Queued up for 3.2, thanks.
Ben.
Signature · 2 lines
Ben Hutchings One of the nice things about standards is that there are so many of them.
PATCH v2 6/23 MIPS: Octeon: Remove udelay() causing huge IRQ latency
In reply to Ralf BaechleFrom: Alexander Sverdlin <[email protected]>
Commit 73bf3c2a500b2db8ac966469591196bf55afb409 upstream.
udelay() in PCI/PCIe read/write callbacks cause 30ms IRQ latency on Octeon platforms because these operations are called from PCI_OP_READ() and PCI_OP_WRITE() under raw_spin_lock_irqsave().
Patchwork: https://patchwork.linux-mips.org/patch/9576/
--- arch/mips/include/asm/octeon/pci-octeon.h | 3 --- arch/mips/pci/pci-octeon.c | 6 ------ arch/mips/pci/pcie-octeon.c | 8 -------- 3 files changed, 17 deletions(-)
arch/mips/include/asm/octeon/pci-octeon.h +0 -3
@@ -11,9 +11,6 @@#include <linux/pci.h> -/* Some PCI cards require delays when accessing config space. */ -#define PCI_CONFIG_SPACE_DELAY 10000 -/* * The physical memory base mapped by BAR1. 256MB at the end of the * first 4GB.
arch/mips/pci/pci-octeon.c +0 -6
@@ -271,9 +271,6 @@ static int octeon_read_config(struct pci_bus *bus, unsigned int devfn, pci_addr.s.func = devfn &0x7 ; pci_addr.s.reg = reg; -#if PCI_CONFIG_SPACE_DELAY -udelay (PCI_CONFIG_SPACE_DELAY ); -#endif switch (size) {case 4 : *val =le32_to_cpu (cvmx_read64_uint32 (pci_addr.u64));
@@ -308,9 +305,6 @@ static int octeon_write_config(struct pci_bus *bus, unsigned int devfn, pci_addr.s.func = devfn &0x7 ; pci_addr.s.reg = reg; -#if PCI_CONFIG_SPACE_DELAY -udelay (PCI_CONFIG_SPACE_DELAY ); -#endif switch (size) {case 4 :cvmx_write64_uint32 (pci_addr.u64,cpu_to_le32 (val));
arch/mips/pci/pcie-octeon.c +0 -8
@@ -1762,14 +1762,6 @@ static int octeon_pcie_write_config(unsigned int pcie_port, struct pci_bus *bus,default :return PCIBIOS_FUNC_NOT_SUPPORTED ; } -#if PCI_CONFIG_SPACE_DELAY -/* -* Delay on writes so that devices have time to come up. Some -* bridges need this to allow time for the secondary busses to -* work -*/ -udelay (PCI_CONFIG_SPACE_DELAY ); -#endif return PCIBIOS_SUCCESSFUL ; }
Signature · 1 line
1.9.3
Patch "MIPS: Octeon: Remove udelay() causing huge IRQ latency" has been added to the 4.0-stable tree
This is a note to let you know that I've just added the patch titled
MIPS: Octeon: Remove udelay() causing huge IRQ latency
to the 4.0-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
mips-octeon-remove-udelay-causing-huge-irq-latency.patch
and it can be found in the queue-4.0 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From [email protected] Fri May 8 16:24:52 2015
From: Ralf Baechle <[email protected]>
Date: Wed, 18 Mar 2015 14:05:21 +0100
Subject: MIPS: Octeon: Remove udelay() causing huge IRQ latency
To: [email protected]
Message-ID: <0d6db65f5dd6fb417f1f45bac283d0e23814fe34.1431087908.git.ralf@linux-mips.org>
From: Alexander Sverdlin <[email protected]>
Commit 73bf3c2a500b2db8ac966469591196bf55afb409 upstream.
udelay() in PCI/PCIe read/write callbacks cause 30ms IRQ latency on Octeon platforms because these operations are called from PCI_OP_READ() and PCI_OP_WRITE() under raw_spin_lock_irqsave().
Patchwork: https://patchwork.linux-mips.org/patch/9576/
--- arch/mips/include/asm/octeon/pci-octeon.h | 3 --- arch/mips/pci/pci-octeon.c | 6 ------ arch/mips/pci/pcie-octeon.c | 8 -------- 3 files changed, 17 deletions(-)
arch/mips/include/asm/octeon/pci-octeon.h +0 -3
@@ -11,9 +11,6 @@#include <linux/pci.h> -/* Some PCI cards require delays when accessing config space. */ -#define PCI_CONFIG_SPACE_DELAY 10000 -/* * The physical memory base mapped by BAR1. 256MB at the end of the * first 4GB.
arch/mips/pci/pci-octeon.c +0 -6
@@ -271,9 +271,6 @@ static int octeon_read_config(struct pci pci_addr.s.func = devfn &0x7 ; pci_addr.s.reg = reg; -#if PCI_CONFIG_SPACE_DELAY -udelay (PCI_CONFIG_SPACE_DELAY ); -#endif switch (size) {case 4 : *val =le32_to_cpu (cvmx_read64_uint32 (pci_addr.u64));
@@ -308,9 +305,6 @@ static int octeon_write_config(struct pc pci_addr.s.func = devfn &0x7 ; pci_addr.s.reg = reg; -#if PCI_CONFIG_SPACE_DELAY -udelay (PCI_CONFIG_SPACE_DELAY ); -#endif switch (size) {case 4 :cvmx_write64_uint32 (pci_addr.u64,cpu_to_le32 (val));
arch/mips/pci/pcie-octeon.c +0 -8
@@ -1762,14 +1762,6 @@ static int octeon_pcie_write_config(unsidefault :return PCIBIOS_FUNC_NOT_SUPPORTED ; } -#if PCI_CONFIG_SPACE_DELAY -/* -* Delay on writes so that devices have time to come up. Some -* bridges need this to allow time for the secondary busses to -* work -*/ -udelay (PCI_CONFIG_SPACE_DELAY ); -#endif return PCIBIOS_SUCCESSFUL ; }
Patches currently in stable-queue which might be from [email protected] are
queue-4.0/mips-octeon-remove-udelay-causing-huge-irq-latency.patch queue-4.0/mips-makefile-fix-mips-ase-detection-code.patch queue-4.0/mips-r4kcache-use-correct-base-register-for-mips-r6-cache-flushes.patch queue-4.0/mips-fix-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-ralink-fix-bad-config-symbol-in-pci-makefile.patch queue-4.0/revert-mips-remove-race-window-in-page-fault-handling.patch queue-4.0/mips-fix-race-condition-in-lazy-cache-flushing.patch queue-4.0/mips-bcm63xx-move-bcm63xx_gpio_init-to-bcm63xx_register_devices.patch queue-4.0/mips-octeon-delete-override-of-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-asm-spinlock-fix-addiu-instruction-for-r10000_llsc_war-case.patch queue-4.0/mips-kconfig-disable-smp-cps-for-64-bit.patch queue-4.0/mips-bcm47xx-fix-detecting-microsoft-mn-700-asus-wl500g.patch queue-4.0/mips-octeon-use-correct-csr-to-soft-reset.patch queue-4.0/revert-mips-avoid-pipeline-stalls-on-some-mips32r2-cores.patch queue-4.0/mips-octeon-dma-octeon-fix-ohci-usb-config-check.patch queue-4.0/mips-octeon-fix-pci-interrupt-mapping-for-d-link-dsr-1000n.patch queue-4.0/mips-kconfig-fix-typo-for-the-r2-to-r6-emulator-kernel-parameter.patch queue-4.0/ssb-fix-kconfig-dependencies.patch queue-4.0/mips-kernel-entry.s-set-correct-isa-level-for-mips_ihb.patch queue-4.0/mips-netlogic-fix-for-sata-phy-init.patch queue-4.0/mips-ralink-add-missing-symbol-for-ralink_ill_acc.patch queue-4.0/mips-asm-elf-set-o32-default-fpu-flags.patch queue-4.0/mips-smp-cps-cpu_set-fpu-mask-if-fpu-present.patch
Ben Hutchings
AppliedRe: [PATCH v2 06/23] MIPS: Octeon: Remove udelay() causing huge IRQ latency
In reply to Ralf BaechleQuoted 3 lines · Ralf Baechle
From: Alexander Sverdlin <[email protected]>
Commit
73bf3c2a500b2db8ac966469591196bf55afb409upstream.
[...]
Queued up for 3.2, thanks.
Ben.
Signature · 2 lines
Ben Hutchings One of the nice things about standards is that there are so many of them.
PATCH v2 7/23 MIPS: OCTEON: fix PCI interrupt mapping for D-Link DSR-1000N
In reply to Ralf BaechleFrom: Aaro Koskinen <[email protected]>
Commit b083518c52ab75a345d668ca7fa41e530df08d51 upstream.
Fix PCI interrupt mapping for DSR1000N. This will get the PCI slot interrupts working. The mapping is based on D-Link GPL tarball.
Patchwork: https://patchwork.linux-mips.org/patch/9593/
--- arch/mips/pci/pci-octeon.c | 2 ++ 1 file changed, 2 insertions(+)
arch/mips/pci/pci-octeon.c +2 -0
@@ -214,6 +214,8 @@ const char *octeon_get_pci_interrupts(void)return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA" ;case CVMX_BOARD_TYPE_BBGW_REF :return "AABCD" ; +case CVMX_BOARD_TYPE_CUST_DSR1000N : +return "CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC" ;case CVMX_BOARD_TYPE_THUNDER :case CVMX_BOARD_TYPE_EBH3000 :default :
Signature · 1 line
1.9.3
Patch "MIPS: OCTEON: fix PCI interrupt mapping for D-Link DSR-1000N" has been added to the 4.0-stable tree
This is a note to let you know that I've just added the patch titled
MIPS: OCTEON: fix PCI interrupt mapping for D-Link DSR-1000N
to the 4.0-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
mips-octeon-fix-pci-interrupt-mapping-for-d-link-dsr-1000n.patch
and it can be found in the queue-4.0 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From [email protected] Fri May 8 16:25:05 2015
From: Ralf Baechle <[email protected]>
Date: Sun, 22 Mar 2015 17:55:39 +0200
Subject: MIPS: OCTEON: fix PCI interrupt mapping for D-Link DSR-1000N
To: [email protected]
Message-ID: <caa87aea665abf098316cc6a0a96c932134832c5.1431087908.git.ralf@linux-mips.org>
From: Aaro Koskinen <[email protected]>
Commit b083518c52ab75a345d668ca7fa41e530df08d51 upstream.
Fix PCI interrupt mapping for DSR1000N. This will get the PCI slot interrupts working. The mapping is based on D-Link GPL tarball.
Patchwork: https://patchwork.linux-mips.org/patch/9593/
--- arch/mips/pci/pci-octeon.c | 2 ++ 1 file changed, 2 insertions(+)
arch/mips/pci/pci-octeon.c +2 -0
@@ -214,6 +214,8 @@ const char *octeon_get_pci_interrupts(voreturn "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA" ;case CVMX_BOARD_TYPE_BBGW_REF :return "AABCD" ; +case CVMX_BOARD_TYPE_CUST_DSR1000N : +return "CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC" ;case CVMX_BOARD_TYPE_THUNDER :case CVMX_BOARD_TYPE_EBH3000 :default :
Patches currently in stable-queue which might be from [email protected] are
queue-4.0/mips-octeon-remove-udelay-causing-huge-irq-latency.patch queue-4.0/mips-makefile-fix-mips-ase-detection-code.patch queue-4.0/mips-r4kcache-use-correct-base-register-for-mips-r6-cache-flushes.patch queue-4.0/mips-fix-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-ralink-fix-bad-config-symbol-in-pci-makefile.patch queue-4.0/revert-mips-remove-race-window-in-page-fault-handling.patch queue-4.0/mips-fix-race-condition-in-lazy-cache-flushing.patch queue-4.0/mips-bcm63xx-move-bcm63xx_gpio_init-to-bcm63xx_register_devices.patch queue-4.0/mips-octeon-delete-override-of-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-asm-spinlock-fix-addiu-instruction-for-r10000_llsc_war-case.patch queue-4.0/mips-kconfig-disable-smp-cps-for-64-bit.patch queue-4.0/mips-bcm47xx-fix-detecting-microsoft-mn-700-asus-wl500g.patch queue-4.0/mips-octeon-use-correct-csr-to-soft-reset.patch queue-4.0/revert-mips-avoid-pipeline-stalls-on-some-mips32r2-cores.patch queue-4.0/mips-octeon-dma-octeon-fix-ohci-usb-config-check.patch queue-4.0/mips-octeon-fix-pci-interrupt-mapping-for-d-link-dsr-1000n.patch queue-4.0/mips-kconfig-fix-typo-for-the-r2-to-r6-emulator-kernel-parameter.patch queue-4.0/ssb-fix-kconfig-dependencies.patch queue-4.0/mips-kernel-entry.s-set-correct-isa-level-for-mips_ihb.patch queue-4.0/mips-netlogic-fix-for-sata-phy-init.patch queue-4.0/mips-ralink-add-missing-symbol-for-ralink_ill_acc.patch queue-4.0/mips-asm-elf-set-o32-default-fpu-flags.patch queue-4.0/mips-smp-cps-cpu_set-fpu-mask-if-fpu-present.patch
PATCH v2 8/23 MIPS: Netlogic: Fix for SATA PHY init
In reply to Ralf BaechleFrom: Ganesan Ramalingam <[email protected]>
Commit 872cd4c2c617bb3a203ebe18115fd0c697112b87 upstream.
Update to the SATA PHY initialization. This is needed for SATA detection to succeed in all configurations.
Patchwork: https://patchwork.linux-mips.org/patch/8886/
--- arch/mips/netlogic/xlp/ahci-init-xlp2.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)
arch/mips/netlogic/xlp/ahci-init-xlp2.c +13 -0
@@ -203,6 +203,7 @@ static u8 read_phy_reg(u64 regbase, u32 addr, u32 physel)static void config_sata_phy (u64 regbase) {u32 port, i, reg; +u8 val;for (port =0 ; port <2 ; port++) {for (i =0 , reg =RXCDRCALFOSC0 ; reg <=CALDUTY ; reg++, i++)
@@ -210,6 +211,18 @@ static void config_sata_phy(u64 regbase)for (i =0 , reg =RXDPIF ; reg <=PPMDRIFTMAX_HI ; reg++, i++)write_phy_reg (regbase, reg, port, sata_phy_config2[i]); + +/* Fix for PHY link up failures at lower temperatures */ +write_phy_reg (regbase,0x800F , port,0x1f ); + + val =read_phy_reg (regbase,0x0029 , port); +write_phy_reg (regbase,0x0029 , port, val | (0x7 <<1 )); + + val =read_phy_reg (regbase,0x0056 , port); +write_phy_reg (regbase,0x0056 , port, val & ~(1 <<3 )); + + val =read_phy_reg (regbase,0x0018 , port); +write_phy_reg (regbase,0x0018 , port, val & ~(0x7 <<0 )); } }
Signature · 1 line
1.9.3
Patch "MIPS: Netlogic: Fix for SATA PHY init" has been added to the 4.0-stable tree
This is a note to let you know that I've just added the patch titled
MIPS: Netlogic: Fix for SATA PHY init
to the 4.0-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
mips-netlogic-fix-for-sata-phy-init.patch
and it can be found in the queue-4.0 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From [email protected] Fri May 8 16:25:15 2015
From: Ralf Baechle <[email protected]>
Date: Wed, 7 Jan 2015 16:58:26 +0530
Subject: MIPS: Netlogic: Fix for SATA PHY init
To: [email protected]
Message-ID: <de078db9540ed3c7a17ba4053d7cf1a196b56194.1431087908.git.ralf@linux-mips.org>
From: Ganesan Ramalingam <[email protected]>
Commit 872cd4c2c617bb3a203ebe18115fd0c697112b87 upstream.
Update to the SATA PHY initialization. This is needed for SATA detection to succeed in all configurations.
Patchwork: https://patchwork.linux-mips.org/patch/8886/
--- arch/mips/netlogic/xlp/ahci-init-xlp2.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)
arch/mips/netlogic/xlp/ahci-init-xlp2.c +13 -0
@@ -203,6 +203,7 @@ static u8 read_phy_reg(u64 regbase, u32static void config_sata_phy (u64 regbase) {u32 port, i, reg; +u8 val;for (port =0 ; port <2 ; port++) {for (i =0 , reg =RXCDRCALFOSC0 ; reg <=CALDUTY ; reg++, i++)
@@ -210,6 +211,18 @@ static void config_sata_phy(u64 regbase)for (i =0 , reg =RXDPIF ; reg <=PPMDRIFTMAX_HI ; reg++, i++)write_phy_reg (regbase, reg, port, sata_phy_config2[i]); + +/* Fix for PHY link up failures at lower temperatures */ +write_phy_reg (regbase,0x800F , port,0x1f ); + + val =read_phy_reg (regbase,0x0029 , port); +write_phy_reg (regbase,0x0029 , port, val | (0x7 <<1 )); + + val =read_phy_reg (regbase,0x0056 , port); +write_phy_reg (regbase,0x0056 , port, val & ~(1 <<3 )); + + val =read_phy_reg (regbase,0x0018 , port); +write_phy_reg (regbase,0x0018 , port, val & ~(0x7 <<0 )); } }
Patches currently in stable-queue which might be from [email protected] are
queue-4.0/mips-octeon-remove-udelay-causing-huge-irq-latency.patch queue-4.0/mips-makefile-fix-mips-ase-detection-code.patch queue-4.0/mips-r4kcache-use-correct-base-register-for-mips-r6-cache-flushes.patch queue-4.0/mips-fix-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-ralink-fix-bad-config-symbol-in-pci-makefile.patch queue-4.0/revert-mips-remove-race-window-in-page-fault-handling.patch queue-4.0/mips-fix-race-condition-in-lazy-cache-flushing.patch queue-4.0/mips-bcm63xx-move-bcm63xx_gpio_init-to-bcm63xx_register_devices.patch queue-4.0/mips-octeon-delete-override-of-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-asm-spinlock-fix-addiu-instruction-for-r10000_llsc_war-case.patch queue-4.0/mips-kconfig-disable-smp-cps-for-64-bit.patch queue-4.0/mips-bcm47xx-fix-detecting-microsoft-mn-700-asus-wl500g.patch queue-4.0/mips-octeon-use-correct-csr-to-soft-reset.patch queue-4.0/revert-mips-avoid-pipeline-stalls-on-some-mips32r2-cores.patch queue-4.0/mips-octeon-dma-octeon-fix-ohci-usb-config-check.patch queue-4.0/mips-octeon-fix-pci-interrupt-mapping-for-d-link-dsr-1000n.patch queue-4.0/mips-kconfig-fix-typo-for-the-r2-to-r6-emulator-kernel-parameter.patch queue-4.0/ssb-fix-kconfig-dependencies.patch queue-4.0/mips-kernel-entry.s-set-correct-isa-level-for-mips_ihb.patch queue-4.0/mips-netlogic-fix-for-sata-phy-init.patch queue-4.0/mips-ralink-add-missing-symbol-for-ralink_ill_acc.patch queue-4.0/mips-asm-elf-set-o32-default-fpu-flags.patch queue-4.0/mips-smp-cps-cpu_set-fpu-mask-if-fpu-present.patch
PATCH v2 9/23 MIPS: Kconfig: Fix typo for the r2-to-r6 emulator kernel parameter
In reply to Ralf BaechleFrom: Markos Chandras <[email protected]>
Commit 07edf0d46c07568d08feee95bbaa38c71b084150 upstream.
Commit b0a668fb2038 ("MIPS: kernel: mips-r2-to-r6-emul: Add R2 emulator for MIPS R6") added the mips r2-to-r6 emulator so an R2 userland can be executed on R6 kernels. This needed both build time and runtime support. The runtime support needed the "mipsr2emu" kernel parameter instead of the "mipsr2emul" listed in the Kconfig help message.
Patchwork: https://patchwork.linux-mips.org/patch/9504/
--- arch/mips/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/mips/Kconfig +1 -1
@@ -2072,7 +2072,7 @@ config MIPSR2_TO_R6_EMULATOR help Choose this option if you want to run non-R6 MIPS userland code. Even if you say 'Y' here, the emulator will still be disabled by - default. You can enable it using the 'mipsr2emul' kernel option. + default. You can enable it using the 'mipsr2emu' kernel option. The only reason this is a build-time option is to save ~14K from the final kernel image. comment "MIPS R2-to-R6 emulator is only available for UP kernels"
Signature · 1 line
1.9.3
Patch "MIPS: Kconfig: Fix typo for the r2-to-r6 emulator kernel parameter" has been added to the 4.0-stable tree
This is a note to let you know that I've just added the patch titled
MIPS: Kconfig: Fix typo for the r2-to-r6 emulator kernel parameter
to the 4.0-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
mips-kconfig-fix-typo-for-the-r2-to-r6-emulator-kernel-parameter.patch
and it can be found in the queue-4.0 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From [email protected] Fri May 8 16:39:19 2015
From: Ralf Baechle <[email protected]>
Date: Tue, 10 Mar 2015 12:30:56 +0000
Subject: MIPS: Kconfig: Fix typo for the r2-to-r6 emulator kernel parameter
To: [email protected]
Message-ID: <fa02c4fe56f4d48872fe2ea51f01de14250e78bf.1431087908.git.ralf@linux-mips.org>
From: Markos Chandras <[email protected]>
Commit 07edf0d46c07568d08feee95bbaa38c71b084150 upstream.
Commit b0a668fb2038 ("MIPS: kernel: mips-r2-to-r6-emul: Add R2 emulator for MIPS R6") added the mips r2-to-r6 emulator so an R2 userland can be executed on R6 kernels. This needed both build time and runtime support. The runtime support needed the "mipsr2emu" kernel parameter instead of the "mipsr2emul" listed in the Kconfig help message.
Patchwork: https://patchwork.linux-mips.org/patch/9504/
--- arch/mips/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/mips/Kconfig +1 -1
@@ -2072,7 +2072,7 @@ config MIPSR2_TO_R6_EMULATOR help Choose this option if you want to run non-R6 MIPS userland code. Even if you say 'Y' here, the emulator will still be disabled by - default. You can enable it using the 'mipsr2emul' kernel option. + default. You can enable it using the 'mipsr2emu' kernel option. The only reason this is a build-time option is to save ~14K from the final kernel image. comment "MIPS R2-to-R6 emulator is only available for UP kernels"
Patches currently in stable-queue which might be from [email protected] are
queue-4.0/mips-octeon-remove-udelay-causing-huge-irq-latency.patch queue-4.0/mips-makefile-fix-mips-ase-detection-code.patch queue-4.0/mips-r4kcache-use-correct-base-register-for-mips-r6-cache-flushes.patch queue-4.0/mips-fix-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-ralink-fix-bad-config-symbol-in-pci-makefile.patch queue-4.0/revert-mips-remove-race-window-in-page-fault-handling.patch queue-4.0/mips-fix-race-condition-in-lazy-cache-flushing.patch queue-4.0/mips-bcm63xx-move-bcm63xx_gpio_init-to-bcm63xx_register_devices.patch queue-4.0/mips-octeon-delete-override-of-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-asm-spinlock-fix-addiu-instruction-for-r10000_llsc_war-case.patch queue-4.0/mips-kconfig-disable-smp-cps-for-64-bit.patch queue-4.0/mips-bcm47xx-fix-detecting-microsoft-mn-700-asus-wl500g.patch queue-4.0/mips-octeon-use-correct-csr-to-soft-reset.patch queue-4.0/revert-mips-avoid-pipeline-stalls-on-some-mips32r2-cores.patch queue-4.0/mips-octeon-dma-octeon-fix-ohci-usb-config-check.patch queue-4.0/mips-octeon-fix-pci-interrupt-mapping-for-d-link-dsr-1000n.patch queue-4.0/mips-kconfig-fix-typo-for-the-r2-to-r6-emulator-kernel-parameter.patch queue-4.0/ssb-fix-kconfig-dependencies.patch queue-4.0/mips-kernel-entry.s-set-correct-isa-level-for-mips_ihb.patch queue-4.0/mips-netlogic-fix-for-sata-phy-init.patch queue-4.0/mips-ralink-add-missing-symbol-for-ralink_ill_acc.patch queue-4.0/mips-asm-elf-set-o32-default-fpu-flags.patch queue-4.0/mips-smp-cps-cpu_set-fpu-mask-if-fpu-present.patch
PATCH v2 10/23 MIPS: r4kcache: Use correct base register for MIPS R6 cache flushes
In reply to Ralf BaechleFrom: Markos Chandras <[email protected]>
Commit f6b39ae6f4d6ee835bb16e452086121aa010f1a7 upstream.
Commit 934c79231c1b("MIPS: asm: r4kcache: Add MIPS R6 cache unroll functions") added support for MIPS R6 cache flushes but it used the wrong base address register to perform the flushes so the same lines were flushed over and over. Moreover, replace the "addiu" instructions with LONG_ADDIU so the correct base address is calculated for 64-bit cores.
Patchwork: https://patchwork.linux-mips.org/patch/9384/
--- arch/mips/include/asm/r4kcache.h | 89 ++++++++++++++++++++-------------------- 1 file changed, 45 insertions(+), 44 deletions(-)
arch/mips/include/asm/r4kcache.h +45 -44
@@ -12,6 +12,8 @@#ifndef _ASM_R4KCACHE_H#define _ASM_R4KCACHE_H +#include <linux/stringify.h> +#include <asm/asm.h> #include <asm/cacheops.h> #include <asm/compiler.h>
@@ -344,7 +346,7 @@ static inline void invalidate_tcache_page(unsigned long addr)" cache %1, 0x0a0(%0); cache %1, 0x0b0(%0)\n" \" cache %1, 0x0c0(%0); cache %1, 0x0d0(%0)\n" \" cache %1, 0x0e0(%0); cache %1, 0x0f0(%0)\n" \ -" addiu $1, $0, 0x100 \n" \ + " "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n" \" cache %1, 0x000($1); cache %1, 0x010($1)\n" \" cache %1, 0x020($1); cache %1, 0x030($1)\n" \" cache %1, 0x040($1); cache %1, 0x050($1)\n" \
@@ -368,17 +370,17 @@ static inline void invalidate_tcache_page(unsigned long addr)" cache %1, 0x040(%0); cache %1, 0x060(%0)\n" \" cache %1, 0x080(%0); cache %1, 0x0a0(%0)\n" \" cache %1, 0x0c0(%0); cache %1, 0x0e0(%0)\n" \ -" addiu $1, %0, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n" \" cache %1, 0x000($1); cache %1, 0x020($1)\n" \" cache %1, 0x040($1); cache %1, 0x060($1)\n" \" cache %1, 0x080($1); cache %1, 0x0a0($1)\n" \" cache %1, 0x0c0($1); cache %1, 0x0e0($1)\n" \ -" addiu $1, $1, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \" cache %1, 0x000($1); cache %1, 0x020($1)\n" \" cache %1, 0x040($1); cache %1, 0x060($1)\n" \" cache %1, 0x080($1); cache %1, 0x0a0($1)\n" \" cache %1, 0x0c0($1); cache %1, 0x0e0($1)\n" \ -" addiu $1, $1, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100\n" \" cache %1, 0x000($1); cache %1, 0x020($1)\n" \" cache %1, 0x040($1); cache %1, 0x060($1)\n" \" cache %1, 0x080($1); cache %1, 0x0a0($1)\n" \
@@ -396,25 +398,25 @@ static inline void invalidate_tcache_page(unsigned long addr)" .set noat\n" \" cache %1, 0x000(%0); cache %1, 0x040(%0)\n" \" cache %1, 0x080(%0); cache %1, 0x0c0(%0)\n" \ -" addiu $1, %0, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n" \" cache %1, 0x000($1); cache %1, 0x040($1)\n" \" cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ -" addiu $1, %0, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \" cache %1, 0x000($1); cache %1, 0x040($1)\n" \" cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ -" addiu $1, %0, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \" cache %1, 0x000($1); cache %1, 0x040($1)\n" \" cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ -" addiu $1, %0, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \" cache %1, 0x000($1); cache %1, 0x040($1)\n" \" cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ -" addiu $1, %0, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \" cache %1, 0x000($1); cache %1, 0x040($1)\n" \" cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ -" addiu $1, %0, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \" cache %1, 0x000($1); cache %1, 0x040($1)\n" \" cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ -" addiu $1, %0, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \" cache %1, 0x000($1); cache %1, 0x040($1)\n" \" cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \" .set pop\n" \
@@ -429,39 +431,38 @@ static inline void invalidate_tcache_page(unsigned long addr)" .set mips64r6\n" \" .set noat\n" \" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ -" addiu $1, %0, 0x100\n" \ -" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ -" addiu $1, %0, 0x100\n" \ -" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ -" addiu $1, %0, 0x100\n" \ -" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ -" addiu $1, %0, 0x100\n" \ -" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ -" addiu $1, %0, 0x100\n" \ -" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ -" addiu $1, %0, 0x100\n" \ -" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ -" addiu $1, %0, 0x100\n" \ -" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ -" addiu $1, %0, 0x100\n" \ -" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ -" addiu $1, %0, 0x100\n" \ -" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ -" addiu $1, %0, 0x100\n" \ -" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ -" addiu $1, %0, 0x100\n" \ -" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ -" addiu $1, %0, 0x100\n" \ -" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ -" addiu $1, %0, 0x100\n" \ -" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ -" addiu $1, %0, 0x100\n" \ -" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ -" addiu $1, %0, 0x100\n" \ -" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ -" addiu $1, %0, 0x100\n" \ -" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ -" addiu $1, %0, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n" \ +" cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ +" cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ +" cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ +" cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ +" cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ +" cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ +" cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ +" cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ +" cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ +" cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ +" cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ +" cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ +" cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ +" cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ +" cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ " .set pop\n" \ : \ : "r" (base), \
Signature · 1 line
1.9.3
Patch "MIPS: r4kcache: Use correct base register for MIPS R6 cache flushes" has been added to the 4.0-stable tree
This is a note to let you know that I've just added the patch titled
MIPS: r4kcache: Use correct base register for MIPS R6 cache flushes
to the 4.0-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
mips-r4kcache-use-correct-base-register-for-mips-r6-cache-flushes.patch
and it can be found in the queue-4.0 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From [email protected] Fri May 8 16:39:27 2015
From: Ralf Baechle <[email protected]>
Date: Tue, 3 Mar 2015 18:48:47 +0000
Subject: MIPS: r4kcache: Use correct base register for MIPS R6 cache flushes
To: [email protected]
Message-ID: <c87cb8d1aeb0220918be14ba834d993072a79ea3.1431087908.git.ralf@linux-mips.org>
From: Markos Chandras <[email protected]>
Commit f6b39ae6f4d6ee835bb16e452086121aa010f1a7 upstream.
Commit 934c79231c1b("MIPS: asm: r4kcache: Add MIPS R6 cache unroll functions") added support for MIPS R6 cache flushes but it used the wrong base address register to perform the flushes so the same lines were flushed over and over. Moreover, replace the "addiu" instructions with LONG_ADDIU so the correct base address is calculated for 64-bit cores.
Patchwork: https://patchwork.linux-mips.org/patch/9384/
--- arch/mips/include/asm/r4kcache.h | 89 +++++++++++++++++++-------------------- 1 file changed, 45 insertions(+), 44 deletions(-)
arch/mips/include/asm/r4kcache.h +45 -44
@@ -12,6 +12,8 @@#ifndef _ASM_R4KCACHE_H#define _ASM_R4KCACHE_H +#include <linux/stringify.h> +#include <asm/asm.h> #include <asm/cacheops.h> #include <asm/compiler.h>
@@ -344,7 +346,7 @@ static inline void invalidate_tcache_pag" cache %1, 0x0a0(%0); cache %1, 0x0b0(%0)\n" \" cache %1, 0x0c0(%0); cache %1, 0x0d0(%0)\n" \" cache %1, 0x0e0(%0); cache %1, 0x0f0(%0)\n" \ -" addiu $1, $0, 0x100 \n" \ + " "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n" \" cache %1, 0x000($1); cache %1, 0x010($1)\n" \" cache %1, 0x020($1); cache %1, 0x030($1)\n" \" cache %1, 0x040($1); cache %1, 0x050($1)\n" \
@@ -368,17 +370,17 @@ static inline void invalidate_tcache_pag" cache %1, 0x040(%0); cache %1, 0x060(%0)\n" \" cache %1, 0x080(%0); cache %1, 0x0a0(%0)\n" \" cache %1, 0x0c0(%0); cache %1, 0x0e0(%0)\n" \ -" addiu $1, %0, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n" \" cache %1, 0x000($1); cache %1, 0x020($1)\n" \" cache %1, 0x040($1); cache %1, 0x060($1)\n" \" cache %1, 0x080($1); cache %1, 0x0a0($1)\n" \" cache %1, 0x0c0($1); cache %1, 0x0e0($1)\n" \ -" addiu $1, $1, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \" cache %1, 0x000($1); cache %1, 0x020($1)\n" \" cache %1, 0x040($1); cache %1, 0x060($1)\n" \" cache %1, 0x080($1); cache %1, 0x0a0($1)\n" \" cache %1, 0x0c0($1); cache %1, 0x0e0($1)\n" \ -" addiu $1, $1, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100\n" \" cache %1, 0x000($1); cache %1, 0x020($1)\n" \" cache %1, 0x040($1); cache %1, 0x060($1)\n" \" cache %1, 0x080($1); cache %1, 0x0a0($1)\n" \
@@ -396,25 +398,25 @@ static inline void invalidate_tcache_pag" .set noat\n" \" cache %1, 0x000(%0); cache %1, 0x040(%0)\n" \" cache %1, 0x080(%0); cache %1, 0x0c0(%0)\n" \ -" addiu $1, %0, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n" \" cache %1, 0x000($1); cache %1, 0x040($1)\n" \" cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ -" addiu $1, %0, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \" cache %1, 0x000($1); cache %1, 0x040($1)\n" \" cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ -" addiu $1, %0, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \" cache %1, 0x000($1); cache %1, 0x040($1)\n" \" cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ -" addiu $1, %0, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \" cache %1, 0x000($1); cache %1, 0x040($1)\n" \" cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ -" addiu $1, %0, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \" cache %1, 0x000($1); cache %1, 0x040($1)\n" \" cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ -" addiu $1, %0, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \" cache %1, 0x000($1); cache %1, 0x040($1)\n" \" cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ -" addiu $1, %0, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \" cache %1, 0x000($1); cache %1, 0x040($1)\n" \" cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \" .set pop\n" \
@@ -429,39 +431,38 @@ static inline void invalidate_tcache_pag" .set mips64r6\n" \" .set noat\n" \" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ -" addiu $1, %0, 0x100\n" \ -" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ -" addiu $1, %0, 0x100\n" \ -" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ -" addiu $1, %0, 0x100\n" \ -" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ -" addiu $1, %0, 0x100\n" \ -" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ -" addiu $1, %0, 0x100\n" \ -" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ -" addiu $1, %0, 0x100\n" \ -" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ -" addiu $1, %0, 0x100\n" \ -" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ -" addiu $1, %0, 0x100\n" \ -" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ -" addiu $1, %0, 0x100\n" \ -" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ -" addiu $1, %0, 0x100\n" \ -" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ -" addiu $1, %0, 0x100\n" \ -" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ -" addiu $1, %0, 0x100\n" \ -" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ -" addiu $1, %0, 0x100\n" \ -" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ -" addiu $1, %0, 0x100\n" \ -" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ -" addiu $1, %0, 0x100\n" \ -" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ -" addiu $1, %0, 0x100\n" \ -" cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ -" addiu $1, %0, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n" \ +" cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ +" cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ +" cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ +" cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ +" cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ +" cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ +" cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ +" cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ +" cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ +" cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ +" cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ +" cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ +" cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ +" cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ +" cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ " .set pop\n" \ : \ : "r" (base), \
Patches currently in stable-queue which might be from [email protected] are
queue-4.0/mips-octeon-remove-udelay-causing-huge-irq-latency.patch queue-4.0/mips-makefile-fix-mips-ase-detection-code.patch queue-4.0/mips-r4kcache-use-correct-base-register-for-mips-r6-cache-flushes.patch queue-4.0/mips-fix-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-ralink-fix-bad-config-symbol-in-pci-makefile.patch queue-4.0/revert-mips-remove-race-window-in-page-fault-handling.patch queue-4.0/mips-fix-race-condition-in-lazy-cache-flushing.patch queue-4.0/mips-bcm63xx-move-bcm63xx_gpio_init-to-bcm63xx_register_devices.patch queue-4.0/mips-octeon-delete-override-of-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-asm-spinlock-fix-addiu-instruction-for-r10000_llsc_war-case.patch queue-4.0/mips-kconfig-disable-smp-cps-for-64-bit.patch queue-4.0/mips-bcm47xx-fix-detecting-microsoft-mn-700-asus-wl500g.patch queue-4.0/mips-octeon-use-correct-csr-to-soft-reset.patch queue-4.0/revert-mips-avoid-pipeline-stalls-on-some-mips32r2-cores.patch queue-4.0/mips-octeon-dma-octeon-fix-ohci-usb-config-check.patch queue-4.0/mips-octeon-fix-pci-interrupt-mapping-for-d-link-dsr-1000n.patch queue-4.0/mips-kconfig-fix-typo-for-the-r2-to-r6-emulator-kernel-parameter.patch queue-4.0/ssb-fix-kconfig-dependencies.patch queue-4.0/mips-kernel-entry.s-set-correct-isa-level-for-mips_ihb.patch queue-4.0/mips-netlogic-fix-for-sata-phy-init.patch queue-4.0/mips-ralink-add-missing-symbol-for-ralink_ill_acc.patch queue-4.0/mips-asm-elf-set-o32-default-fpu-flags.patch queue-4.0/mips-smp-cps-cpu_set-fpu-mask-if-fpu-present.patch
PATCH v2 11/23 MIPS: asm: spinlock: Fix addiu instruction for R10000_LLSC_WAR case
In reply to Ralf BaechleFrom: Markos Chandras <[email protected]>
Commit 518222161d4a2d3f3b2700098563b62383f83878 upstream.
Commit 5753762cbd1c("MIPS: asm: spinlock: Replace "sub" instruction with "addiu") replaced the "sub" instruction with addiu but it did not update the immediate value in the R10000_LLSC_WAR case.
Patchwork: https://patchwork.linux-mips.org/patch/9385/
--- arch/mips/include/asm/spinlock.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/mips/include/asm/spinlock.h +1 -1
@@ -263,7 +263,7 @@ static inline void arch_read_unlock(arch_rwlock_t *rw)if (R10000_LLSC_WAR ) { __asm__ __volatile__("1: ll %1, %2 # arch_read_unlock \n" -" addiu %1, 1 \n" +" addiu %1, -1 \n" " sc %1, %0 \n" " beqzl %1, 1b \n" : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
Signature · 1 line
1.9.3
Patch "MIPS: asm: spinlock: Fix addiu instruction for R10000_LLSC_WAR case" has been added to the 4.0-stable tree
This is a note to let you know that I've just added the patch titled
MIPS: asm: spinlock: Fix addiu instruction for R10000_LLSC_WAR case
to the 4.0-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
mips-asm-spinlock-fix-addiu-instruction-for-r10000_llsc_war-case.patch
and it can be found in the queue-4.0 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From [email protected] Fri May 8 16:39:36 2015
From: Ralf Baechle <[email protected]>
Date: Tue, 3 Mar 2015 18:48:48 +0000
Subject: MIPS: asm: spinlock: Fix addiu instruction for R10000_LLSC_WAR case
To: [email protected]
Message-ID: <2ef4ca102e747fd6883ad6625e6270d242e2fce2.1431087908.git.ralf@linux-mips.org>
From: Markos Chandras <[email protected]>
Commit 518222161d4a2d3f3b2700098563b62383f83878 upstream.
Commit 5753762cbd1c("MIPS: asm: spinlock: Replace "sub" instruction with "addiu") replaced the "sub" instruction with addiu but it did not update the immediate value in the R10000_LLSC_WAR case.
Patchwork: https://patchwork.linux-mips.org/patch/9385/
--- arch/mips/include/asm/spinlock.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/mips/include/asm/spinlock.h +1 -1
@@ -263,7 +263,7 @@ static inline void arch_read_unlock(archif (R10000_LLSC_WAR ) { __asm__ __volatile__("1: ll %1, %2 # arch_read_unlock \n" -" addiu %1, 1 \n" +" addiu %1, -1 \n" " sc %1, %0 \n" " beqzl %1, 1b \n" : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
Patches currently in stable-queue which might be from [email protected] are
queue-4.0/mips-octeon-remove-udelay-causing-huge-irq-latency.patch queue-4.0/mips-makefile-fix-mips-ase-detection-code.patch queue-4.0/mips-r4kcache-use-correct-base-register-for-mips-r6-cache-flushes.patch queue-4.0/mips-fix-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-ralink-fix-bad-config-symbol-in-pci-makefile.patch queue-4.0/revert-mips-remove-race-window-in-page-fault-handling.patch queue-4.0/mips-fix-race-condition-in-lazy-cache-flushing.patch queue-4.0/mips-bcm63xx-move-bcm63xx_gpio_init-to-bcm63xx_register_devices.patch queue-4.0/mips-octeon-delete-override-of-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-asm-spinlock-fix-addiu-instruction-for-r10000_llsc_war-case.patch queue-4.0/mips-kconfig-disable-smp-cps-for-64-bit.patch queue-4.0/mips-bcm47xx-fix-detecting-microsoft-mn-700-asus-wl500g.patch queue-4.0/mips-octeon-use-correct-csr-to-soft-reset.patch queue-4.0/revert-mips-avoid-pipeline-stalls-on-some-mips32r2-cores.patch queue-4.0/mips-octeon-dma-octeon-fix-ohci-usb-config-check.patch queue-4.0/mips-octeon-fix-pci-interrupt-mapping-for-d-link-dsr-1000n.patch queue-4.0/mips-kconfig-fix-typo-for-the-r2-to-r6-emulator-kernel-parameter.patch queue-4.0/ssb-fix-kconfig-dependencies.patch queue-4.0/mips-kernel-entry.s-set-correct-isa-level-for-mips_ihb.patch queue-4.0/mips-netlogic-fix-for-sata-phy-init.patch queue-4.0/mips-ralink-add-missing-symbol-for-ralink_ill_acc.patch queue-4.0/mips-asm-elf-set-o32-default-fpu-flags.patch queue-4.0/mips-smp-cps-cpu_set-fpu-mask-if-fpu-present.patch
PATCH v2 12/23 MIPS: kernel: entry.S: Set correct ISA level for mips_ihb
In reply to Ralf BaechleFrom: Markos Chandras <[email protected]>
Commit aebac99384f7a6d83a3dcd42bf2481eed2670083 upstream.
Commit 6ebb496ffc7e("MIPS: kernel: entry.S: Add MIPS R6 related definitions") added the MIPSR6 definition but it did not update the ISA level of the actual assembly code so a pre-MIPSR6 jr.hb instruction was generated instead. Fix this by using the MISP_ISA_LEVEL_RAW macro.
Patchwork: https://patchwork.linux-mips.org/patch/9386/
--- arch/mips/kernel/entry.S | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
arch/mips/kernel/entry.S +2 -1
@@ -10,6 +10,7 @@ #include <asm/asm.h> #include <asm/asmmacro.h> +#include <asm/compiler.h> #include <asm/regdef.h> #include <asm/mipsregs.h> #include <asm/stackframe.h>
@@ -185,7 +186,7 @@ syscall_exit_work: * For C code use the inline version named instruction_hazard(). */ LEAF(mips_ihb) - .set mips32r2 + .set MIPS_ISA_LEVEL_RAW jr.hb ra nop END(mips_ihb)
Signature · 1 line
1.9.3
Patch "MIPS: kernel: entry.S: Set correct ISA level for mips_ihb" has been added to the 4.0-stable tree
This is a note to let you know that I've just added the patch titled
MIPS: kernel: entry.S: Set correct ISA level for mips_ihb
to the 4.0-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
mips-kernel-entry.s-set-correct-isa-level-for-mips_ihb.patch
and it can be found in the queue-4.0 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From [email protected] Fri May 8 16:39:44 2015
From: Ralf Baechle <[email protected]>
Date: Tue, 3 Mar 2015 18:48:49 +0000
Subject: MIPS: kernel: entry.S: Set correct ISA level for mips_ihb
To: [email protected]
Message-ID: <48b943431ab90523cb388d461fb30c585c2d27f9.1431087908.git.ralf@linux-mips.org>
From: Markos Chandras <[email protected]>
Commit aebac99384f7a6d83a3dcd42bf2481eed2670083 upstream.
Commit 6ebb496ffc7e("MIPS: kernel: entry.S: Add MIPS R6 related definitions") added the MIPSR6 definition but it did not update the ISA level of the actual assembly code so a pre-MIPSR6 jr.hb instruction was generated instead. Fix this by using the MISP_ISA_LEVEL_RAW macro.
Patchwork: https://patchwork.linux-mips.org/patch/9386/
--- arch/mips/kernel/entry.S | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
arch/mips/kernel/entry.S +2 -1
@@ -10,6 +10,7 @@ #include <asm/asm.h> #include <asm/asmmacro.h> +#include <asm/compiler.h> #include <asm/regdef.h> #include <asm/mipsregs.h> #include <asm/stackframe.h>
@@ -185,7 +186,7 @@ syscall_exit_work: * For C code use the inline version named instruction_hazard(). */ LEAF(mips_ihb) - .set mips32r2 + .set MIPS_ISA_LEVEL_RAW jr.hb ra nop END(mips_ihb)
Patches currently in stable-queue which might be from [email protected] are
queue-4.0/mips-octeon-remove-udelay-causing-huge-irq-latency.patch queue-4.0/mips-makefile-fix-mips-ase-detection-code.patch queue-4.0/mips-r4kcache-use-correct-base-register-for-mips-r6-cache-flushes.patch queue-4.0/mips-fix-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-ralink-fix-bad-config-symbol-in-pci-makefile.patch queue-4.0/revert-mips-remove-race-window-in-page-fault-handling.patch queue-4.0/mips-fix-race-condition-in-lazy-cache-flushing.patch queue-4.0/mips-bcm63xx-move-bcm63xx_gpio_init-to-bcm63xx_register_devices.patch queue-4.0/mips-octeon-delete-override-of-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-asm-spinlock-fix-addiu-instruction-for-r10000_llsc_war-case.patch queue-4.0/mips-kconfig-disable-smp-cps-for-64-bit.patch queue-4.0/mips-bcm47xx-fix-detecting-microsoft-mn-700-asus-wl500g.patch queue-4.0/mips-octeon-use-correct-csr-to-soft-reset.patch queue-4.0/revert-mips-avoid-pipeline-stalls-on-some-mips32r2-cores.patch queue-4.0/mips-octeon-dma-octeon-fix-ohci-usb-config-check.patch queue-4.0/mips-octeon-fix-pci-interrupt-mapping-for-d-link-dsr-1000n.patch queue-4.0/mips-kconfig-fix-typo-for-the-r2-to-r6-emulator-kernel-parameter.patch queue-4.0/ssb-fix-kconfig-dependencies.patch queue-4.0/mips-kernel-entry.s-set-correct-isa-level-for-mips_ihb.patch queue-4.0/mips-netlogic-fix-for-sata-phy-init.patch queue-4.0/mips-ralink-add-missing-symbol-for-ralink_ill_acc.patch queue-4.0/mips-asm-elf-set-o32-default-fpu-flags.patch queue-4.0/mips-smp-cps-cpu_set-fpu-mask-if-fpu-present.patch
PATCH v2 13/23 MIPS: Fix cpu_has_mips_r2_exec_hazard.
In reply to Ralf BaechleCommit 9cdf30bd3bac697fc533988f44a117434a858f69 upstream.
Returns a non-zero value if the current processor implementation requires an IHB instruction to deal with an instruction hazard as per MIPS R2 architecture specification, zero otherwise.
For a discussion, see http://patchwork.linux-mips.org/patch/9539/.
--- arch/mips/include/asm/cpu-features.h | 33 ++++++++++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-)
arch/mips/include/asm/cpu-features.h +32 -1
@@ -235,8 +235,39 @@/* MIPSR2 and MIPSR6 have a lot of similarities */ #define cpu_has_mips_r2_r6 (cpu_has_mips_r2 | cpu_has_mips_r6) +/* +* cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor +* +* Returns non-zero value if the current processor implementation requires +* an IHB instruction to deal with an instruction hazard as per MIPS R2 +* architecture specification, zero otherwise. +*/ #ifndef cpu_has_mips_r2_exec_hazard -#define cpu_has_mips_r2_exec_hazard (cpu_has_mips_r2 | cpu_has_mips_r6) +#define cpu_has_mips_r2_exec_hazard \ +({ \ + int __res; \ + \ + switch (current_cpu_type()) { \ + case CPU_M14KC: \ + case CPU_74K: \ + case CPU_1074K: \ + case CPU_PROAPTIV: \ + case CPU_P5600: \ + case CPU_M5150: \ + case CPU_QEMU_GENERIC: \ + case CPU_CAVIUM_OCTEON: \ + case CPU_CAVIUM_OCTEON_PLUS: \ + case CPU_CAVIUM_OCTEON2: \ + case CPU_CAVIUM_OCTEON3: \ + __res = 0; \ + break; \ + \ + default: \ + __res = 1; \ + } \ + \ + __res; \ +})#endif /*
Signature · 1 line
1.9.3
Patch "MIPS: Fix cpu_has_mips_r2_exec_hazard." has been added to the 4.0-stable tree
This is a note to let you know that I've just added the patch titled
MIPS: Fix cpu_has_mips_r2_exec_hazard.
to the 4.0-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
mips-fix-cpu_has_mips_r2_exec_hazard.patch
and it can be found in the queue-4.0 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From [email protected] Fri May 8 16:39:53 2015
From: Ralf Baechle <[email protected]>
Date: Wed, 25 Mar 2015 13:14:16 +0100
Subject: MIPS: Fix cpu_has_mips_r2_exec_hazard.
To: [email protected]
Message-ID: <62b458a293df11aef74befe68888a9443862a1ad.1431087908.git.ralf@linux-mips.org>
From: Ralf Baechle <[email protected]>
Commit 9cdf30bd3bac697fc533988f44a117434a858f69 upstream.
Returns a non-zero value if the current processor implementation requires an IHB instruction to deal with an instruction hazard as per MIPS R2 architecture specification, zero otherwise.
For a discussion, see http://patchwork.linux-mips.org/patch/9539/.
--- arch/mips/include/asm/cpu-features.h | 33 ++++++++++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-)
arch/mips/include/asm/cpu-features.h +32 -1
@@ -235,8 +235,39 @@/* MIPSR2 and MIPSR6 have a lot of similarities */ #define cpu_has_mips_r2_r6 (cpu_has_mips_r2 | cpu_has_mips_r6) +/* +* cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor +* +* Returns non-zero value if the current processor implementation requires +* an IHB instruction to deal with an instruction hazard as per MIPS R2 +* architecture specification, zero otherwise. +*/ #ifndef cpu_has_mips_r2_exec_hazard -#define cpu_has_mips_r2_exec_hazard (cpu_has_mips_r2 | cpu_has_mips_r6) +#define cpu_has_mips_r2_exec_hazard \ +({ \ + int __res; \ + \ + switch (current_cpu_type()) { \ + case CPU_M14KC: \ + case CPU_74K: \ + case CPU_1074K: \ + case CPU_PROAPTIV: \ + case CPU_P5600: \ + case CPU_M5150: \ + case CPU_QEMU_GENERIC: \ + case CPU_CAVIUM_OCTEON: \ + case CPU_CAVIUM_OCTEON_PLUS: \ + case CPU_CAVIUM_OCTEON2: \ + case CPU_CAVIUM_OCTEON3: \ + __res = 0; \ + break; \ + \ + default: \ + __res = 1; \ + } \ + \ + __res; \ +})#endif /*
Patches currently in stable-queue which might be from [email protected] are
queue-4.0/mips-octeon-remove-udelay-causing-huge-irq-latency.patch queue-4.0/mips-makefile-fix-mips-ase-detection-code.patch queue-4.0/mips-r4kcache-use-correct-base-register-for-mips-r6-cache-flushes.patch queue-4.0/mips-fix-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-ralink-fix-bad-config-symbol-in-pci-makefile.patch queue-4.0/revert-mips-remove-race-window-in-page-fault-handling.patch queue-4.0/mips-fix-race-condition-in-lazy-cache-flushing.patch queue-4.0/mips-bcm63xx-move-bcm63xx_gpio_init-to-bcm63xx_register_devices.patch queue-4.0/mips-octeon-delete-override-of-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-asm-spinlock-fix-addiu-instruction-for-r10000_llsc_war-case.patch queue-4.0/mips-kconfig-disable-smp-cps-for-64-bit.patch queue-4.0/mips-bcm47xx-fix-detecting-microsoft-mn-700-asus-wl500g.patch queue-4.0/mips-octeon-use-correct-csr-to-soft-reset.patch queue-4.0/revert-mips-avoid-pipeline-stalls-on-some-mips32r2-cores.patch queue-4.0/mips-octeon-dma-octeon-fix-ohci-usb-config-check.patch queue-4.0/mips-octeon-fix-pci-interrupt-mapping-for-d-link-dsr-1000n.patch queue-4.0/mips-kconfig-fix-typo-for-the-r2-to-r6-emulator-kernel-parameter.patch queue-4.0/ssb-fix-kconfig-dependencies.patch queue-4.0/mips-kernel-entry.s-set-correct-isa-level-for-mips_ihb.patch queue-4.0/mips-netlogic-fix-for-sata-phy-init.patch queue-4.0/mips-ralink-add-missing-symbol-for-ralink_ill_acc.patch queue-4.0/mips-asm-elf-set-o32-default-fpu-flags.patch queue-4.0/mips-smp-cps-cpu_set-fpu-mask-if-fpu-present.patch
Ben Hutchings
AppliedRe: [PATCH v2 13/23] MIPS: Fix cpu_has_mips_r2_exec_hazard.
In reply to Ralf BaechleQuoted 1 line · Ralf Baechle
Commit
9cdf30bd3bac697fc533988f44a117434a858f69upstream.
[...]
Queued up for 3.2, with a rather shorter list of CPU types. Thanks.
Ben.
Signature · 2 lines
Ben Hutchings One of the nice things about standards is that there are so many of them.
PATCH v2 14/23 MIPS: Octeon: Delete override of cpu_has_mips_r2_exec_hazard.
In reply to Ralf BaechleCommit f05ff43355e6997c18f82ddcee370a6e5f8643ce upstream.
This is no longer needed with the fixed, new and improved definition of cpu_has_mips_r2_exec_hazard in <asm/cpu-features.h>.
For a discussion, see http://patchwork.linux-mips.org/patch/9539/.
--- arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h | 1 - 1 file changed, 1 deletion(-)
arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h +0 -1
@@ -50,7 +50,6 @@#define cpu_has_mips32r2 0#define cpu_has_mips64r1 0#define cpu_has_mips64r2 1 -#define cpu_has_mips_r2_exec_hazard 0#define cpu_has_dsp 0#define cpu_has_dsp2 0#define cpu_has_mipsmt 0
Signature · 1 line
1.9.3
Patch "MIPS: Octeon: Delete override of cpu_has_mips_r2_exec_hazard." has been added to the 4.0-stable tree
This is a note to let you know that I've just added the patch titled
MIPS: Octeon: Delete override of cpu_has_mips_r2_exec_hazard.
to the 4.0-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
mips-octeon-delete-override-of-cpu_has_mips_r2_exec_hazard.patch
and it can be found in the queue-4.0 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From [email protected] Fri May 8 16:40:06 2015
From: Ralf Baechle <[email protected]>
Date: Wed, 25 Mar 2015 13:21:51 +0100
Subject: MIPS: Octeon: Delete override of cpu_has_mips_r2_exec_hazard.
To: [email protected]
Message-ID: <93b252080ebf0d3b7ae89f10437d8728ad8a281a.1431087908.git.ralf@linux-mips.org>
From: Ralf Baechle <[email protected]>
Commit f05ff43355e6997c18f82ddcee370a6e5f8643ce upstream.
This is no longer needed with the fixed, new and improved definition of cpu_has_mips_r2_exec_hazard in <asm/cpu-features.h>.
For a discussion, see http://patchwork.linux-mips.org/patch/9539/.
--- arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h | 1 - 1 file changed, 1 deletion(-)
arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h +0 -1
@@ -50,7 +50,6 @@#define cpu_has_mips32r2 0#define cpu_has_mips64r1 0#define cpu_has_mips64r2 1 -#define cpu_has_mips_r2_exec_hazard 0#define cpu_has_dsp 0#define cpu_has_dsp2 0#define cpu_has_mipsmt 0
Patches currently in stable-queue which might be from [email protected] are
queue-4.0/mips-octeon-remove-udelay-causing-huge-irq-latency.patch queue-4.0/mips-makefile-fix-mips-ase-detection-code.patch queue-4.0/mips-r4kcache-use-correct-base-register-for-mips-r6-cache-flushes.patch queue-4.0/mips-fix-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-ralink-fix-bad-config-symbol-in-pci-makefile.patch queue-4.0/revert-mips-remove-race-window-in-page-fault-handling.patch queue-4.0/mips-fix-race-condition-in-lazy-cache-flushing.patch queue-4.0/mips-bcm63xx-move-bcm63xx_gpio_init-to-bcm63xx_register_devices.patch queue-4.0/mips-octeon-delete-override-of-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-asm-spinlock-fix-addiu-instruction-for-r10000_llsc_war-case.patch queue-4.0/mips-kconfig-disable-smp-cps-for-64-bit.patch queue-4.0/mips-bcm47xx-fix-detecting-microsoft-mn-700-asus-wl500g.patch queue-4.0/mips-octeon-use-correct-csr-to-soft-reset.patch queue-4.0/revert-mips-avoid-pipeline-stalls-on-some-mips32r2-cores.patch queue-4.0/mips-octeon-dma-octeon-fix-ohci-usb-config-check.patch queue-4.0/mips-octeon-fix-pci-interrupt-mapping-for-d-link-dsr-1000n.patch queue-4.0/mips-kconfig-fix-typo-for-the-r2-to-r6-emulator-kernel-parameter.patch queue-4.0/ssb-fix-kconfig-dependencies.patch queue-4.0/mips-kernel-entry.s-set-correct-isa-level-for-mips_ihb.patch queue-4.0/mips-netlogic-fix-for-sata-phy-init.patch queue-4.0/mips-ralink-add-missing-symbol-for-ralink_ill_acc.patch queue-4.0/mips-asm-elf-set-o32-default-fpu-flags.patch queue-4.0/mips-smp-cps-cpu_set-fpu-mask-if-fpu-present.patch
Ben Hutchings
AppliedRe: [PATCH v2 14/23] MIPS: Octeon: Delete override of cpu_has_mips_r2_exec_hazard.
In reply to Ralf BaechleQuoted 1 line · Ralf Baechle
Commit
f05ff43355e6997c18f82ddcee370a6e5f8643ceupstream.
[...]
Queued up for 3.2, thanks.
Ben.
Signature · 2 lines
Ben Hutchings One of the nice things about standards is that there are so many of them.
PATCH v2 15/23 Revert "MIPS: Avoid pipeline stalls on some MIPS32R2 cores."
In reply to Ralf BaechleCommit 9eaffa84a8a46adab065c983401fc9d5949c958f upstream.
For a discussion, see http://patchwork.linux-mips.org/patch/9539/.
This reverts commit 625c0a21700bdb90844d926a1508a17a77e369c9.
--- arch/mips/mm/tlbex.c | 21 ++------------------- 1 file changed, 2 insertions(+), 19 deletions(-)
arch/mips/mm/tlbex.c +2 -19
@@ -501,26 +501,9 @@ static void build_tlb_write_entry(u32 **p, struct uasm_label **l,case tlb_indexed: tlbw = uasm_i_tlbwi;break ; } -if (cpu_has_mips_r2_exec_hazard) { -/* -* The architecture spec says an ehb is required here, -* but a number of cores do not have the hazard and -* using an ehb causes an expensive pipeline stall. -*/ -switch (current_cpu_type ()) { -case CPU_M14KC : -case CPU_74K : -case CPU_1074K : -case CPU_PROAPTIV : -case CPU_P5600 : -case CPU_M5150 : -case CPU_QEMU_GENERIC : -break ; - -default : +if (cpu_has_mips_r2_r6) { +if (cpu_has_mips_r2_exec_hazard)uasm_i_ehb (p); -break ; - }tlbw (p);return ; }
Signature · 1 line
1.9.3
Patch "Revert "MIPS: Avoid pipeline stalls on some MIPS32R2 cores."" has been added to the 4.0-stable tree
This is a note to let you know that I've just added the patch titled
Revert "MIPS: Avoid pipeline stalls on some MIPS32R2 cores."
to the 4.0-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
revert-mips-avoid-pipeline-stalls-on-some-mips32r2-cores.patch
and it can be found in the queue-4.0 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From [email protected] Fri May 8 16:40:22 2015
From: Ralf Baechle <[email protected]>
Date: Wed, 25 Mar 2015 13:18:27 +0100
Subject: Revert "MIPS: Avoid pipeline stalls on some MIPS32R2 cores."
To: [email protected]
Message-ID: <ab0cb06de61240d9b5449cc968f2a96ea2aae1ac.1431087908.git.ralf@linux-mips.org>
Commit 9eaffa84a8a46adab065c983401fc9d5949c958f upstream.
For a discussion, see http://patchwork.linux-mips.org/patch/9539/.
This reverts commit 625c0a21700bdb90844d926a1508a17a77e369c9.
--- arch/mips/mm/tlbex.c | 21 ++------------------- 1 file changed, 2 insertions(+), 19 deletions(-)
arch/mips/mm/tlbex.c +2 -19
@@ -501,26 +501,9 @@ static void build_tlb_write_entry(u32 **case tlb_indexed: tlbw = uasm_i_tlbwi;break ; } -if (cpu_has_mips_r2_exec_hazard) { -/* -* The architecture spec says an ehb is required here, -* but a number of cores do not have the hazard and -* using an ehb causes an expensive pipeline stall. -*/ -switch (current_cpu_type ()) { -case CPU_M14KC : -case CPU_74K : -case CPU_1074K : -case CPU_PROAPTIV : -case CPU_P5600 : -case CPU_M5150 : -case CPU_QEMU_GENERIC : -break ; - -default : +if (cpu_has_mips_r2_r6) { +if (cpu_has_mips_r2_exec_hazard)uasm_i_ehb (p); -break ; - }tlbw (p);return ; }
Patches currently in stable-queue which might be from [email protected] are
queue-4.0/mips-octeon-remove-udelay-causing-huge-irq-latency.patch queue-4.0/mips-makefile-fix-mips-ase-detection-code.patch queue-4.0/mips-r4kcache-use-correct-base-register-for-mips-r6-cache-flushes.patch queue-4.0/mips-fix-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-ralink-fix-bad-config-symbol-in-pci-makefile.patch queue-4.0/revert-mips-remove-race-window-in-page-fault-handling.patch queue-4.0/mips-fix-race-condition-in-lazy-cache-flushing.patch queue-4.0/mips-bcm63xx-move-bcm63xx_gpio_init-to-bcm63xx_register_devices.patch queue-4.0/mips-octeon-delete-override-of-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-asm-spinlock-fix-addiu-instruction-for-r10000_llsc_war-case.patch queue-4.0/mips-kconfig-disable-smp-cps-for-64-bit.patch queue-4.0/mips-bcm47xx-fix-detecting-microsoft-mn-700-asus-wl500g.patch queue-4.0/mips-octeon-use-correct-csr-to-soft-reset.patch queue-4.0/revert-mips-avoid-pipeline-stalls-on-some-mips32r2-cores.patch queue-4.0/mips-octeon-dma-octeon-fix-ohci-usb-config-check.patch queue-4.0/mips-octeon-fix-pci-interrupt-mapping-for-d-link-dsr-1000n.patch queue-4.0/mips-kconfig-fix-typo-for-the-r2-to-r6-emulator-kernel-parameter.patch queue-4.0/ssb-fix-kconfig-dependencies.patch queue-4.0/mips-kernel-entry.s-set-correct-isa-level-for-mips_ihb.patch queue-4.0/mips-netlogic-fix-for-sata-phy-init.patch queue-4.0/mips-ralink-add-missing-symbol-for-ralink_ill_acc.patch queue-4.0/mips-asm-elf-set-o32-default-fpu-flags.patch queue-4.0/mips-smp-cps-cpu_set-fpu-mask-if-fpu-present.patch
PATCH v2 16/23 SSB: fix Kconfig dependencies
In reply to Ralf BaechleFrom: Adrien Schildknecht <[email protected]>
Commit 179fa46fb666c8f2aa2bbb1f3114d5d826d59d3d upstream.
The commit 21400f252a97 ("MIPS: BCM47XX: Make ssb init NVRAM instead of bcm47xx polling it") introduces a dependency to SSB_SFLASH but did not add it to the Kconfig.
drivers/ssb/driver_mipscore.c:216:36: error: 'struct ssb_mipscore' has no member named 'sflash'
struct ssb_sflash *sflash = &mcore->sflash;
^
drivers/ssb/driver_mipscore.c:249:12: error: dereferencing pointer to
incomplete type
if (sflash->present) {
^Patchwork: https://patchwork.linux-mips.org/patch/9598/
--- drivers/ssb/Kconfig | 1 + 1 file changed, 1 insertion(+)
drivers/ssb/Kconfig +1 -0
@@ -130,6 +130,7 @@ config SSB_DRIVER_MIPS bool "SSB Broadcom MIPS core driver" depends on SSB && MIPS select SSB_SERIAL + select SSB_SFLASH help Driver for the Sonics Silicon Backplane attached Broadcom MIPS core.
Signature · 1 line
1.9.3
Patch "SSB: fix Kconfig dependencies" has been added to the 4.0-stable tree
This is a note to let you know that I've just added the patch titled
SSB: fix Kconfig dependencies
to the 4.0-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
ssb-fix-kconfig-dependencies.patch
and it can be found in the queue-4.0 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From [email protected] Fri May 8 16:40:35 2015
From: Ralf Baechle <[email protected]>
Date: Wed, 25 Mar 2015 16:31:42 +0100
Subject: SSB: fix Kconfig dependencies
To: [email protected]
Message-ID: <7c53fda29589eec7716f6cf5cc54946e95565897.1431087908.git.ralf@linux-mips.org>
From: Adrien Schildknecht <[email protected]>
Commit 179fa46fb666c8f2aa2bbb1f3114d5d826d59d3d upstream.
The commit 21400f252a97 ("MIPS: BCM47XX: Make ssb init NVRAM instead of bcm47xx polling it") introduces a dependency to SSB_SFLASH but did not add it to the Kconfig.
drivers/ssb/driver_mipscore.c:216:36: error: 'struct ssb_mipscore' has no member named 'sflash'
struct ssb_sflash *sflash = &mcore->sflash;
^
drivers/ssb/driver_mipscore.c:249:12: error: dereferencing pointer to
incomplete type
if (sflash->present) {
^Patchwork: https://patchwork.linux-mips.org/patch/9598/
--- drivers/ssb/Kconfig | 1 + 1 file changed, 1 insertion(+)
drivers/ssb/Kconfig +1 -0
@@ -130,6 +130,7 @@ config SSB_DRIVER_MIPS bool "SSB Broadcom MIPS core driver" depends on SSB && MIPS select SSB_SERIAL + select SSB_SFLASH help Driver for the Sonics Silicon Backplane attached Broadcom MIPS core.
Patches currently in stable-queue which might be from [email protected] are
queue-4.0/mips-octeon-remove-udelay-causing-huge-irq-latency.patch queue-4.0/mips-makefile-fix-mips-ase-detection-code.patch queue-4.0/mips-r4kcache-use-correct-base-register-for-mips-r6-cache-flushes.patch queue-4.0/mips-fix-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-ralink-fix-bad-config-symbol-in-pci-makefile.patch queue-4.0/revert-mips-remove-race-window-in-page-fault-handling.patch queue-4.0/mips-fix-race-condition-in-lazy-cache-flushing.patch queue-4.0/mips-bcm63xx-move-bcm63xx_gpio_init-to-bcm63xx_register_devices.patch queue-4.0/mips-octeon-delete-override-of-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-asm-spinlock-fix-addiu-instruction-for-r10000_llsc_war-case.patch queue-4.0/mips-kconfig-disable-smp-cps-for-64-bit.patch queue-4.0/mips-bcm47xx-fix-detecting-microsoft-mn-700-asus-wl500g.patch queue-4.0/mips-octeon-use-correct-csr-to-soft-reset.patch queue-4.0/revert-mips-avoid-pipeline-stalls-on-some-mips32r2-cores.patch queue-4.0/mips-octeon-dma-octeon-fix-ohci-usb-config-check.patch queue-4.0/mips-octeon-fix-pci-interrupt-mapping-for-d-link-dsr-1000n.patch queue-4.0/mips-kconfig-fix-typo-for-the-r2-to-r6-emulator-kernel-parameter.patch queue-4.0/ssb-fix-kconfig-dependencies.patch queue-4.0/mips-kernel-entry.s-set-correct-isa-level-for-mips_ihb.patch queue-4.0/mips-netlogic-fix-for-sata-phy-init.patch queue-4.0/mips-ralink-add-missing-symbol-for-ralink_ill_acc.patch queue-4.0/mips-asm-elf-set-o32-default-fpu-flags.patch queue-4.0/mips-smp-cps-cpu_set-fpu-mask-if-fpu-present.patch
PATCH v2 17/23 MIPS: ralink: Fix bad config symbol in PCI makefile.
In reply to Ralf BaechleFrom: John Crispin <[email protected]>
Commit 93a7de8819a661d06eb11f4de3d6888b9a842b30 upstream.
A wrong symbol is referenced by commit 187c26ddf0b2 ("MIPS: ralink: add rt2880 pci driver"). Fix this by changing it to the correct symbol.
Patchwork: https://patchwork.linux-mips.org/patch/9298/
--- arch/mips/pci/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/mips/pci/Makefile +1 -1
@@ -43,7 +43,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1480.o pci-bcm1480ht.o obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o obj-$(CONFIG_LANTIQ) += fixup-lantiq.o obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o -obj-$(CONFIG_SOC_RT2880) += pci-rt2880.o +obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
Signature · 1 line
1.9.3
Patch "MIPS: ralink: Fix bad config symbol in PCI makefile." has been added to the 4.0-stable tree
This is a note to let you know that I've just added the patch titled
MIPS: ralink: Fix bad config symbol in PCI makefile.
to the 4.0-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
mips-ralink-fix-bad-config-symbol-in-pci-makefile.patch
and it can be found in the queue-4.0 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From [email protected] Fri May 8 16:40:47 2015
From: Ralf Baechle <[email protected]>
Date: Mon, 23 Feb 2015 06:17:32 +0100
Subject: MIPS: ralink: Fix bad config symbol in PCI makefile.
To: [email protected]
Message-ID: <3e94c2b670b9f299527533bfa51660c392bba05a.1431087908.git.ralf@linux-mips.org>
From: John Crispin <[email protected]>
Commit 93a7de8819a661d06eb11f4de3d6888b9a842b30 upstream.
A wrong symbol is referenced by commit 187c26ddf0b2 ("MIPS: ralink: add rt2880 pci driver"). Fix this by changing it to the correct symbol.
Patchwork: https://patchwork.linux-mips.org/patch/9298/
--- arch/mips/pci/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/mips/pci/Makefile +1 -1
@@ -43,7 +43,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1 obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o obj-$(CONFIG_LANTIQ) += fixup-lantiq.o obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o -obj-$(CONFIG_SOC_RT2880) += pci-rt2880.o +obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
Patches currently in stable-queue which might be from [email protected] are
queue-4.0/mips-octeon-remove-udelay-causing-huge-irq-latency.patch queue-4.0/mips-makefile-fix-mips-ase-detection-code.patch queue-4.0/mips-r4kcache-use-correct-base-register-for-mips-r6-cache-flushes.patch queue-4.0/mips-fix-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-ralink-fix-bad-config-symbol-in-pci-makefile.patch queue-4.0/revert-mips-remove-race-window-in-page-fault-handling.patch queue-4.0/mips-fix-race-condition-in-lazy-cache-flushing.patch queue-4.0/mips-bcm63xx-move-bcm63xx_gpio_init-to-bcm63xx_register_devices.patch queue-4.0/mips-octeon-delete-override-of-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-asm-spinlock-fix-addiu-instruction-for-r10000_llsc_war-case.patch queue-4.0/mips-kconfig-disable-smp-cps-for-64-bit.patch queue-4.0/mips-bcm47xx-fix-detecting-microsoft-mn-700-asus-wl500g.patch queue-4.0/mips-octeon-use-correct-csr-to-soft-reset.patch queue-4.0/revert-mips-avoid-pipeline-stalls-on-some-mips32r2-cores.patch queue-4.0/mips-octeon-dma-octeon-fix-ohci-usb-config-check.patch queue-4.0/mips-octeon-fix-pci-interrupt-mapping-for-d-link-dsr-1000n.patch queue-4.0/mips-kconfig-fix-typo-for-the-r2-to-r6-emulator-kernel-parameter.patch queue-4.0/ssb-fix-kconfig-dependencies.patch queue-4.0/mips-kernel-entry.s-set-correct-isa-level-for-mips_ihb.patch queue-4.0/mips-netlogic-fix-for-sata-phy-init.patch queue-4.0/mips-ralink-add-missing-symbol-for-ralink_ill_acc.patch queue-4.0/mips-asm-elf-set-o32-default-fpu-flags.patch queue-4.0/mips-smp-cps-cpu_set-fpu-mask-if-fpu-present.patch
PATCH v2 18/23 MIPS: ralink: add missing symbol for RALINK_ILL_ACC
In reply to Ralf BaechleFrom: John Crispin <[email protected]>
Commit a7b7aad383c5dd9221a06e378197350dd27c1163 upstream.
A driver was added in commit 5433acd81e87 ("MIPS: ralink: add illegal access driver") without the Kconfig section being added. Fix this by adding the symbol to the Kconfig file.
Patchwork: https://patchwork.linux-mips.org/patch/9299/
--- arch/mips/ralink/Kconfig | 5 +++++ 1 file changed, 5 insertions(+)
arch/mips/ralink/Kconfig +5 -0
@@ -7,6 +7,11 @@ config CLKEVT_RT3352 select CLKSRC_OF select CLKSRC_MMIO +config RALINK_ILL_ACC + bool + depends on SOC_RT305X + default y + choice prompt "Ralink SoC selection" default SOC_RT305X
Signature · 1 line
1.9.3
Patch "MIPS: ralink: add missing symbol for RALINK_ILL_ACC" has been added to the 4.0-stable tree
This is a note to let you know that I've just added the patch titled
MIPS: ralink: add missing symbol for RALINK_ILL_ACC
to the 4.0-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
mips-ralink-add-missing-symbol-for-ralink_ill_acc.patch
and it can be found in the queue-4.0 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From [email protected] Fri May 8 16:40:54 2015
From: Ralf Baechle <[email protected]>
Date: Mon, 23 Feb 2015 06:17:33 +0100
Subject: MIPS: ralink: add missing symbol for RALINK_ILL_ACC
To: [email protected]
Message-ID: <e4e82f025f7a55ba7f70a4b72a3693a96cf4ab57.1431087908.git.ralf@linux-mips.org>
From: John Crispin <[email protected]>
Commit a7b7aad383c5dd9221a06e378197350dd27c1163 upstream.
A driver was added in commit 5433acd81e87 ("MIPS: ralink: add illegal access driver") without the Kconfig section being added. Fix this by adding the symbol to the Kconfig file.
Patchwork: https://patchwork.linux-mips.org/patch/9299/
--- arch/mips/ralink/Kconfig | 5 +++++ 1 file changed, 5 insertions(+)
arch/mips/ralink/Kconfig +5 -0
@@ -7,6 +7,11 @@ config CLKEVT_RT3352 select CLKSRC_OF select CLKSRC_MMIO +config RALINK_ILL_ACC + bool + depends on SOC_RT305X + default y + choice prompt "Ralink SoC selection" default SOC_RT305X
Patches currently in stable-queue which might be from [email protected] are
queue-4.0/mips-octeon-remove-udelay-causing-huge-irq-latency.patch queue-4.0/mips-makefile-fix-mips-ase-detection-code.patch queue-4.0/mips-r4kcache-use-correct-base-register-for-mips-r6-cache-flushes.patch queue-4.0/mips-fix-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-ralink-fix-bad-config-symbol-in-pci-makefile.patch queue-4.0/revert-mips-remove-race-window-in-page-fault-handling.patch queue-4.0/mips-fix-race-condition-in-lazy-cache-flushing.patch queue-4.0/mips-bcm63xx-move-bcm63xx_gpio_init-to-bcm63xx_register_devices.patch queue-4.0/mips-octeon-delete-override-of-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-asm-spinlock-fix-addiu-instruction-for-r10000_llsc_war-case.patch queue-4.0/mips-kconfig-disable-smp-cps-for-64-bit.patch queue-4.0/mips-bcm47xx-fix-detecting-microsoft-mn-700-asus-wl500g.patch queue-4.0/mips-octeon-use-correct-csr-to-soft-reset.patch queue-4.0/revert-mips-avoid-pipeline-stalls-on-some-mips32r2-cores.patch queue-4.0/mips-octeon-dma-octeon-fix-ohci-usb-config-check.patch queue-4.0/mips-octeon-fix-pci-interrupt-mapping-for-d-link-dsr-1000n.patch queue-4.0/mips-kconfig-fix-typo-for-the-r2-to-r6-emulator-kernel-parameter.patch queue-4.0/ssb-fix-kconfig-dependencies.patch queue-4.0/mips-kernel-entry.s-set-correct-isa-level-for-mips_ihb.patch queue-4.0/mips-netlogic-fix-for-sata-phy-init.patch queue-4.0/mips-ralink-add-missing-symbol-for-ralink_ill_acc.patch queue-4.0/mips-asm-elf-set-o32-default-fpu-flags.patch queue-4.0/mips-smp-cps-cpu_set-fpu-mask-if-fpu-present.patch
PATCH v2 19/23 MIPS: smp-cps: cpu_set FPU mask if FPU present
In reply to Ralf BaechleFrom: Niklas Cassel <[email protected]>
Commit 90db024f140d0d6ad960cc5f090e3c8ed890ca55 upstream.
If we have an FPU, enroll ourselves in the FPU-full mask. Matching the MT_SMP and CMP implementations of smp_setup.
Patchwork: https://patchwork.linux-mips.org/patch/8948/
--- arch/mips/kernel/smp-cps.c | 6 ++++++ 1 file changed, 6 insertions(+)
arch/mips/kernel/smp-cps.c +6 -0
@@ -88,6 +88,12 @@ static void __init cps_smp_setup(void)/* Make core 0 coherent with everything */ write_gcr_cl_coherence (0xff ); + +#ifdef CONFIG_MIPS_MT_FPAFF +/* If we have an FPU, enroll ourselves in the FPU-full mask */ +if (cpu_has_fpu) +cpu_set (0 , mt_fpu_cpumask); +#endif /* CONFIG_MIPS_MT_FPAFF */ }static void __init cps_prepare_cpus (unsigned int max_cpus)
Signature · 1 line
1.9.3
Patch "MIPS: smp-cps: cpu_set FPU mask if FPU present" has been added to the 4.0-stable tree
This is a note to let you know that I've just added the patch titled
MIPS: smp-cps: cpu_set FPU mask if FPU present
to the 4.0-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
mips-smp-cps-cpu_set-fpu-mask-if-fpu-present.patch
and it can be found in the queue-4.0 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From [email protected] Fri May 8 16:41:04 2015
From: Ralf Baechle <[email protected]>
Date: Thu, 15 Jan 2015 16:41:13 +0100
Subject: MIPS: smp-cps: cpu_set FPU mask if FPU present
To: [email protected]
Message-ID: <9c4e1e5b939e7699d945633fa8ca930aa555e8a4.1431087908.git.ralf@linux-mips.org>
From: Niklas Cassel <[email protected]>
Commit 90db024f140d0d6ad960cc5f090e3c8ed890ca55 upstream.
If we have an FPU, enroll ourselves in the FPU-full mask. Matching the MT_SMP and CMP implementations of smp_setup.
Patchwork: https://patchwork.linux-mips.org/patch/8948/
--- arch/mips/kernel/smp-cps.c | 6 ++++++ 1 file changed, 6 insertions(+)
arch/mips/kernel/smp-cps.c +6 -0
@@ -88,6 +88,12 @@ static void __init cps_smp_setup(void)/* Make core 0 coherent with everything */ write_gcr_cl_coherence (0xff ); + +#ifdef CONFIG_MIPS_MT_FPAFF +/* If we have an FPU, enroll ourselves in the FPU-full mask */ +if (cpu_has_fpu) +cpu_set (0 , mt_fpu_cpumask); +#endif /* CONFIG_MIPS_MT_FPAFF */ }static void __init cps_prepare_cpus (unsigned int max_cpus)
Patches currently in stable-queue which might be from [email protected] are
queue-4.0/mips-octeon-remove-udelay-causing-huge-irq-latency.patch queue-4.0/mips-makefile-fix-mips-ase-detection-code.patch queue-4.0/mips-r4kcache-use-correct-base-register-for-mips-r6-cache-flushes.patch queue-4.0/mips-fix-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-ralink-fix-bad-config-symbol-in-pci-makefile.patch queue-4.0/revert-mips-remove-race-window-in-page-fault-handling.patch queue-4.0/mips-fix-race-condition-in-lazy-cache-flushing.patch queue-4.0/mips-bcm63xx-move-bcm63xx_gpio_init-to-bcm63xx_register_devices.patch queue-4.0/mips-octeon-delete-override-of-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-asm-spinlock-fix-addiu-instruction-for-r10000_llsc_war-case.patch queue-4.0/mips-kconfig-disable-smp-cps-for-64-bit.patch queue-4.0/mips-bcm47xx-fix-detecting-microsoft-mn-700-asus-wl500g.patch queue-4.0/mips-octeon-use-correct-csr-to-soft-reset.patch queue-4.0/revert-mips-avoid-pipeline-stalls-on-some-mips32r2-cores.patch queue-4.0/mips-octeon-dma-octeon-fix-ohci-usb-config-check.patch queue-4.0/mips-octeon-fix-pci-interrupt-mapping-for-d-link-dsr-1000n.patch queue-4.0/mips-kconfig-fix-typo-for-the-r2-to-r6-emulator-kernel-parameter.patch queue-4.0/ssb-fix-kconfig-dependencies.patch queue-4.0/mips-kernel-entry.s-set-correct-isa-level-for-mips_ihb.patch queue-4.0/mips-netlogic-fix-for-sata-phy-init.patch queue-4.0/mips-ralink-add-missing-symbol-for-ralink_ill_acc.patch queue-4.0/mips-asm-elf-set-o32-default-fpu-flags.patch queue-4.0/mips-smp-cps-cpu_set-fpu-mask-if-fpu-present.patch
PATCH v2 20/23 MIPS: Kconfig: Disable SMP/CPS for 64-bit
In reply to Ralf BaechleFrom: Markos Chandras <[email protected]>
Commit 6ca716f2e5571d25a3899c6c5c91ff72ea6d6f5e upstream.
A 64-bit build for Malta produces far too many build problems when SMP/CPS is selected. Moreover, there is currently no 64-bit product with SMP/CPS so we disable SMP/CPS when building for 64-bit until it is properly supported.
Patchwork: https://patchwork.linux-mips.org/patch/8573/
--- arch/mips/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/mips/Kconfig +1 -1
@@ -2142,7 +2142,7 @@ config MIPS_CMP config MIPS_CPS bool "MIPS Coherent Processing System support" - depends on SYS_SUPPORTS_MIPS_CPS + depends on SYS_SUPPORTS_MIPS_CPS && !64BIT select MIPS_CM select MIPS_CPC select MIPS_CPS_PM if HOTPLUG_CPU
Signature · 1 line
1.9.3
Patch "MIPS: Kconfig: Disable SMP/CPS for 64-bit" has been added to the 4.0-stable tree
This is a note to let you know that I've just added the patch titled
MIPS: Kconfig: Disable SMP/CPS for 64-bit
to the 4.0-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
mips-kconfig-disable-smp-cps-for-64-bit.patch
and it can be found in the queue-4.0 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From [email protected] Fri May 8 16:41:14 2015
From: Ralf Baechle <[email protected]>
Date: Tue, 25 Nov 2014 09:15:45 +0000
Subject: MIPS: Kconfig: Disable SMP/CPS for 64-bit
To: [email protected]
Message-ID: <546f04059a2bc9e50a87375273190a7248ba578d.1431087908.git.ralf@linux-mips.org>
From: Markos Chandras <[email protected]>
Commit 6ca716f2e5571d25a3899c6c5c91ff72ea6d6f5e upstream.
A 64-bit build for Malta produces far too many build problems when SMP/CPS is selected. Moreover, there is currently no 64-bit product with SMP/CPS so we disable SMP/CPS when building for 64-bit until it is properly supported.
Patchwork: https://patchwork.linux-mips.org/patch/8573/
--- arch/mips/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/mips/Kconfig +1 -1
@@ -2142,7 +2142,7 @@ config MIPS_CMP config MIPS_CPS bool "MIPS Coherent Processing System support" - depends on SYS_SUPPORTS_MIPS_CPS + depends on SYS_SUPPORTS_MIPS_CPS && !64BIT select MIPS_CM select MIPS_CPC select MIPS_CPS_PM if HOTPLUG_CPU
Patches currently in stable-queue which might be from [email protected] are
queue-4.0/mips-octeon-remove-udelay-causing-huge-irq-latency.patch queue-4.0/mips-makefile-fix-mips-ase-detection-code.patch queue-4.0/mips-r4kcache-use-correct-base-register-for-mips-r6-cache-flushes.patch queue-4.0/mips-fix-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-ralink-fix-bad-config-symbol-in-pci-makefile.patch queue-4.0/revert-mips-remove-race-window-in-page-fault-handling.patch queue-4.0/mips-fix-race-condition-in-lazy-cache-flushing.patch queue-4.0/mips-bcm63xx-move-bcm63xx_gpio_init-to-bcm63xx_register_devices.patch queue-4.0/mips-octeon-delete-override-of-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-asm-spinlock-fix-addiu-instruction-for-r10000_llsc_war-case.patch queue-4.0/mips-kconfig-disable-smp-cps-for-64-bit.patch queue-4.0/mips-bcm47xx-fix-detecting-microsoft-mn-700-asus-wl500g.patch queue-4.0/mips-octeon-use-correct-csr-to-soft-reset.patch queue-4.0/revert-mips-avoid-pipeline-stalls-on-some-mips32r2-cores.patch queue-4.0/mips-octeon-dma-octeon-fix-ohci-usb-config-check.patch queue-4.0/mips-octeon-fix-pci-interrupt-mapping-for-d-link-dsr-1000n.patch queue-4.0/mips-kconfig-fix-typo-for-the-r2-to-r6-emulator-kernel-parameter.patch queue-4.0/ssb-fix-kconfig-dependencies.patch queue-4.0/mips-kernel-entry.s-set-correct-isa-level-for-mips_ihb.patch queue-4.0/mips-netlogic-fix-for-sata-phy-init.patch queue-4.0/mips-ralink-add-missing-symbol-for-ralink_ill_acc.patch queue-4.0/mips-asm-elf-set-o32-default-fpu-flags.patch queue-4.0/mips-smp-cps-cpu_set-fpu-mask-if-fpu-present.patch
PATCH v2 21/23 MIPS: BCM47XX: Fix detecting Microsoft MN-700 & Asus WL500G
In reply to Ralf BaechleFrom: Rafał Miłecki <[email protected]>
Commit 96f7c21363e0e0d19f3471f54a719ed06d708513 upstream.
Since the day of adding this code it was broken. We were iterating over a wrong array and checking for wrong NVRAM entry.
Patchwork: https://patchwork.linux-mips.org/patch/9654/
--- arch/mips/bcm47xx/board.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
arch/mips/bcm47xx/board.c +2 -2
@@ -247,8 +247,8 @@ static __init const struct bcm47xx_board_type *bcm47xx_board_get_nvram(void) }if (bcm47xx_nvram_getenv ("hardware_version" , buf1,sizeof (buf1)) >=0 && -bcm47xx_nvram_getenv ("boardtype" , buf2,sizeof (buf2)) >=0 ) { -for (e2 = bcm47xx_board_list_boot_hw; e2->value1; e2++) { +bcm47xx_nvram_getenv ("boardnum" , buf2,sizeof (buf2)) >=0 ) { +for (e2 = bcm47xx_board_list_hw_version_num; e2->value1; e2++) {if (!strstarts (buf1, e2->value1) && !strcmp (buf2, e2->value2))return &e2->board;
Signature · 1 line
1.9.3
Patch "MIPS: BCM47XX: Fix detecting Microsoft MN-700 & Asus WL500G" has been added to the 4.0-stable tree
This is a note to let you know that I've just added the patch titled
MIPS: BCM47XX: Fix detecting Microsoft MN-700 & Asus WL500G
to the 4.0-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
mips-bcm47xx-fix-detecting-microsoft-mn-700-asus-wl500g.patch
and it can be found in the queue-4.0 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From [email protected] Fri May 8 16:41:25 2015
From: Ralf Baechle <[email protected]>
Date: Wed, 1 Apr 2015 16:01:02 +0200
Subject: MIPS: BCM47XX: Fix detecting Microsoft MN-700 & Asus WL500G
To: [email protected]
Message-ID: <120826c332638c82e91d69cb98a0d305fd768b33.1431087908.git.ralf@linux-mips.org>
From: Rafał Miłecki <[email protected]>
Commit 96f7c21363e0e0d19f3471f54a719ed06d708513 upstream.
Since the day of adding this code it was broken. We were iterating over a wrong array and checking for wrong NVRAM entry.
Patchwork: https://patchwork.linux-mips.org/patch/9654/
--- arch/mips/bcm47xx/board.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
arch/mips/bcm47xx/board.c +2 -2
@@ -247,8 +247,8 @@ static __init const struct bcm47xx_board }if (bcm47xx_nvram_getenv ("hardware_version" , buf1,sizeof (buf1)) >=0 && -bcm47xx_nvram_getenv ("boardtype" , buf2,sizeof (buf2)) >=0 ) { -for (e2 = bcm47xx_board_list_boot_hw; e2->value1; e2++) { +bcm47xx_nvram_getenv ("boardnum" , buf2,sizeof (buf2)) >=0 ) { +for (e2 = bcm47xx_board_list_hw_version_num; e2->value1; e2++) {if (!strstarts (buf1, e2->value1) && !strcmp (buf2, e2->value2))return &e2->board;
Patches currently in stable-queue which might be from [email protected] are
queue-4.0/mips-octeon-remove-udelay-causing-huge-irq-latency.patch queue-4.0/mips-makefile-fix-mips-ase-detection-code.patch queue-4.0/mips-r4kcache-use-correct-base-register-for-mips-r6-cache-flushes.patch queue-4.0/mips-fix-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-ralink-fix-bad-config-symbol-in-pci-makefile.patch queue-4.0/revert-mips-remove-race-window-in-page-fault-handling.patch queue-4.0/mips-fix-race-condition-in-lazy-cache-flushing.patch queue-4.0/mips-bcm63xx-move-bcm63xx_gpio_init-to-bcm63xx_register_devices.patch queue-4.0/mips-octeon-delete-override-of-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-asm-spinlock-fix-addiu-instruction-for-r10000_llsc_war-case.patch queue-4.0/mips-kconfig-disable-smp-cps-for-64-bit.patch queue-4.0/mips-bcm47xx-fix-detecting-microsoft-mn-700-asus-wl500g.patch queue-4.0/mips-octeon-use-correct-csr-to-soft-reset.patch queue-4.0/revert-mips-avoid-pipeline-stalls-on-some-mips32r2-cores.patch queue-4.0/mips-octeon-dma-octeon-fix-ohci-usb-config-check.patch queue-4.0/mips-octeon-fix-pci-interrupt-mapping-for-d-link-dsr-1000n.patch queue-4.0/mips-kconfig-fix-typo-for-the-r2-to-r6-emulator-kernel-parameter.patch queue-4.0/ssb-fix-kconfig-dependencies.patch queue-4.0/mips-kernel-entry.s-set-correct-isa-level-for-mips_ihb.patch queue-4.0/mips-netlogic-fix-for-sata-phy-init.patch queue-4.0/mips-ralink-add-missing-symbol-for-ralink_ill_acc.patch queue-4.0/mips-asm-elf-set-o32-default-fpu-flags.patch queue-4.0/mips-smp-cps-cpu_set-fpu-mask-if-fpu-present.patch
PATCH v2 22/23 MIPS: asm: elf: Set O32 default FPU flags
In reply to Ralf BaechleFrom: Markos Chandras <[email protected]>
Commit 48f8eaee3f59848809644507fc47363b37e54450 upstream.
Set good default FPU flags (FR0) for O32 binaries similar to what the kernel does for the N64/N32 ones. This also fixes a regression introduced in commit 46490b572544 ("MIPS: kernel: elf: Improve the overall ABI and FPU mode checks") when MIPS_O32_FP64_SUPPORT is disabled. In that case, the mips_set_personality_fp() did not set the FPU mode at all because it assumed that the FPU mode was already set properly. That led to O32 userland problems.
Patchwork: http://patchwork.linux-mips.org/patch/9344/
--- arch/mips/include/asm/elf.h | 5 +++++ 1 file changed, 5 insertions(+)
arch/mips/include/asm/elf.h +5 -0
@@ -294,6 +294,9 @@ do { \if (personality (current->personality) !=PER_LINUX ) \set_personality (PER_LINUX ); \ \ +clear_thread_flag (TIF_HYBRID_FPREGS ); \ +set_thread_flag (TIF_32BIT_FPREGS ); \ + \mips_set_personality_fp (state); \ \ current->thread.abi = &mips_abi; \
@@ -319,6 +322,8 @@ do { \ do { \ set_thread_flag(TIF_32BIT_REGS); \ set_thread_flag(TIF_32BIT_ADDR); \ + clear_thread_flag(TIF_HYBRID_FPREGS); \ + set_thread_flag(TIF_32BIT_FPREGS); \ \ mips_set_personality_fp(state); \ \
Signature · 1 line
1.9.3
Patch "MIPS: asm: elf: Set O32 default FPU flags" has been added to the 4.0-stable tree
This is a note to let you know that I've just added the patch titled
MIPS: asm: elf: Set O32 default FPU flags
to the 4.0-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
mips-asm-elf-set-o32-default-fpu-flags.patch
and it can be found in the queue-4.0 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From [email protected] Fri May 8 16:41:33 2015
From: Ralf Baechle <[email protected]>
Date: Thu, 26 Feb 2015 11:11:30 +0000
Subject: MIPS: asm: elf: Set O32 default FPU flags
To: [email protected]
Message-ID: <f082010117c14678fa75a70db9862e89735ab6d6.1431087908.git.ralf@linux-mips.org>
From: Markos Chandras <[email protected]>
Commit 48f8eaee3f59848809644507fc47363b37e54450 upstream.
Set good default FPU flags (FR0) for O32 binaries similar to what the kernel does for the N64/N32 ones. This also fixes a regression introduced in commit 46490b572544 ("MIPS: kernel: elf: Improve the overall ABI and FPU mode checks") when MIPS_O32_FP64_SUPPORT is disabled. In that case, the mips_set_personality_fp() did not set the FPU mode at all because it assumed that the FPU mode was already set properly. That led to O32 userland problems.
Patchwork: http://patchwork.linux-mips.org/patch/9344/
--- arch/mips/include/asm/elf.h | 5 +++++ 1 file changed, 5 insertions(+)
arch/mips/include/asm/elf.h +5 -0
@@ -294,6 +294,9 @@ do { \if (personality (current->personality) !=PER_LINUX ) \set_personality (PER_LINUX ); \ \ +clear_thread_flag (TIF_HYBRID_FPREGS ); \ +set_thread_flag (TIF_32BIT_FPREGS ); \ + \mips_set_personality_fp (state); \ \ current->thread.abi = &mips_abi; \
@@ -319,6 +322,8 @@ do { \ do { \ set_thread_flag(TIF_32BIT_REGS); \ set_thread_flag(TIF_32BIT_ADDR); \ + clear_thread_flag(TIF_HYBRID_FPREGS); \ + set_thread_flag(TIF_32BIT_FPREGS); \ \ mips_set_personality_fp(state); \ \
Patches currently in stable-queue which might be from [email protected] are
queue-4.0/mips-octeon-remove-udelay-causing-huge-irq-latency.patch queue-4.0/mips-makefile-fix-mips-ase-detection-code.patch queue-4.0/mips-r4kcache-use-correct-base-register-for-mips-r6-cache-flushes.patch queue-4.0/mips-fix-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-ralink-fix-bad-config-symbol-in-pci-makefile.patch queue-4.0/revert-mips-remove-race-window-in-page-fault-handling.patch queue-4.0/mips-fix-race-condition-in-lazy-cache-flushing.patch queue-4.0/mips-bcm63xx-move-bcm63xx_gpio_init-to-bcm63xx_register_devices.patch queue-4.0/mips-octeon-delete-override-of-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-asm-spinlock-fix-addiu-instruction-for-r10000_llsc_war-case.patch queue-4.0/mips-kconfig-disable-smp-cps-for-64-bit.patch queue-4.0/mips-bcm47xx-fix-detecting-microsoft-mn-700-asus-wl500g.patch queue-4.0/mips-octeon-use-correct-csr-to-soft-reset.patch queue-4.0/revert-mips-avoid-pipeline-stalls-on-some-mips32r2-cores.patch queue-4.0/mips-octeon-dma-octeon-fix-ohci-usb-config-check.patch queue-4.0/mips-octeon-fix-pci-interrupt-mapping-for-d-link-dsr-1000n.patch queue-4.0/mips-kconfig-fix-typo-for-the-r2-to-r6-emulator-kernel-parameter.patch queue-4.0/ssb-fix-kconfig-dependencies.patch queue-4.0/mips-kernel-entry.s-set-correct-isa-level-for-mips_ihb.patch queue-4.0/mips-netlogic-fix-for-sata-phy-init.patch queue-4.0/mips-ralink-add-missing-symbol-for-ralink_ill_acc.patch queue-4.0/mips-asm-elf-set-o32-default-fpu-flags.patch queue-4.0/mips-smp-cps-cpu_set-fpu-mask-if-fpu-present.patch
PATCH v2 23/23 MIPS: Makefile: Fix MIPS ASE detection code
In reply to Ralf BaechleFrom: Markos Chandras <[email protected]>
Commit 5306a5450824691e27d68f711758515debedeeac upstream.
Commit 32098ec7bcba ("MIPS: Makefile: Move the ASEs checks after setting the core's CFLAGS") re-arranged the MIPS ASE detection code and also added the current cflags to the detection logic. However, this introduced a few bugs. First of all, the mips-cflags should not be quoted since that ends up being passed as a string to subsequent commands leading to broken detection from the cc-option-* tools. Moreover, in order to avoid duplicating the cflags-y because of how cc-option works, we rework the logic so we pass only those cflags which are needed by the selected ASE. Finally, fix some typos resulting in MSA not being detected correctly.
Patchwork: https://patchwork.linux-mips.org/patch/9661/
--- arch/mips/Makefile | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-)
arch/mips/Makefile +10 -4
@@ -197,11 +197,17 @@ endif # Warning: the 64-bit MIPS architecture does not support the `smartmips' extension # Pass -Wa,--no-warn to disable all assembler warnings until the kernel code has # been fixed properly. -mips-cflags := "$(cflags-y)" -cflags-$(CONFIG_CPU_HAS_SMARTMIPS) += $(call cc-option,$(mips-cflags),-msmartmips) -Wa,--no-warn -cflags-$(CONFIG_CPU_MICROMIPS) += $(call cc-option,$(mips-cflags),-mmicromips) +mips-cflags := $(cflags-y) +ifeq ($(CONFIG_CPU_HAS_SMARTMIPS),y) +smartmips-ase := $(call cc-option-yn,$(mips-cflags) -msmartmips) +cflags-$(smartmips-ase) += -msmartmips -Wa,--no-warn +endif +ifeq ($(CONFIG_CPU_MICROMIPS),y) +micromips-ase := $(call cc-option-yn,$(mips-cflags) -mmicromips) +cflags-$(micromips-ase) += -mmicromips +endif ifeq ($(CONFIG_CPU_HAS_MSA),y) -toolchain-msa := $(call cc-option-yn,-$(mips-cflags),mhard-float -mfp64 -Wa$(comma)-mmsa) +toolchain-msa := $(call cc-option-yn,$(mips-cflags) -mhard-float -mfp64 -Wa$(comma)-mmsa) cflags-$(toolchain-msa) += -DTOOLCHAIN_SUPPORTS_MSA endif
Signature · 1 line
1.9.3
Patch "MIPS: Makefile: Fix MIPS ASE detection code" has been added to the 4.0-stable tree
This is a note to let you know that I've just added the patch titled
MIPS: Makefile: Fix MIPS ASE detection code
to the 4.0-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
mips-makefile-fix-mips-ase-detection-code.patch
and it can be found in the queue-4.0 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From [email protected] Fri May 8 16:41:43 2015
From: Ralf Baechle <[email protected]>
Date: Thu, 2 Apr 2015 14:42:52 +0100
Subject: MIPS: Makefile: Fix MIPS ASE detection code
To: [email protected]
Message-ID: <6c0628970f5549f2ceceb5c5814587f2d5064723.1431087908.git.ralf@linux-mips.org>
From: Markos Chandras <[email protected]>
Commit 5306a5450824691e27d68f711758515debedeeac upstream.
Commit 32098ec7bcba ("MIPS: Makefile: Move the ASEs checks after setting the core's CFLAGS") re-arranged the MIPS ASE detection code and also added the current cflags to the detection logic. However, this introduced a few bugs. First of all, the mips-cflags should not be quoted since that ends up being passed as a string to subsequent commands leading to broken detection from the cc-option-* tools. Moreover, in order to avoid duplicating the cflags-y because of how cc-option works, we rework the logic so we pass only those cflags which are needed by the selected ASE. Finally, fix some typos resulting in MSA not being detected correctly.
Patchwork: https://patchwork.linux-mips.org/patch/9661/
--- arch/mips/Makefile | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-)
arch/mips/Makefile +10 -4
@@ -197,11 +197,17 @@ endif # Warning: the 64-bit MIPS architecture does not support the `smartmips' extension # Pass -Wa,--no-warn to disable all assembler warnings until the kernel code has # been fixed properly. -mips-cflags := "$(cflags-y)" -cflags-$(CONFIG_CPU_HAS_SMARTMIPS) += $(call cc-option,$(mips-cflags),-msmartmips) -Wa,--no-warn -cflags-$(CONFIG_CPU_MICROMIPS) += $(call cc-option,$(mips-cflags),-mmicromips) +mips-cflags := $(cflags-y) +ifeq ($(CONFIG_CPU_HAS_SMARTMIPS),y) +smartmips-ase := $(call cc-option-yn,$(mips-cflags) -msmartmips) +cflags-$(smartmips-ase) += -msmartmips -Wa,--no-warn +endif +ifeq ($(CONFIG_CPU_MICROMIPS),y) +micromips-ase := $(call cc-option-yn,$(mips-cflags) -mmicromips) +cflags-$(micromips-ase) += -mmicromips +endif ifeq ($(CONFIG_CPU_HAS_MSA),y) -toolchain-msa := $(call cc-option-yn,-$(mips-cflags),mhard-float -mfp64 -Wa$(comma)-mmsa) +toolchain-msa := $(call cc-option-yn,$(mips-cflags) -mhard-float -mfp64 -Wa$(comma)-mmsa) cflags-$(toolchain-msa) += -DTOOLCHAIN_SUPPORTS_MSA endif
Patches currently in stable-queue which might be from [email protected] are
queue-4.0/mips-octeon-remove-udelay-causing-huge-irq-latency.patch queue-4.0/mips-makefile-fix-mips-ase-detection-code.patch queue-4.0/mips-r4kcache-use-correct-base-register-for-mips-r6-cache-flushes.patch queue-4.0/mips-fix-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-ralink-fix-bad-config-symbol-in-pci-makefile.patch queue-4.0/revert-mips-remove-race-window-in-page-fault-handling.patch queue-4.0/mips-fix-race-condition-in-lazy-cache-flushing.patch queue-4.0/mips-bcm63xx-move-bcm63xx_gpio_init-to-bcm63xx_register_devices.patch queue-4.0/mips-octeon-delete-override-of-cpu_has_mips_r2_exec_hazard.patch queue-4.0/mips-asm-spinlock-fix-addiu-instruction-for-r10000_llsc_war-case.patch queue-4.0/mips-kconfig-disable-smp-cps-for-64-bit.patch queue-4.0/mips-bcm47xx-fix-detecting-microsoft-mn-700-asus-wl500g.patch queue-4.0/mips-octeon-use-correct-csr-to-soft-reset.patch queue-4.0/revert-mips-avoid-pipeline-stalls-on-some-mips32r2-cores.patch queue-4.0/mips-octeon-dma-octeon-fix-ohci-usb-config-check.patch queue-4.0/mips-octeon-fix-pci-interrupt-mapping-for-d-link-dsr-1000n.patch queue-4.0/mips-kconfig-fix-typo-for-the-r2-to-r6-emulator-kernel-parameter.patch queue-4.0/ssb-fix-kconfig-dependencies.patch queue-4.0/mips-kernel-entry.s-set-correct-isa-level-for-mips_ihb.patch queue-4.0/mips-netlogic-fix-for-sata-phy-init.patch queue-4.0/mips-ralink-add-missing-symbol-for-ralink_ill_acc.patch queue-4.0/mips-asm-elf-set-o32-default-fpu-flags.patch queue-4.0/mips-smp-cps-cpu_set-fpu-mask-if-fpu-present.patch