Add SDHCI support for APM X-Gene SoC using ARASAN SDHCI controller.
Subsystems (4)
v7 cover Add SDHCI support for APM X-Gene SoC using ARASAN SDHCI controller.
This patch adds the SDHCI support for APM X-Gene SoC using ARASAN SDHCI controller.
v1 change:
* Use the CONFIG_ARM64_DMA_HAS_IOMMU for dma-mapping.
v2 change:
* Drop the IOMMU support and switching to PIO mode for arasan. controller integrated inside APM X-Gene SoC.
v3 change:
* Change the sdhci-of-arasan.c to support arasan4.9a.
* Add quirks for arasan4.9a.
v4 change:
* Cleanup the Documentation and dts.
v5 change:
* Rebase the dts files.
* Drop patch 2 and 3 as it is applied.
v6 change:
* Clean the unrequired properties from dts.
* Rename sdhc to sdhci.
* support to disable timming using capability register read.
v7 change:
* Rename sdhci nodes to mmc.
---
Suman Tripathi (2):
arm64: dts: Add the arasan mmc nodes in apm-storm.dtsi
mmc: host: sdhci: Add support to disable SDR104/SDR50/DDR50 based on
capability register 0.
arch/arm64/boot/dts/apm/apm-mustang.dts | 4 +++ arch/arm64/boot/dts/apm/apm-storm.dtsi | 43 +++++++++++++++++++++++++++++++++ drivers/mmc/host/sdhci.c | 3 ++- 3 files changed, 49 insertions(+), 1 deletion(-)
--
1.8.2.1
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PATCH v7 1/2 arm64: dts: Add the arasan mmc nodes in apm-storm.dtsi
This patch adds the arasan mmc nodes to reuse the of-arasan driver for APM X-Gene SoC.
---
--- arch/arm64/boot/dts/apm/apm-mustang.dts | 4 +++ arch/arm64/boot/dts/apm/apm-storm.dtsi | 43 +++++++++++++++++++++++++++++++++ 2 files changed, 47 insertions(+)
arch/arm64/boot/dts/apm/apm-mustang.dts +4 -0
@@ -52,3 +52,7 @@ &xgenet { status = "ok"; }; + +&mmc0 { + status = "ok"; +};
arch/arm64/boot/dts/apm/apm-storm.dtsi +43 -0
55 lines not on this page · raw message
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1.8.2.1
PATCH v7 1/2 arm64: dts: Add the arasan mmc nodes in apm-storm.dtsi
Hi Arnd,
Quoted 84 lines · Suman Tripathi
This patch adds the arasan mmc nodes to reuse the of-arasan driver for APM X-Gene SoC.
Signed-off-by Suman Tripathi <[email protected]>---
--- arch/arm64/boot/dts/apm/apm-mustang.dts | 4 +++ arch/arm64/boot/dts/apm/apm-storm.dtsi | 43 +++++++++++++++++++++++++++++++++ 2 files changed, 47 insertions(+)arch/arm64/boot/dts/apm/apm-mustang.dts +4
-0@@ -52,3 +52,7 @@ &xgenet { status = "ok"; }; + +&mmc0 { + status = "ok"; +};arch/arm64/boot/dts/apm/apm-storm.dtsi +43
-1@@ -145,6 +145,40 @@ clock-output-names = "socplldiv2"; }; + ahbclk: ahbclk at 1f2ac000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + reg = <0x0 0x1f2ac000 0x0 0x1000 + 0x0 0x17000000 0x0 0x2000>; + reg-names = "csr-reg", "div-reg"; + csr-offset = <0x0>; + csr-mask = <0x1>; + enable-offset = <0x8>; + enable-mask = <0x1>; + divider-offset = <0x164>; + divider-width = <0x5>; + divider-shift = <0x0>; + clock-output-names = "ahbclk"; + }; + + sdioclk: sdioclk at 1f2ac000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + reg = <0x0 0x1f2ac000 0x0 0x1000 + 0x0 0x17000000 0x0 0x2000>; + reg-names = "csr-reg", "div-reg"; + csr-offset = <0x0>; + csr-mask = <0x2>; + enable-offset = <0x8>; + enable-mask = <0x2>; + divider-offset = <0x178>; + divider-width = <0x8>; + divider-shift = <0x0>; + clock-output-names = "sdioclk"; + }; + qmlclk: qmlclk { compatible = "apm,xgene-device-clock"; #clock-cells = <1>;@@ -533,6 +567,15 @@ interrupts = <0x0 0x4f 0x4>; }; + mmc0: mmc at 1c000000 { + compatible = "arasan,sdhci-4.9a"; + reg = <0x0 0x1c000000 0x0 0x100>; + interrupts = <0x0 0x49 0x4>; + dma-coherent; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&sdioclk 0>, <&ahbclk 0>; + }; + phy1: phy at 1f21a000 { compatible = "apm,xgene-phy"; reg = <0x0 0x1f21a000 0x0 0x100>; --
Quoted 2 lines
1.8.2.1
Can you review this ?
Signature · 3 lines
Thanks, with regards, Suman Tripathi
PATCH v7 1/2 arm64: dts: Add the arasan mmc nodes in apm-storm.dtsi
Hi Arnd and all
Quoted 83 lines · Suman Tripathi
Hi Arnd,
Quoted 80 lines · Suman Tripathi
This patch adds the arasan mmc nodes to reuse the of-arasan driver for APM X-Gene SoC.
Signed-off-by Suman Tripathi <[email protected]>---
--- arch/arm64/boot/dts/apm/apm-mustang.dts | 4 +++ arch/arm64/boot/dts/apm/apm-storm.dtsi | 43 +++++++++++++++++++++++++++++++++ 2 files changed, 47 insertions(+)arch/arm64/boot/dts/apm/apm-mustang.dts +4
-0@@ -52,3 +52,7 @@ &xgenet { status = "ok"; }; + +&mmc0 { + status = "ok"; +};arch/arm64/boot/dts/apm/apm-storm.dtsi +43
-0@@ -145,6 +145,40 @@ clock-output-names = "socplldiv2"; }; + ahbclk: ahbclk at 1f2ac000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + reg = <0x0 0x1f2ac000 0x0 0x1000 + 0x0 0x17000000 0x0 0x2000>; + reg-names = "csr-reg", "div-reg"; + csr-offset = <0x0>; + csr-mask = <0x1>; + enable-offset = <0x8>; + enable-mask = <0x1>; + divider-offset = <0x164>; + divider-width = <0x5>; + divider-shift = <0x0>; + clock-output-names = "ahbclk"; + }; + + sdioclk: sdioclk at 1f2ac000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + reg = <0x0 0x1f2ac000 0x0 0x1000 + 0x0 0x17000000 0x0 0x2000>; + reg-names = "csr-reg", "div-reg"; + csr-offset = <0x0>; + csr-mask = <0x2>; + enable-offset = <0x8>; + enable-mask = <0x2>; + divider-offset = <0x178>; + divider-width = <0x8>; + divider-shift = <0x0>; + clock-output-names = "sdioclk"; + }; + qmlclk: qmlclk { compatible = "apm,xgene-device-clock"; #clock-cells = <1>;@@ -533,6 +567,15 @@ interrupts = <0x0 0x4f 0x4>; }; + mmc0: mmc at 1c000000 { + compatible = "arasan,sdhci-4.9a"; + reg = <0x0 0x1c000000 0x0 0x100>; + interrupts = <0x0 0x49 0x4>; + dma-coherent; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&sdioclk 0>, <&ahbclk 0>; + }; +
Quoted 8 lines
Quoted 6 lines
arch/arm64/boot/dts/apm/apm-storm.dtsi +0
-1phy1: phy at 1f21a000 { compatible = "apm,xgene-phy"; reg = <0x0 0x1f21a000 0x0 0x100>; --1.8.2.1
Can you review this ?
Sorry to bother on this again . Can you review it ?
Quoted 6 lines
--
Thanks,
with regards,
Suman Tripathi
Signature · 3 lines
Thanks, with regards, Suman Tripathi
A message that is not in the archive (sent off-list or not yet received): 1431517912-10322-1-git-send-email-stripathi-qTEPVZfXA3Y@public.gmane.org
PATCH v7 2/2 mmc: host: sdhci: Add support to disable SDR104/SDR50/DDR50 based on capability register 0.
The sdhci framework disables SDR104/SDR50/DDR50 based on only quirk. This patch adds the support to disable SDR104/SDR50/DDR50 based on reading the capability register 0.
---
--- drivers/mmc/host/sdhci.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
drivers/mmc/host/sdhci.c +2 -1
@@ -3118,7 +3118,8 @@ int sdhci_add_host(struct sdhci_host *host) } } -if (host->quirks2 &SDHCI_QUIRK2_NO_1_8_V ) +if (host->quirks2 &SDHCI_QUIRK2_NO_1_8_V || + !(caps[0 ] &SDHCI_CAN_VDD_180 )) caps[1 ] &= ~(SDHCI_SUPPORT_SDR104 |SDHCI_SUPPORT_SDR50 |SDHCI_SUPPORT_DDR50 );
--
1.8.2.1
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PATCH v7 2/2 mmc: host: sdhci: Add support to disable SDR104/SDR50/DDR50 based on capability register 0.
Quoted 25 lines · Suman Tripathi
The sdhci framework disables SDR104/SDR50/DDR50 based on only quirk. This patch adds the support to disable SDR104/SDR50/DDR50 based on reading the capability register 0.
Signed-off-by Suman Tripathi <[email protected]>---
--- drivers/mmc/host/sdhci.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)drivers/mmc/host/sdhci.c +2
-2@@ -3118,7 +3118,8 @@ int sdhci_add_host(struct sdhci_host *host) } } -if (host->quirks2 &SDHCI_QUIRK2_NO_1_8_V ) +if (host->quirks2 &SDHCI_QUIRK2_NO_1_8_V || + !(caps[0 ] &SDHCI_CAN_VDD_180 )) caps[1 ] &= ~(SDHCI_SUPPORT_SDR104 |SDHCI_SUPPORT_SDR50 |SDHCI_SUPPORT_DDR50 ); --
Quoted 2 lines
1.8.2.1
I didn't get any comments on this patch . Can anyone review it (Michal , Ulf , Arnd etc ...)?
Signature · 3 lines
Thanks, with regards, Suman Tripathi