arm64: tegra: Add Tegra132 support
Subsystems (4)
PATCH 1/6 arm64: tegra: Add Tegra132 support
From: Thierry Reding <[email protected]>
NVIDIA Tegra132 (also known as Tegra K1 64-bit) is a variant of Tegra124 but with 2 Denver CPUs instead of the 4+1 Cortex-A15. This adds the DTSI file for the SoC, which is mostly similar to the one for Tegra124.
Based on work by Allen Martin <[email protected]>
--- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/nvidia/Makefile | 2 + arch/arm64/boot/dts/nvidia/tegra132.dtsi | 990 +++++++++++++++++++++++++++++++ 3 files changed, 993 insertions(+) create mode 100644 arch/arm64/boot/dts/nvidia/Makefile create mode 100644 arch/arm64/boot/dts/nvidia/tegra132.dtsi
arch/arm64/boot/dts/Makefile +1 -0
@@ -5,6 +5,7 @@ dts-dirs += cavium dts-dirs += exynos dts-dirs += freescale dts-dirs += mediatek +dts-dirs += nvidia dts-dirs += qcom dts-dirs += sprd dts-dirs += xilinx
arch/arm64/boot/dts/nvidia/Makefile new file +2 -0
@@ -0,0 +1,2 @@ +always := $(dtb-y) +clean-files := *.dtb
arch/arm64/boot/dts/nvidia/tegra132.dtsi new file +990 -0
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2.3.5
PATCH 2/6 arm64: tegra: Add NVIDIA Tegra132 Norrin support
From: Thierry Reding <[email protected]>
Norrin is a Tegra132-based FFD used as reference platform within NVIDIA.
Based on work by Allen Martin <[email protected]>
--- arch/arm64/boot/dts/nvidia/Makefile | 2 + arch/arm64/boot/dts/nvidia/tegra132-norrin.dts | 1130 ++++++++++++++++++++++++ 2 files changed, 1132 insertions(+) create mode 100644 arch/arm64/boot/dts/nvidia/tegra132-norrin.dts
arch/arm64/boot/dts/nvidia/Makefile +2 -0
@@ -1,2 +1,4 @@ +dtb-$(CONFIG_ARCH_TEGRA) += tegra132-norrin.dtb + always := $(dtb-y) clean-files := *.dtb
arch/arm64/boot/dts/nvidia/tegra132-norrin.dts new file +1130 -0
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2.3.5
PATCH 3/6 arm64: tegra: Add Tegra210 support
In reply to Thierry RedingFrom: Thierry Reding <[email protected]>
NVIDIA Tegra210 (also known as Tegra X1) has four Cortex-A57 and four Cortex-A53 CPUs. Compared to Tegra124 and Tegra132 it comes with a 256- core Maxwell GPU. It supports processing videos of up to 4K resolutions at 60 fps (H.265, VP9, H.264).
--- arch/arm64/Kconfig | 9 + arch/arm64/boot/dts/nvidia/tegra210.dtsi | 998 +++++++++++++++++++++++++++++++ 2 files changed, 1007 insertions(+) create mode 100644 arch/arm64/boot/dts/nvidia/tegra210.dtsi
arch/arm64/Kconfig +9 -0
@@ -225,6 +225,15 @@ config ARCH_TEGRA_132_SOC but contains an NVIDIA Denver CPU complex in place of Tegra124's "4+1" Cortex-A15 CPU complex. +config ARCH_TEGRA_210_SOC + bool "NVIDIA Tegra210 SoC" + depends on ARCH_TEGRA + select PINCTRL_TEGRA210 + select USB_ULPI if USB_PHY + select USB_ULPI_VIEWPORT if USB_PHY + help + Enable support for the NVIDIA Tegra210 SoC. + config ARCH_SPRD bool "Spreadtrum SoC platform" help
arch/arm64/boot/dts/nvidia/tegra210.dtsi new file +998 -0
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2.3.5
Catalin Marinas
maintainerPATCH 3/6 arm64: tegra: Add Tegra210 support
Quoted 21 lines · Thierry Reding
From: Thierry Reding <[email protected]>
NVIDIA Tegra210 (also known as Tegra X1) has four Cortex-A57 and four Cortex-A53 CPUs. Compared to Tegra124 and Tegra132 it comes with a 256- core Maxwell GPU. It supports processing videos of up to 4K resolutions at 60 fps (H.265, VP9, H.264).
Signed-off-by Thierry Reding <[email protected]>--- arch/arm64/Kconfig | 9 + arch/arm64/boot/dts/nvidia/tegra210.dtsi | 998 +++++++++++++++++++++++++++++++ 2 files changed, 1007 insertions(+) create mode 100644 arch/arm64/boot/dts/nvidia/tegra210.dtsiarch/arm64/Kconfig +0
-0@@ -225,6 +225,15 @@ config ARCH_TEGRA_132_SOC but contains an NVIDIA Denver CPU complex in place of Tegra124's "4+1" Cortex-A15 CPU complex.
arch/arm64/Kconfig config ARCH_TEGRA_132_SOC · line 236
Quoted 10 lines
arch/arm64/Kconfig +9
-0+config ARCH_TEGRA_210_SOC + bool "NVIDIA Tegra210 SoC" + depends on ARCH_TEGRA + select PINCTRL_TEGRA210 + select USB_ULPI if USB_PHY + select USB_ULPI_VIEWPORT if USB_PHY + help + Enable support for the NVIDIA Tegra210 SoC. +
The previous ARCH_TEGRA_132_SOC escaped me. Do we need all these ARCH_TEGRA_*_SOC entries? Can we not have per-driver Kconfig options? For example, ARCH_TEGRA_132_SOC seems to be only used in drivers/clk/tegra, a specific Kconfig entry in there would suffice.
Signature · 1 line
Catalin
PATCH 3/6 arm64: tegra: Add Tegra210 support
Quoted 23 lines · Catalin Marinas
Quoted 22 lines · Thierry Reding
From: Thierry Reding <[email protected]>
NVIDIA Tegra210 (also known as Tegra X1) has four Cortex-A57 and four Cortex-A53 CPUs. Compared to Tegra124 and Tegra132 it comes with a 256- core Maxwell GPU. It supports processing videos of up to 4K resolutions at 60 fps (H.265, VP9, H.264).
Signed-off-by Thierry Reding <[email protected]>--- arch/arm64/Kconfig | 9 + arch/arm64/boot/dts/nvidia/tegra210.dtsi | 998 +++++++++++++++++++++++++++++++ 2 files changed, 1007 insertions(+) create mode 100644 arch/arm64/boot/dts/nvidia/tegra210.dtsiarch/arm64/Kconfig +0
-0@@ -225,6 +225,15 @@ config ARCH_TEGRA_132_SOC but contains an NVIDIA Denver CPU complex in place of Tegra124's "4+1" Cortex-A15 CPU complex.
Quoted 14 lines
arch/arm64/Kconfig config ARCH_TEGRA_132_SOC · line 236
Quoted 9 lines
arch/arm64/Kconfig +9
-0+config ARCH_TEGRA_210_SOC + bool "NVIDIA Tegra210 SoC" + depends on ARCH_TEGRA + select PINCTRL_TEGRA210 + select USB_ULPI if USB_PHY + select USB_ULPI_VIEWPORT if USB_PHY + help + Enable support for the NVIDIA Tegra210 SoC. +The previous
ARCH_TEGRA_132_SOCescaped me. Do we need all these ARCH_TEGRA_*_SOC entries? Can we not have per-driverKconfigoptions? For example,ARCH_TEGRA_132_SOCseems to be only used indrivers/clk/tegra, a specificKconfigentry in there would suffice.
There are actually a couple of other places where this will be used in subsequent patches (e.g. memory controller driver). The idea behind having these is that each one of them is used to enable the essentials out of the box, so that people don't have to go and enable a bunch of driver-specific Kconfig options just to get a kernel configuration that can actually boot.
This is also useful for integrators since they can simply omit all SoC generations that they're not interested in. Having a per-SoC option provides an easy way of doing so.
Thierry
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Catalin Marinas
maintainerPATCH 3/6 arm64: tegra: Add Tegra210 support
Quoted 39 lines · Thierry Reding
Quoted 23 lines · Catalin Marinas
Quoted 22 lines · Thierry Reding
From: Thierry Reding <[email protected]>
NVIDIA Tegra210 (also known as Tegra X1) has four Cortex-A57 and four Cortex-A53 CPUs. Compared to Tegra124 and Tegra132 it comes with a 256- core Maxwell GPU. It supports processing videos of up to 4K resolutions at 60 fps (H.265, VP9, H.264).
Signed-off-by Thierry Reding <[email protected]>--- arch/arm64/Kconfig | 9 + arch/arm64/boot/dts/nvidia/tegra210.dtsi | 998 +++++++++++++++++++++++++++++++ 2 files changed, 1007 insertions(+) create mode 100644 arch/arm64/boot/dts/nvidia/tegra210.dtsiarch/arm64/Kconfig +0
-0@@ -225,6 +225,15 @@ config ARCH_TEGRA_132_SOC but contains an NVIDIA Denver CPU complex in place of Tegra124's "4+1" Cortex-A15 CPU complex.Quoted 14 lines
arch/arm64/Kconfig config ARCH_TEGRA_132_SOC · line 236
Quoted 9 lines
arch/arm64/Kconfig +9
-0+config ARCH_TEGRA_210_SOC + bool "NVIDIA Tegra210 SoC" + depends on ARCH_TEGRA + select PINCTRL_TEGRA210 + select USB_ULPI if USB_PHY + select USB_ULPI_VIEWPORT if USB_PHY + help + Enable support for the NVIDIA Tegra210 SoC. +The previous
ARCH_TEGRA_132_SOCescaped me. Do we need all these ARCH_TEGRA_*_SOC entries? Can we not have per-driverKconfigoptions? For example,ARCH_TEGRA_132_SOCseems to be only used indrivers/clk/tegra, a specificKconfigentry in there would suffice.
Quoted 6 lines
There are actually a couple of other places where this will be used in subsequent patches (e.g. memory controller driver). The idea behind having these is that each one of them is used to enable the essentials out of the box, so that people don't have to go and enable a bunch of driver-specific
Kconfigoptions just to get a kernel configuration that can actually boot.
We debated whether to have ARCH_* options at all on arm64 and we settled for the middle ground - only add them for SoC families, not individual SoCs. As for the kernel configuration that actually boots, we want the arm64 defconfig to include all the supported SoCs and drivers (though longer term I'd like to see more drivers built as modules by default).
Quoted 3 lines
This is also useful for integrators since they can simply omit all SoC generations that they're not interested in. Having a per-SoC option provides an easy way of doing so.
The integrators could just select a SoC family and trim down unwanted options, I don't think they rely on the kernel defconfig for a final product. If this becomes an issue, I would rather have per-SoC defconfigs than lots of Kconfig entries.
Signature · 1 line
Catalin
PATCH 3/6 arm64: tegra: Add Tegra210 support
Quoted 53 lines · Catalin Marinas
Quoted 39 lines · Thierry Reding
Quoted 23 lines · Catalin Marinas
Quoted 22 lines · Thierry Reding
From: Thierry Reding <[email protected]>
NVIDIA Tegra210 (also known as Tegra X1) has four Cortex-A57 and four Cortex-A53 CPUs. Compared to Tegra124 and Tegra132 it comes with a 256- core Maxwell GPU. It supports processing videos of up to 4K resolutions at 60 fps (H.265, VP9, H.264).
Signed-off-by Thierry Reding <[email protected]>--- arch/arm64/Kconfig | 9 + arch/arm64/boot/dts/nvidia/tegra210.dtsi | 998 +++++++++++++++++++++++++++++++ 2 files changed, 1007 insertions(+) create mode 100644 arch/arm64/boot/dts/nvidia/tegra210.dtsiarch/arm64/Kconfig +0
-0@@ -225,6 +225,15 @@ config ARCH_TEGRA_132_SOC but contains an NVIDIA Denver CPU complex in place of Tegra124's "4+1" Cortex-A15 CPU complex.Quoted 14 lines
arch/arm64/Kconfig config ARCH_TEGRA_132_SOC · line 236
Quoted 9 lines
arch/arm64/Kconfig +9
-0+config ARCH_TEGRA_210_SOC + bool "NVIDIA Tegra210 SoC" + depends on ARCH_TEGRA + select PINCTRL_TEGRA210 + select USB_ULPI if USB_PHY + select USB_ULPI_VIEWPORT if USB_PHY + help + Enable support for the NVIDIA Tegra210 SoC. +The previous
ARCH_TEGRA_132_SOCescaped me. Do we need all these ARCH_TEGRA_*_SOC entries? Can we not have per-driverKconfigoptions? For example,ARCH_TEGRA_132_SOCseems to be only used indrivers/clk/tegra, a specificKconfigentry in there would suffice.Quoted 6 lines
There are actually a couple of other places where this will be used in subsequent patches (e.g. memory controller driver). The idea behind having these is that each one of them is used to enable the essentials out of the box, so that people don't have to go and enable a bunch of driver-specific
Kconfigoptions just to get a kernel configuration that can actually boot.We debated whether to have ARCH_* options at all on arm64 and we settled for the middle ground - only add them for SoC families, not individual SoCs. As for the kernel configuration that actually boots, we want the arm64 defconfig to include all the supported SoCs and drivers (though longer term I'd like to see more drivers built as modules by default).
Quoted 8 lines
Quoted 3 lines
This is also useful for integrators since they can simply omit all SoC generations that they're not interested in. Having a per-SoC option provides an easy way of doing so.
The integrators could just select a SoC family and trim down unwanted options, I don't think they rely on the kernel defconfig for a final product. If this becomes an issue, I would rather have per-SoC defconfigs than lots of
Kconfigentries.
I understand the desire to start with a clean plate on a new architecture, but Tegra has worked like this for the past 5 years and it's worked out really well for us. So I'm reluctant to introduce these inconsistencies merely because 64-bit ARM now lives in a different directory.
Are you concerned about arch/arm64/Kconfig growing wild? If so we could easily move these configuration options outside to something like drivers/soc/tegra/Kconfig. While at it, we could move existing options from arch/arm/mach-tegra over to that as well.
Thierry
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Catalin Marinas
maintainerPATCH 3/6 arm64: tegra: Add Tegra210 support
Quoted 63 lines · Thierry Reding
Quoted 53 lines · Catalin Marinas
Quoted 39 lines · Thierry Reding
Quoted 23 lines · Catalin Marinas
Quoted 22 lines · Thierry Reding
From: Thierry Reding <[email protected]>
NVIDIA Tegra210 (also known as Tegra X1) has four Cortex-A57 and four Cortex-A53 CPUs. Compared to Tegra124 and Tegra132 it comes with a 256- core Maxwell GPU. It supports processing videos of up to 4K resolutions at 60 fps (H.265, VP9, H.264).
Signed-off-by Thierry Reding <[email protected]>--- arch/arm64/Kconfig | 9 + arch/arm64/boot/dts/nvidia/tegra210.dtsi | 998 +++++++++++++++++++++++++++++++ 2 files changed, 1007 insertions(+) create mode 100644 arch/arm64/boot/dts/nvidia/tegra210.dtsiarch/arm64/Kconfig +0
-0@@ -225,6 +225,15 @@ config ARCH_TEGRA_132_SOC but contains an NVIDIA Denver CPU complex in place of Tegra124's "4+1" Cortex-A15 CPU complex.Quoted 14 lines
arch/arm64/Kconfig config ARCH_TEGRA_132_SOC · line 236
Quoted 9 lines
arch/arm64/Kconfig +9
-0+config ARCH_TEGRA_210_SOC + bool "NVIDIA Tegra210 SoC" + depends on ARCH_TEGRA + select PINCTRL_TEGRA210 + select USB_ULPI if USB_PHY + select USB_ULPI_VIEWPORT if USB_PHY + help + Enable support for the NVIDIA Tegra210 SoC. +The previous
ARCH_TEGRA_132_SOCescaped me. Do we need all these ARCH_TEGRA_*_SOC entries? Can we not have per-driverKconfigoptions? For example,ARCH_TEGRA_132_SOCseems to be only used indrivers/clk/tegra, a specificKconfigentry in there would suffice.Quoted 6 lines
There are actually a couple of other places where this will be used in subsequent patches (e.g. memory controller driver). The idea behind having these is that each one of them is used to enable the essentials out of the box, so that people don't have to go and enable a bunch of driver-specific
Kconfigoptions just to get a kernel configuration that can actually boot.We debated whether to have ARCH_* options at all on arm64 and we settled for the middle ground - only add them for SoC families, not individual SoCs. As for the kernel configuration that actually boots, we want the arm64 defconfig to include all the supported SoCs and drivers (though longer term I'd like to see more drivers built as modules by default).
Quoted 8 lines
Quoted 3 lines
This is also useful for integrators since they can simply omit all SoC generations that they're not interested in. Having a per-SoC option provides an easy way of doing so.
The integrators could just select a SoC family and trim down unwanted options, I don't think they rely on the kernel defconfig for a final product. If this becomes an issue, I would rather have per-SoC defconfigs than lots of
Kconfigentries.
Quoted 5 lines
I understand the desire to start with a clean plate on a new architecture, but Tegra has worked like this for the past 5 years and it's worked out really well for us. So I'm reluctant to introduce these inconsistencies merely because 64-bit ARM now lives in a different directory.
That's a good time to start cleaning this up, especially since we mandate single image from the beginning.
Quoted 4 lines
Are you concerned about
arch/arm64/Kconfiggrowing wild? If so we could easily move these configuration options outside to something likedrivers/soc/tegra/Kconfig. While at it, we could move existing options fromarch/arm/mach-tegraover to that as well.
I think the whole ARCH_TEGRA_*_SOC approach is wrong. You don't bother introducing Kconfig entries for individual drivers but instead add an obj-*_SOC in various Makefiles under drivers/. If we ever get to a point where we can build (part of) the SoCs as modules (and I'm not talking about kernels shipped with end products but those distro kernel targeting development boards), we have to go back and add such Kconfig entries for specific drivers.
So if you do it properly from the beginning with per-driver Kconfig entry, I no longer see the point of an ARCH_TEGRA_*_SOC option. It may be more convenient for people building end products but they should know better what components are required, defconfig is rarely meant for them.
I'm looking forward to a patch removing ARCH_TEGRA_132_SOC as well (you can keep the 32-bit arm options if you'd like).
Signature · 1 line
Catalin
PATCH 3/6 arm64: tegra: Add Tegra210 support
Quoted 78 lines · Catalin Marinas
Quoted 63 lines · Thierry Reding
Quoted 53 lines · Catalin Marinas
Quoted 39 lines · Thierry Reding
Quoted 23 lines · Catalin Marinas
Quoted 22 lines · Thierry Reding
From: Thierry Reding <[email protected]>
NVIDIA Tegra210 (also known as Tegra X1) has four Cortex-A57 and four Cortex-A53 CPUs. Compared to Tegra124 and Tegra132 it comes with a 256- core Maxwell GPU. It supports processing videos of up to 4K resolutions at 60 fps (H.265, VP9, H.264).
Signed-off-by Thierry Reding <[email protected]>--- arch/arm64/Kconfig | 9 + arch/arm64/boot/dts/nvidia/tegra210.dtsi | 998 +++++++++++++++++++++++++++++++ 2 files changed, 1007 insertions(+) create mode 100644 arch/arm64/boot/dts/nvidia/tegra210.dtsiarch/arm64/Kconfig +0
-0@@ -225,6 +225,15 @@ config ARCH_TEGRA_132_SOC but contains an NVIDIA Denver CPU complex in place of Tegra124's "4+1" Cortex-A15 CPU complex.Quoted 14 lines
arch/arm64/Kconfig config ARCH_TEGRA_132_SOC · line 236
Quoted 9 lines
arch/arm64/Kconfig +9
-0+config ARCH_TEGRA_210_SOC + bool "NVIDIA Tegra210 SoC" + depends on ARCH_TEGRA + select PINCTRL_TEGRA210 + select USB_ULPI if USB_PHY + select USB_ULPI_VIEWPORT if USB_PHY + help + Enable support for the NVIDIA Tegra210 SoC. +The previous
ARCH_TEGRA_132_SOCescaped me. Do we need all these ARCH_TEGRA_*_SOC entries? Can we not have per-driverKconfigoptions? For example,ARCH_TEGRA_132_SOCseems to be only used indrivers/clk/tegra, a specificKconfigentry in there would suffice.Quoted 6 lines
There are actually a couple of other places where this will be used in subsequent patches (e.g. memory controller driver). The idea behind having these is that each one of them is used to enable the essentials out of the box, so that people don't have to go and enable a bunch of driver-specific
Kconfigoptions just to get a kernel configuration that can actually boot.We debated whether to have ARCH_* options at all on arm64 and we settled for the middle ground - only add them for SoC families, not individual SoCs. As for the kernel configuration that actually boots, we want the arm64 defconfig to include all the supported SoCs and drivers (though longer term I'd like to see more drivers built as modules by default).
Quoted 8 lines
Quoted 3 lines
This is also useful for integrators since they can simply omit all SoC generations that they're not interested in. Having a per-SoC option provides an easy way of doing so.
The integrators could just select a SoC family and trim down unwanted options, I don't think they rely on the kernel defconfig for a final product. If this becomes an issue, I would rather have per-SoC defconfigs than lots of
Kconfigentries.Quoted 5 lines
I understand the desire to start with a clean plate on a new architecture, but Tegra has worked like this for the past 5 years and it's worked out really well for us. So I'm reluctant to introduce these inconsistencies merely because 64-bit ARM now lives in a different directory.
That's a good time to start cleaning this up, especially since we mandate single image from the beginning.
Quoted 4 lines
Are you concerned about
arch/arm64/Kconfiggrowing wild? If so we could easily move these configuration options outside to something likedrivers/soc/tegra/Kconfig. While at it, we could move existing options fromarch/arm/mach-tegraover to that as well.
Quoted 7 lines
I think the whole ARCH_TEGRA_*_SOC approach is wrong. You don't bother introducing
Kconfigentries for individual drivers but instead add an obj-*_SOC in various Makefiles underdrivers/. If we ever get to a point where we can build (part of) the SoCs as modules (and I'm not talking about kernels shipped with end products but those distro kernel targeting development boards), we have to go back and add suchKconfigentries for specific drivers.
We can cross that bridge when we get to it. Currently we only use them in the fashion you describe for essential drivers that can't be built as modules. If that ever changes we can easily add the Kconfig entry. This isn't as much churn as you make it out to be, after all if the Kconfig entry already existed we'd still have to change it from bool to tristate to make them build as modules.
Another situation in which we use these Kconfig symbols is for drivers that have an own Kconfig entry but that support more than one SoC generation so that we automatically strip support for SoCs for which support isn't selected. This is especially useful to avoid building code that will only ever work on 32-bit Tegra on 64-bit builds.
Quoted 4 lines
So if you do it properly from the beginning with per-driver
Kconfigentry, I no longer see the point of an ARCH_TEGRA_*_SOC option. It may be more convenient for people building end products but they should know better what components are required, defconfig is rarely meant for them.
Your proposal also means that we'll have to go and add separate Kconfig entries for each SoC generation that a driver supports so that the SoC specific bits can be disabled.
So in order to get rid of one per-SoC Kconfig entry you'd prefer us to add per-SoC options per driver? Don't you think that's going to make things worse rather than improve them?
There are currently three drivers (off the top of my head) where we do this and each of them supports five existing generations plus the new Tegra210. So rather than having six symbols to select SoC generation support we'd be needing 18, and that's only counting existing drivers.
Quoted 2 lines
I'm looking forward to a patch removing
ARCH_TEGRA_132_SOCas well (you can keep the 32-bit arm options if you'd like).
Given the above, will you reconsider? I already proposed that we move these under drivers/soc/tegra (though I'd like to hear Arnd's opinion on that first), that way you wouldn't have to concern yourself with them.
Thierry
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Catalin Marinas
maintainerPATCH 3/6 arm64: tegra: Add Tegra210 support
Quoted 10 lines · Thierry Reding
Quoted 4 lines · Catalin Marinas
So if you do it properly from the beginning with per-driver
Kconfigentry, I no longer see the point of an ARCH_TEGRA_*_SOC option. It may be more convenient for people building end products but they should know better what components are required, defconfig is rarely meant for them.Your proposal also means that we'll have to go and add separate
Kconfigentries for each SoC generation that a driver supports so that the SoC specific bits can be disabled.
Quoted 8 lines
So in order to get rid of one per-SoC
Kconfigentry you'd prefer us to add per-SoC options per driver? Don't you think that's going to make things worse rather than improve them?There are currently three drivers (off the top of my head) where we do this and each of them supports five existing generations plus the new Tegra210. So rather than having six symbols to select SoC generation support we'd be needing 18, and that's only counting existing drivers.
That's not what I meant. For example, you have a clk-tegra124.c file built for two SoCs already and there may be more coming. Instead of multiple obj-y of the same file, just add the entry below to drivers/clk/tegra/Kconfig:
config CLK_TEGRA124
bool "NVIDIA Tegra 124 clock" depends on ARCH_TEGRA_124_SOC || (ARM64 && ARCH_TEGRA) default y help Used on Tegra 124, 132 etc. ...
Note that I preserved the 124_SOC dependency for the 32-bit arm case. But for arm64, just make it dependent on ARCH_TEGRA.
Once done, the Makefile only needs a single entry:
obj-$(CONFIG_TEGRA124) += clk-tegra124.o
Signature · 1 line
Catalin
PATCH 3/6 arm64: tegra: Add Tegra210 support
In reply to Catalin MarinasQuoted 78 lines · Catalin Marinas
Quoted 63 lines · Thierry Reding
Quoted 53 lines · Catalin Marinas
Quoted 39 lines · Thierry Reding
Quoted 23 lines · Catalin Marinas
Quoted 22 lines · Thierry Reding
From: Thierry Reding <[email protected]>
NVIDIA Tegra210 (also known as Tegra X1) has four Cortex-A57 and four Cortex-A53 CPUs. Compared to Tegra124 and Tegra132 it comes with a 256- core Maxwell GPU. It supports processing videos of up to 4K resolutions at 60 fps (H.265, VP9, H.264).
Signed-off-by Thierry Reding <[email protected]>--- arch/arm64/Kconfig | 9 + arch/arm64/boot/dts/nvidia/tegra210.dtsi | 998 +++++++++++++++++++++++++++++++ 2 files changed, 1007 insertions(+)create mode 100644
arch/arm64/boot/dts/nvidia/tegra210.dtsiarch/arm64/Kconfig +0
-0@@ -225,6 +225,15 @@ config ARCH_TEGRA_132_SOC but contains an NVIDIA Denver CPU complex in place of Tegra124's "4+1" Cortex-A15 CPU complex.Quoted 14 lines
arch/arm64/Kconfig config ARCH_TEGRA_132_SOC · line 236
Quoted 9 lines
arch/arm64/Kconfig +9
-0+config ARCH_TEGRA_210_SOC + bool "NVIDIA Tegra210 SoC" + depends on ARCH_TEGRA + select PINCTRL_TEGRA210 + select USB_ULPI if USB_PHY + select USB_ULPI_VIEWPORT if USB_PHY + help + Enable support for the NVIDIA Tegra210 SoC. +The previous
ARCH_TEGRA_132_SOCescaped me. Do we need all these ARCH_TEGRA_*_SOC entries? Can we not have per-driverKconfigoptions? For example,ARCH_TEGRA_132_SOCseems to be only used indrivers/clk/tegra, a specificKconfigentry in there would suffice.Quoted 6 lines
There are actually a couple of other places where this will be used in subsequent patches (e.g. memory controller driver). The idea behind having these is that each one of them is used to enable the essentials out of the box, so that people don't have to go and enable a bunch of driver-specific
Kconfigoptions just to get a kernel configuration that can actually boot.We debated whether to have ARCH_* options at all on arm64 and we settled for the middle ground - only add them for SoC families, not individual SoCs. As for the kernel configuration that actually boots, we want the arm64 defconfig to include all the supported SoCs and drivers (though longer term I'd like to see more drivers built as modules by default).
Quoted 8 lines
Quoted 3 lines
This is also useful for integrators since they can simply omit all SoC generations that they're not interested in. Having a per-SoC option provides an easy way of doing so.
The integrators could just select a SoC family and trim down unwanted options, I don't think they rely on the kernel defconfig for a final product. If this becomes an issue, I would rather have per-SoC defconfigs than lots of
Kconfigentries.Quoted 5 lines
I understand the desire to start with a clean plate on a new architecture, but Tegra has worked like this for the past 5 years and it's worked out really well for us. So I'm reluctant to introduce these inconsistencies merely because 64-bit ARM now lives in a different directory.
That's a good time to start cleaning this up, especially since we mandate single image from the beginning.
Quoted 4 lines
Are you concerned about
arch/arm64/Kconfiggrowing wild? If so we could easily move these configuration options outside to something likedrivers/soc/tegra/Kconfig. While at it, we could move existing options fromarch/arm/mach-tegraover to that as well.
Quoted 7 lines
I think the whole ARCH_TEGRA_*_SOC approach is wrong. You don't bother introducing
Kconfigentries for individual drivers but instead add an obj-*_SOC in various Makefiles underdrivers/. If we ever get to a point where we can build (part of) the SoCs as modules (and I'm not talking about kernels shipped with end products but those distro kernel targeting development boards), we have to go back and add suchKconfigentries for specific drivers.
Just as an aside, long long ago I tried to remove the ARCH_TEGRA_* usage from anywhere outside arch/arm/mach-tegra, but was shot down because that would not allow the driver Kconfig files to only show the drivers that were relevant for the particular Tegra SoCs we had enabled. It's really frustrating to have to deal with the situation of different people pushing in completely the opposite directions on this kind of topic.
PATCH 4/6 arm64: tegra: Add NVIDIA P2530 compute module support
In reply to Thierry RedingFrom: Thierry Reding <[email protected]>
The NVIDIA P2530 is a compute module used in several reference designs. It features a Tegra210 SoC, 4 GiB of LPDDR4 RAM, 16 GiB eMMC and various other essentials. It is typically connected to some base board that provides the connectors needed to hook it up to the outside world.
--- arch/arm64/boot/dts/nvidia/tegra210-p2530-e03.dtsi | 285 +++++++++++++++++++++ 1 file changed, 285 insertions(+) create mode 100644 arch/arm64/boot/dts/nvidia/tegra210-p2530-e03.dtsi
arch/arm64/boot/dts/nvidia/tegra210-p2530-e03.dtsi new file +285 -0
@@ -0,0 +1,285 @@ +#include "tegra210.dtsi" + +/ { + model = "NVIDIA Tegra210 P2530 main board"; + compatible = "nvidia,p2530-e03", "nvidia,tegra210"; + + aliases { + rtc0 = "/i2c at 0,7000d000/pmic at 3c"; + rtc1 = "/rtc at 0,7000e000"; + serial0 = &uarta; + }; + + memory { + reg = <0x0 0x80000000 0x0 0xc0000000>; + }; + + /* debug port */ + serial at 0,70006000 { + status = "okay"; + }; + + i2c at 0,7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: pmic at 3c { + compatible = "maxim,max77620"; + reg = <0x3c>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + + #interrupt-cells = <2>; + interrupt-controller; + + #gpio-cells = <2>; + gpio-controller; + + maxim,enable-clock32k-out; + + maxim,system-pmic-power-off; + + maxim,hot-die-threshold-temp = <110000>; + #thermal-sensor-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&max77620_default>; + + gpio-init-names = "default"; + gpio-init-0 = <&max77620_gpio_default>; + + max77620_default: pinmux at 0 { + pin_gpio0 { + pins = "gpio0"; + function = "gpio"; + }; + + pin_gpio1 { + pins = "gpio1"; + function = "fps-out"; + drive-push-pull = <1>; + maxim,fps-source = <0>; + maxim,fps-power-up-period = <7>; + maxim,fps-power-down-period = <0>; + }; + + pin_gpio2 { + pins = "gpio2", "gpio3"; + function = "fps-out"; + drive-open-drain = <1>; + maxim,fps-source = <0>; + }; + + pin_gpio4 { + pins = "gpio4"; + function = "32k-out1"; + }; + + pin_gpio5_6_7 { + pins = "gpio5", "gpio6", "gpio7"; + function = "gpio"; + drive-push-pull = <1>; + }; + }; + + max77620_gpio_default: gpio_default { + gpio-output-high = <2>; + }; + + watchdog { + maxim,wdt-timeout = <16>; + maxim,wdt-clear-time = <13>; + status = "disabled"; + dt-override-status-odm-data = <0x00020000 0x00020000>; + }; + + fps { + #address-cells = <1>; + #size-cells = <0>; + fps at 0 { + reg = <0>; + maxim,fps-time-period = <2560>; + maxim,fps-enable-input = <0>; + }; + + fps at 1 { + reg = <1>; + maxim,fps-time-period = <2560>; + maxim,fps-enable-input = <1>; + maxim,enable-sleep; + }; + + fps at 2 { + reg = <2>; + maxim,fps-enable-input = <0>; + }; + }; + + backup-battery { + maxim,backup-battery-charging-current = <100>; + maxim,backup-battery-charging-voltage = <3000000>; + maxim,backup-battery-output-resister = <100>; + }; + + regulators { + in-ldo0-1-supply = <&max77620_sd2>; + in-ldo7-8-supply = <&max77620_sd2>; + + max77620_sd0: sd0 { + regulator-name = "VDD_SOC"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + maxim,fps-source = <1>; + regulator-init-mode = <2>; + }; + + max77620_sd1: sd1 { + regulator-name = "VDD_DDR_1V1_PMIC"; + regulator-always-on; + regulator-boot-on; + regulator-init-mode = <2>; + maxim,fps-source = <0>; + }; + + max77620_sd2: sd2 { + regulator-name = "VDD_PRE_REG_1V35"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + maxim,fps-source = <1>; + }; + + vdd_1v8: sd3 { + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + maxim,fps-source = <0>; + regulator-init-mode = <2>; + }; + + vdd_sys_1v2: ldo0 { + regulator-name = "AVDD_SYS_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + maxim,fps-source = <3>; + }; + + vdd_pex_1v05: ldo1 { + regulator-name = "VDD_PEX_1V05"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + maxim,fps-source = <3>; + }; + + vddio_sdmmc: ldo2 { + regulator-name = "VDDIO_SDMMC"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + maxim,fps-source = <3>; + }; + + max77620_ldo3: ldo3 { + regulator-name = "VDD_CAM_HV"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + maxim,fps-source = <3>; + }; + + max77620_ldo4: ldo4 { + regulator-name = "VDD_RTC"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + maxim,fps-source = <0>; + }; + + max77620_ldo5: ldo5 { + regulator-name = "VDD_TS_HV"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + maxim,fps-source = <3>; + }; + + max77620_ldo6: ldo6 { + regulator-name = "VDD_TS_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + maxim,fps-source = <0>; + maxim,fps-power-up-period = <7>; + maxim,fps-power-down-period = <0>; + }; + + avdd_1v05_pll: ldo7 { + regulator-name = "AVDD_1V05_PLL"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + regulator-boot-on; + maxim,fps-source = <1>; + }; + + avdd_1v05: ldo8 { + regulator-name = "AVDD_SATA_HDMI_DP_1V05"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + maxim,fps-source = <3>; + }; + }; + }; + }; + + pmc at 0,7000e400 { + nvidia,invert-interrupt; + }; + + /* eMMC */ + sdhci at 0,700b0600 { + status = "okay"; + bus-width = <8>; + non-removable; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock at 0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + cpus { + cpu at 0 { + enable-method = "psci"; + }; + + cpu at 1 { + enable-method = "psci"; + }; + + cpu at 2 { + enable-method = "psci"; + }; + + cpu at 3 { + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + status = "disabled"; + method = "smc"; + }; +};
Signature · 1 line
2.3.5
PATCH 5/6 arm64: tegra: Add NVIDIA P2595 base board support
In reply to Thierry RedingFrom: Thierry Reding <[email protected]>
The NVIDIA P2595 base board is used in several reference designs and provides the connectors to connect the P2530 compute module to the outside world. It features a USB 3.0 network adapter, a USB 3.0 port, an HDMI port, a SATA port, an audio codec, a microSD card slot and a display connector, among others.
--- arch/arm64/boot/dts/nvidia/tegra210-p2595-a02.dtsi | 1506 ++++++++++++++++++++ 1 file changed, 1506 insertions(+) create mode 100644 arch/arm64/boot/dts/nvidia/tegra210-p2595-a02.dtsi
arch/arm64/boot/dts/nvidia/tegra210-p2595-a02.dtsi new file +1506 -0
@@ -0,0 +1,1506 @@ +/ { + model = "NVIDIA Tegra210 P2595 I/O board (A02)"; + compatible = "nvidia,p2595-a02", "nvidia,tegra210"; + + aliases { + rtc0 = "/i2c at 0,7000d000/pmic at 3c"; + rtc1 = "/rtc at 0,7000e000"; + serial0 = &uarta; + }; + + memory { + reg = <0x0 0x80000000 0x0 0xc0000000>; + }; + + pcie-controller at 0,01003000 { + status = "disabled"; + + avdd-pll-uerefe-supply = <&avdd_1v05_pll>; + hvddio-pex-supply = <&vdd_1v8>; + dvddio-pex-supply = <&vdd_pex_1v05>; + dvdd-pex-pll-supply = <&vdd_pex_1v05>; + hvdd-pex-pll-e-supply = <&vdd_1v8>; + vddio-pex-ctl-supply = <&vdd_1v8>; + + pci at 1,0 { + status = "okay"; + }; + + pci at 2,0 { + status = "okay"; + }; + }; + + host1x at 0,50000000 { + dpaux at 0,54040000 { + status = "okay"; + }; + + sor at 0,54580000 { + status = "okay"; + + avdd-io-supply = <&avdd_1v05>; + vdd-pll-supply = <&vdd_1v8>; + hdmi-supply = <&vdd_hdmi>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1) + GPIO_ACTIVE_LOW>; + }; + }; + + pinmux: pinmux at 0,70000868 { + pinctrl-names = "boot"; + pinctrl-0 = <&state_boot>; + + state_boot: pinmux { + pex_l0_rst_n_pa0 { + nvidia,pins = "pex_l0_rst_n_pa0"; + nvidia,function = "pe0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + nvidia,io-hv = <TEGRA_PIN_ENABLE>; + }; + pex_l0_clkreq_n_pa1 { + nvidia,pins = "pex_l0_clkreq_n_pa1"; + nvidia,function = "pe0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + nvidia,io-hv = <TEGRA_PIN_ENABLE>; + }; + pex_wake_n_pa2 { + nvidia,pins = "pex_wake_n_pa2"; + nvidia,function = "pe"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + nvidia,io-hv = <TEGRA_PIN_ENABLE>; + }; + pex_l1_rst_n_pa3 { + nvidia,pins = "pex_l1_rst_n_pa3"; + nvidia,function = "pe1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + nvidia,io-hv = <TEGRA_PIN_ENABLE>; + }; + pex_l1_clkreq_n_pa4 { + nvidia,pins = "pex_l1_clkreq_n_pa4"; + nvidia,function = "pe1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + nvidia,io-hv = <TEGRA_PIN_ENABLE>; + }; + sata_led_active_pa5 { + nvidia,pins = "sata_led_active_pa5"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + pa6 { + nvidia,pins = "pa6"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + dap1_fs_pb0 { + nvidia,pins = "dap1_fs_pb0"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + dap1_din_pb1 { + nvidia,pins = "dap1_din_pb1"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + dap1_dout_pb2 { + nvidia,pins = "dap1_dout_pb2"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + dap1_sclk_pb3 { + nvidia,pins = "dap1_sclk_pb3"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + spi2_mosi_pb4 { + nvidia,pins = "spi2_mosi_pb4"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + spi2_miso_pb5 { + nvidia,pins = "spi2_miso_pb5"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + spi2_sck_pb6 { + nvidia,pins = "spi2_sck_pb6"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + spi2_cs0_pb7 { + nvidia,pins = "spi2_cs0_pb7"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + spi1_mosi_pc0 { + nvidia,pins = "spi1_mosi_pc0"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + spi1_miso_pc1 { + nvidia,pins = "spi1_miso_pc1"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + spi1_sck_pc2 { + nvidia,pins = "spi1_sck_pc2"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + spi1_cs0_pc3 { + nvidia,pins = "spi1_cs0_pc3"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + spi1_cs1_pc4 { + nvidia,pins = "spi1_cs1_pc4"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + spi4_sck_pc5 { + nvidia,pins = "spi4_sck_pc5"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + spi4_cs0_pc6 { + nvidia,pins = "spi4_cs0_pc6"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + spi4_mosi_pc7 { + nvidia,pins = "spi4_mosi_pc7"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + spi4_miso_pd0 { + nvidia,pins = "spi4_miso_pd0"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + uart3_tx_pd1 { + nvidia,pins = "uart3_tx_pd1"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + uart3_rx_pd2 { + nvidia,pins = "uart3_rx_pd2"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + uart3_rts_pd3 { + nvidia,pins = "uart3_rts_pd3"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + uart3_cts_pd4 { + nvidia,pins = "uart3_cts_pd4"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + dmic1_clk_pe0 { + nvidia,pins = "dmic1_clk_pe0"; + nvidia,function = "dmic1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + dmic1_dat_pe1 { + nvidia,pins = "dmic1_dat_pe1"; + nvidia,function = "dmic1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + dmic2_clk_pe2 { + nvidia,pins = "dmic2_clk_pe2"; + nvidia,function = "dmic2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + dmic2_dat_pe3 { + nvidia,pins = "dmic2_dat_pe3"; + nvidia,function = "dmic2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + dmic3_clk_pe4 { + nvidia,pins = "dmic3_clk_pe4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + dmic3_dat_pe5 { + nvidia,pins = "dmic3_dat_pe5"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + pe6 { + nvidia,pins = "pe6"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + pe7 { + nvidia,pins = "pe7"; + nvidia,function = "pwm3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + gen3_i2c_scl_pf0 { + nvidia,pins = "gen3_i2c_scl_pf0"; + nvidia,function = "i2c3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + nvidia,io-hv = <TEGRA_PIN_DISABLE>; + }; + gen3_i2c_sda_pf1 { + nvidia,pins = "gen3_i2c_sda_pf1"; + nvidia,function = "i2c3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + nvidia,io-hv = <TEGRA_PIN_DISABLE>; + }; + uart2_tx_pg0 { + nvidia,pins = "uart2_tx_pg0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + uart2_rx_pg1 { + nvidia,pins = "uart2_rx_pg1"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + uart2_rts_pg2 { + nvidia,pins = "uart2_rts_pg2"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + uart2_cts_pg3 { + nvidia,pins = "uart2_cts_pg3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + wifi_en_ph0 { + nvidia,pins = "wifi_en_ph0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + wifi_rst_ph1 { + nvidia,pins = "wifi_rst_ph1"; + nvidia,function = "rsvd0"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + wifi_wake_ap_ph2 { + nvidia,pins = "wifi_wake_ap_ph2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + ap_wake_bt_ph3 { + nvidia,pins = "ap_wake_bt_ph3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + bt_rst_ph4 { + nvidia,pins = "bt_rst_ph4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + bt_wake_ap_ph5 { + nvidia,pins = "bt_wake_ap_ph5"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + ph6 { + nvidia,pins = "ph6"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + ap_wake_nfc_ph7 { + nvidia,pins = "ap_wake_nfc_ph7"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + nfc_en_pi0 { + nvidia,pins = "nfc_en_pi0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + nfc_int_pi1 { + nvidia,pins = "nfc_int_pi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + gps_en_pi2 { + nvidia,pins = "gps_en_pi2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + gps_rst_pi3 { + nvidia,pins = "gps_rst_pi3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + uart4_tx_pi4 { + nvidia,pins = "uart4_tx_pi4"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + uart4_rx_pi5 { + nvidia,pins = "uart4_rx_pi5"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + uart4_rts_pi6 { + nvidia,pins = "uart4_rts_pi6"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + uart4_cts_pi7 { + nvidia,pins = "uart4_cts_pi7"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + gen1_i2c_sda_pj0 { + nvidia,pins = "gen1_i2c_sda_pj0"; + nvidia,function = "i2c1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + nvidia,io-hv = <TEGRA_PIN_DISABLE>; + }; + gen1_i2c_scl_pj1 { + nvidia,pins = "gen1_i2c_scl_pj1"; + nvidia,function = "i2c1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + nvidia,io-hv = <TEGRA_PIN_DISABLE>; + }; + gen2_i2c_scl_pj2 { + nvidia,pins = "gen2_i2c_scl_pj2"; + nvidia,function = "i2c2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + nvidia,io-hv = <TEGRA_PIN_ENABLE>; + }; + gen2_i2c_sda_pj3 { + nvidia,pins = "gen2_i2c_sda_pj3"; + nvidia,function = "i2c2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + nvidia,io-hv = <TEGRA_PIN_ENABLE>; + }; + dap4_fs_pj4 { + nvidia,pins = "dap4_fs_pj4"; + nvidia,function = "i2s4b"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + dap4_din_pj5 { + nvidia,pins = "dap4_din_pj5"; + nvidia,function = "i2s4b"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + dap4_dout_pj6 { + nvidia,pins = "dap4_dout_pj6"; + nvidia,function = "i2s4b"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + dap4_sclk_pj7 { + nvidia,pins = "dap4_sclk_pj7"; + nvidia,function = "i2s4b"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + pk0 { + nvidia,pins = "pk0"; + nvidia,function = "i2s5b"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + pk1 { + nvidia,pins = "pk1"; + nvidia,function = "i2s5b"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + pk2 { + nvidia,pins = "pk2"; + nvidia,function = "i2s5b"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + pk3 { + nvidia,pins = "pk3"; + nvidia,function = "i2s5b"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + pk4 { + nvidia,pins = "pk4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + pk5 { + nvidia,pins = "pk5"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + pk6 { + nvidia,pins = "pk6"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + pk7 { + nvidia,pins = "pk7"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + pl0 { + nvidia,pins = "pl0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + pl1 { + nvidia,pins = "pl1"; + nvidia,function = "soc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + sdmmc1_clk_pm0 { + nvidia,pins = "sdmmc1_clk_pm0"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + sdmmc1_cmd_pm1 { + nvidia,pins = "sdmmc1_cmd_pm1"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + sdmmc1_dat3_pm2 { + nvidia,pins = "sdmmc1_dat3_pm2"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + sdmmc1_dat2_pm3 { + nvidia,pins = "sdmmc1_dat2_pm3"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + sdmmc1_dat1_pm4 { + nvidia,pins = "sdmmc1_dat1_pm4"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + sdmmc1_dat0_pm5 { + nvidia,pins = "sdmmc1_dat0_pm5"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + sdmmc3_clk_pp0 { + nvidia,pins = "sdmmc3_clk_pp0"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + sdmmc3_cmd_pp1 { + nvidia,pins = "sdmmc3_cmd_pp1"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + sdmmc3_dat3_pp2 { + nvidia,pins = "sdmmc3_dat3_pp2"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + sdmmc3_dat2_pp3 { + nvidia,pins = "sdmmc3_dat2_pp3"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + sdmmc3_dat1_pp4 { + nvidia,pins = "sdmmc3_dat1_pp4"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + sdmmc3_dat0_pp5 { + nvidia,pins = "sdmmc3_dat0_pp5"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + cam1_mclk_ps0 { + nvidia,pins = "cam1_mclk_ps0"; + nvidia,function = "extperiph3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + cam2_mclk_ps1 { + nvidia,pins = "cam2_mclk_ps1"; + nvidia,function = "extperiph3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + cam_i2c_scl_ps2 { + nvidia,pins = "cam_i2c_scl_ps2"; + nvidia,function = "i2cvi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + nvidia,io-hv = <TEGRA_PIN_DISABLE>; + }; + cam_i2c_sda_ps3 { + nvidia,pins = "cam_i2c_sda_ps3"; + nvidia,function = "i2cvi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + nvidia,io-hv = <TEGRA_PIN_DISABLE>; + }; + cam_rst_ps4 { + nvidia,pins = "cam_rst_ps4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + cam_af_en_ps5 { + nvidia,pins = "cam_af_en_ps5"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + cam_flash_en_ps6 { + nvidia,pins = "cam_flash_en_ps6"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + cam1_pwdn_ps7 { + nvidia,pins = "cam1_pwdn_ps7"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + cam2_pwdn_pt0 { + nvidia,pins = "cam2_pwdn_pt0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + cam1_strobe_pt1 { + nvidia,pins = "cam1_strobe_pt1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + uart1_tx_pu0 { + nvidia,pins = "uart1_tx_pu0"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + uart1_rx_pu1 { + nvidia,pins = "uart1_rx_pu1"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + uart1_rts_pu2 { + nvidia,pins = "uart1_rts_pu2"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + uart1_cts_pu3 { + nvidia,pins = "uart1_cts_pu3"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + lcd_bl_pwm_pv0 { + nvidia,pins = "lcd_bl_pwm_pv0"; + nvidia,function = "pwm0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + lcd_bl_en_pv1 { + nvidia,pins = "lcd_bl_en_pv1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + lcd_rst_pv2 { + nvidia,pins = "lcd_rst_pv2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + lcd_gpio1_pv3 { + nvidia,pins = "lcd_gpio1_pv3"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + lcd_gpio2_pv4 { + nvidia,pins = "lcd_gpio2_pv4"; + nvidia,function = "pwm1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + ap_ready_pv5 { + nvidia,pins = "ap_ready_pv5"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + touch_rst_pv6 { + nvidia,pins = "touch_rst_pv6"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + touch_clk_pv7 { + nvidia,pins = "touch_clk_pv7"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + modem_wake_ap_px0 { + nvidia,pins = "modem_wake_ap_px0"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + touch_int_px1 { + nvidia,pins = "touch_int_px1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + motion_int_px2 { + nvidia,pins = "motion_int_px2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + als_prox_int_px3 { + nvidia,pins = "als_prox_int_px3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + temp_alert_px4 { + nvidia,pins = "temp_alert_px4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + button_power_on_px5 { + nvidia,pins = "button_power_on_px5"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + button_vol_up_px6 { + nvidia,pins = "button_vol_up_px6"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + button_vol_down_px7 { + nvidia,pins = "button_vol_down_px7"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + button_slide_sw_py0 { + nvidia,pins = "button_slide_sw_py0"; + nvidia,function = "rsvd0"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + button_home_py1 { + nvidia,pins = "button_home_py1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + lcd_te_py2 { + nvidia,pins = "lcd_te_py2"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + pwr_i2c_scl_py3 { + nvidia,pins = "pwr_i2c_scl_py3"; + nvidia,function = "i2cpmu"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + nvidia,io-hv = <TEGRA_PIN_DISABLE>; + }; + pwr_i2c_sda_py4 { + nvidia,pins = "pwr_i2c_sda_py4"; + nvidia,function = "i2cpmu"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + nvidia,io-hv = <TEGRA_PIN_DISABLE>; + }; + clk_32k_out_py5 { + nvidia,pins = "clk_32k_out_py5"; + nvidia,function = "soc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + pz0 { + nvidia,pins = "pz0"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + pz1 { + nvidia,pins = "pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + pz2 { + nvidia,pins = "pz2"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + pz3 { + nvidia,pins = "pz3"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + pz4 { + nvidia,pins = "pz4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + pz5 { + nvidia,pins = "pz5"; + nvidia,function = "soc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + dap2_fs_paa0 { + nvidia,pins = "dap2_fs_paa0"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + dap2_sclk_paa1 { + nvidia,pins = "dap2_sclk_paa1"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + dap2_din_paa2 { + nvidia,pins = "dap2_din_paa2"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + dap2_dout_paa3 { + nvidia,pins = "dap2_dout_paa3"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + aud_mclk_pbb0 { + nvidia,pins = "aud_mclk_pbb0"; + nvidia,function = "aud"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + dvfs_pwm_pbb1 { + nvidia,pins = "dvfs_pwm_pbb1"; + nvidia,function = "cldvfs"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + dvfs_clk_pbb2 { + nvidia,pins = "dvfs_clk_pbb2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + gpio_x1_aud_pbb3 { + nvidia,pins = "gpio_x1_aud_pbb3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + gpio_x3_aud_pbb4 { + nvidia,pins = "gpio_x3_aud_pbb4"; + nvidia,function = "rsvd0"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + hdmi_cec_pcc0 { + nvidia,pins = "hdmi_cec_pcc0"; + nvidia,function = "cec"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + nvidia,io-hv = <TEGRA_PIN_ENABLE>; + }; + hdmi_int_dp_hpd_pcc1 { + nvidia,pins = "hdmi_int_dp_hpd_pcc1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + nvidia,io-hv = <TEGRA_PIN_DISABLE>; + }; + spdif_out_pcc2 { + nvidia,pins = "spdif_out_pcc2"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + spdif_in_pcc3 { + nvidia,pins = "spdif_in_pcc3"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + usb_vbus_en0_pcc4 { + nvidia,pins = "usb_vbus_en0_pcc4"; + nvidia,function = "usb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + nvidia,io-hv = <TEGRA_PIN_ENABLE>; + }; + usb_vbus_en1_pcc5 { + nvidia,pins = "usb_vbus_en1_pcc5"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + nvidia,io-hv = <TEGRA_PIN_DISABLE>; + }; + dp_hpd0_pcc6 { + nvidia,pins = "dp_hpd0_pcc6"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + pcc7 { + nvidia,pins = "pcc7"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + nvidia,io-hv = <TEGRA_PIN_DISABLE>; + }; + spi2_cs1_pdd0 { + nvidia,pins = "spi2_cs1_pdd0"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + qspi_sck_pee0 { + nvidia,pins = "qspi_sck_pee0"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + qspi_cs_n_pee1 { + nvidia,pins = "qspi_cs_n_pee1"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + qspi_io0_pee2 { + nvidia,pins = "qspi_io0_pee2"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + qspi_io1_pee3 { + nvidia,pins = "qspi_io1_pee3"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + qspi_io2_pee4 { + nvidia,pins = "qspi_io2_pee4"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + qspi_io3_pee5 { + nvidia,pins = "qspi_io3_pee5"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + core_pwr_req { + nvidia,pins = "core_pwr_req"; + nvidia,function = "core"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + cpu_pwr_req { + nvidia,pins = "cpu_pwr_req"; + nvidia,function = "cpu"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + pwr_int_n { + nvidia,pins = "pwr_int_n"; + nvidia,function = "pmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + clk_32k_in { + nvidia,pins = "clk_32k_in"; + nvidia,function = "clk"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + jtag_rtck { + nvidia,pins = "jtag_rtck"; + nvidia,function = "jtag"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + clk_req { + nvidia,pins = "clk_req"; + nvidia,function = "sys"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + shutdown { + nvidia,pins = "shutdown"; + nvidia,function = "shutdown"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + }; + }; + + pwm at 0,7000a000 { + status = "okay"; + }; + + /* HDMI DDC */ + hdmi_ddc: i2c at 0,7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + hda at 0,70030000 { + status = "okay"; + }; + + usb at 0,70090000 { + status = "disabled"; + }; + + padctl at 0,7009f000 { + status = "disabled"; + + pinctrl-0 = <&padctl_default>; + pinctrl-names = "default"; + + phys { + pcie-0 { + status = "okay"; + }; + }; + + padctl_default: pinmux { + usb3 { + nvidia,lanes = "pcie-5", "pcie-6"; + nvidia,function = "usb3"; + nvidia,iddq = <0>; + }; + + pcie-x1 { + nvidia,lanes = "pcie-0"; + nvidia,function = "pciex1"; + nvidia,iddq = <0>; + }; + + pcie-x4 { + nvidia,lanes = "pcie-1", "pcie-2", "pcie-3", + "pcie-4"; + nvidia,function = "pciex4"; + nvidia,iddq = <0>; + }; + + sata { + nvidia,lanes = "sata-0"; + nvidia,function = "sata"; + nvidia,iddq = <0>; + }; + }; + }; + + /* microSD */ + sdhci at 0,700b0000 { + status = "okay"; + bus-width = <4>; + no-1-8-v; + + cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; + + vqmmc-supply = <&vddio_sdmmc>; + vmmc-supply = <&vdd_3v3_sd>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + power-supply = <&vdd_3v3_bl>; + pwms = <&pwm 0 40161>; + + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_sys_mux: regulator at 0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "VDD_SYS_MUX"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_5v0_sys: regulator at 1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "VDD_5V0_SYS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_sys_mux>; + }; + + vdd_3v3_sys: regulator at 2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "VDD_3V3_SYS"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_sys_mux>; + }; + + vdd_3v3_sd: regulator at 3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "VDD_3V3_SD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_dsi_csi: regulator at 4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "AVDD_DSI_CSI_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_sys_1v2>; + }; + + vdd_3v3_bl: regulator at 5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "VDD_3V3_BL"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_5v0_io: regulator at 6 { + compatible = "regulator-fixed"; + reg = <6>; + regulator-name = "VDD_5V0_IO_SYS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_3v0_disp: regulator at 7 { + compatible = "regulator-fixed"; + reg = <7>; + regulator-name = "VDD_DISP_3V0_LDO"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + gpio = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_hdmi: regulator at 8 { + compatible = "regulator-fixed"; + reg = <8>; + regulator-name = "VDD_HDMI_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(CC, 7) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + }; +};
Signature · 1 line
2.3.5
PATCH 6/6 arm64: tegra: Add NVIDIA P2371 support
In reply to Thierry RedingFrom: Thierry Reding <[email protected]>
The NVIDIA P2371 is an internal reference design that uses a P2530 compute module hooked up to a a P2595 base board and an optional display module for a 1200x1920 MIPI DSI panel.
--- arch/arm64/boot/dts/nvidia/Makefile | 1 + arch/arm64/boot/dts/nvidia/tegra210-p2371-e01.dts | 27 +++++++++++++++++++++++ 2 files changed, 28 insertions(+) create mode 100644 arch/arm64/boot/dts/nvidia/tegra210-p2371-e01.dts
arch/arm64/boot/dts/nvidia/Makefile +1 -0
@@ -1,4 +1,5 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra132-norrin.dtb +dtb-$(CONFIG_ARCH_TEGRA) += tegra210-p2371-e01.dtb always := $(dtb-y) clean-files := *.dtb
arch/arm64/boot/dts/nvidia/tegra210-p2371-e01.dts new file +27 -0
@@ -0,0 +1,27 @@ +/dts-v1/; + +#include "tegra210-p2530-e03.dtsi" +#include "tegra210-p2595-a02.dtsi" + +/ { + model = "NVIDIA Tegra210 P2371 reference board (E.1)"; + compatible = "nvidia,p2371-e01", "nvidia,tegra210"; + + host1x at 0,50000000 { + dsi at 0,54300000 { + status = "okay"; + + avdd-dsi-csi-supply = <&vdd_dsi_csi>; + + panel at 0 { + compatible = "auo,b080uan01"; + reg = <0>; + + enable-gpios = <&gpio TEGRA_GPIO(V, 2) + GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_5v0_io>; + backlight = <&backlight>; + }; + }; + }; +};
Signature · 1 line
2.3.5