drm/msm/dsi: Add DSI PLL driver under common clock framework

PATCH New Hai Li 1 participant 4 messages May 15, 2015

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Hai Li

author

2015-05-15 17:04 UTC #0 lore raw

cover drm/msm/dsi: Add DSI PLL driver under common clock framework

DSI PLL driver can work with common clock framework and provide source of DSI byte clock and pixel clock, as a clock provider.

Hai Li (3):
drm/msm/dsi: Add DSI PLL clock driver support drm/msm/dsi: Enable PLL driver in MSM DSI drm/msm/dsi: Separate PHY to another platform device

 Documentation/devicetree/bindings/drm/msm/dsi.txt |  59 +-
 drivers/gpu/drm/msm/Kconfig                       |   7 +
 drivers/gpu/drm/msm/Makefile                      |   5 +
 drivers/gpu/drm/msm/dsi/dsi.c                     |  43 +-
 drivers/gpu/drm/msm/dsi/dsi.h                     |  61 +-
 drivers/gpu/drm/msm/dsi/dsi_host.c                |  83 ++-
 drivers/gpu/drm/msm/dsi/dsi_manager.c             |  79 ++-
 drivers/gpu/drm/msm/dsi/dsi_phy.c                 | 311 ++++++++++-
 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c             | 164 ++++++
 drivers/gpu/drm/msm/dsi/pll/dsi_pll.h             |  89 +++
 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c        | 652 ++++++++++++++++++++++
 11 files changed, 1448 insertions(+), 105 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c
 create mode 100644 drivers/gpu/drm/msm/dsi/pll/dsi_pll.h
 create mode 100644 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c

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hosted by The Linux Foundation

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Hai Li

author

2015-05-15 17:04 UTC #1 lore raw

PATCH 1/3 drm/msm/dsi: Add DSI PLL clock driver support

DSI byte clock and pixel clocks are sourced from DSI PLL. This change adds the DSI PLL source clock driver under common clock framework.

This change handles DSI 28nm PLL only.

Signed-off-by Hai Li <[email protected]>

Signed-off-by Archit Taneja <[email protected]>

Signed-off-by Stephane Viau <[email protected]>

Signed-off-by Wentao Xu <[email protected]>

---
 drivers/gpu/drm/msm/Kconfig                |   7 +
 drivers/gpu/drm/msm/Makefile               |   5 +
 drivers/gpu/drm/msm/dsi/dsi.h              |   3 +-
 drivers/gpu/drm/msm/dsi/dsi_host.c         |  10 +-
 drivers/gpu/drm/msm/dsi/dsi_phy.c          |   3 +-
 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c      | 164 ++++++++
 drivers/gpu/drm/msm/dsi/pll/dsi_pll.h      |  89 ++++
 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c | 652 +++++++++++++++++++++++++++++
 8 files changed, 926 insertions(+), 7 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c
 create mode 100644 drivers/gpu/drm/msm/dsi/pll/dsi_pll.h
 create mode 100644 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c

drivers/gpu/drm/msm/Kconfig +7 -0

index 0a6f676..08ba8d0 100644
@@ -46,3 +46,10 @@ config DRM_MSM_DSI
 	  Choose this option if you have a need for MIPI DSI connector
 	  support.
 
+config DRM_MSM_DSI_PLL
+	bool "Enable DSI PLL driver in MSM DRM"
+	depends on DRM_MSM_DSI && COMMON_CLK
+	default y
+	help
+	  Choose this option to enable DSI PLL driver which provides DSI
+	  source clocks under common clock framework.

drivers/gpu/drm/msm/Makefile +5 -0

index ab20867..16a81b9 100644
@@ -1,4 +1,5 @@
 ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/msm
+ccflags-$(CONFIG_DRM_MSM_DSI_PLL) += -Idrivers/gpu/drm/msm/dsi
 
 msm-y := \
 	adreno/adreno_device.o \

@@ -50,10 +51,14 @@ msm-y := \
 
 msm-$(CONFIG_DRM_MSM_FBDEV) += msm_fbdev.o
 msm-$(CONFIG_COMMON_CLK) += mdp/mdp4/mdp4_lvds_pll.o
+
 msm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \
 			dsi/dsi_host.o \
 			dsi/dsi_manager.o \
 			dsi/dsi_phy.o \
 			mdp/mdp5/mdp5_cmd_encoder.o
 
+msm-$(CONFIG_DRM_MSM_DSI_PLL) += dsi/pll/dsi_pll.o \
+				dsi/pll/dsi_pll_28nm.o
+
 obj-$(CONFIG_DRM_MSM)	+= msm.o

drivers/gpu/drm/msm/dsi/dsi.h +2 -1

index 10f54d4..321964a 100644
@@ -103,7 +103,8 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi);
 struct msm_dsi_phy;
 enum msm_dsi_phy_type {
 	MSM_DSI_PHY_UNKNOWN,
-	MSM_DSI_PHY_28NM,
+	MSM_DSI_PHY_28NM_HPM,
+	MSM_DSI_PHY_28NM_LP,
 	MSM_DSI_PHY_MAX
 };
 struct msm_dsi_phy *msm_dsi_phy_init(struct platform_device *pdev,

drivers/gpu/drm/msm/dsi/dsi_host.c +5 -5

index 360b765..f7ba890 100644
@@ -64,7 +64,7 @@ static const struct dsi_config dsi_cfgs[] = {
 		.major = MSM_DSI_VER_MAJOR_6G,
 		.minor = MSM_DSI_6G_VER_MINOR_V1_0,
 		.io_offset = DSI_6G_REG_SHIFT,
-		.phy_type = MSM_DSI_PHY_28NM,
+		.phy_type = MSM_DSI_PHY_28NM_HPM,
 		.reg_cfg = {
 			.num = 4,
 			.regs = {

@@ -79,7 +79,7 @@ static const struct dsi_config dsi_cfgs[] = {
 		.major = MSM_DSI_VER_MAJOR_6G,
 		.minor = MSM_DSI_6G_VER_MINOR_V1_1,
 		.io_offset = DSI_6G_REG_SHIFT,
-		.phy_type = MSM_DSI_PHY_28NM,
+		.phy_type = MSM_DSI_PHY_28NM_HPM,
 		.reg_cfg = {
 			.num = 4,
 			.regs = {

@@ -94,7 +94,7 @@ static const struct dsi_config dsi_cfgs[] = {
 		.major = MSM_DSI_VER_MAJOR_6G,
 		.minor = MSM_DSI_6G_VER_MINOR_V1_1_1,
 		.io_offset = DSI_6G_REG_SHIFT,
-		.phy_type = MSM_DSI_PHY_28NM,
+		.phy_type = MSM_DSI_PHY_28NM_HPM,
 		.reg_cfg = {
 			.num = 4,
 			.regs = {

@@ -109,7 +109,7 @@ static const struct dsi_config dsi_cfgs[] = {
 		.major = MSM_DSI_VER_MAJOR_6G,
 		.minor = MSM_DSI_6G_VER_MINOR_V1_2,
 		.io_offset = DSI_6G_REG_SHIFT,
-		.phy_type = MSM_DSI_PHY_28NM,
+		.phy_type = MSM_DSI_PHY_28NM_HPM,
 		.reg_cfg = {
 			.num = 4,
 			.regs = {

@@ -124,7 +124,7 @@ static const struct dsi_config dsi_cfgs[] = {
 		.major = MSM_DSI_VER_MAJOR_6G,
 		.minor = MSM_DSI_6G_VER_MINOR_V1_3_1,
 		.io_offset = DSI_6G_REG_SHIFT,
-		.phy_type = MSM_DSI_PHY_28NM,
+		.phy_type = MSM_DSI_PHY_28NM_LP,
 		.reg_cfg = {
 			.num = 4,
 			.regs = {

drivers/gpu/drm/msm/dsi/dsi_phy.c +2 -1

index f0cea89..fc11474 100644
@@ -311,7 +311,8 @@ struct msm_dsi_phy *msm_dsi_phy_init(struct platform_device *pdev,
 	}
 
 	switch (type) {
-	case MSM_DSI_PHY_28NM:
+	case MSM_DSI_PHY_28NM_HPM:
+	case MSM_DSI_PHY_28NM_LP:
 		dsi_phy_func_init(28nm);
 		break;
 	default:

drivers/gpu/drm/msm/dsi/pll/dsi_pll.c new file +164 -0

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drivers/gpu/drm/msm/dsi/pll/dsi_pll.h new file +89 -0

89 lines not on this page · raw message

drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c new file +652 -0

652 lines not on this page · raw message

Signature · 7 lines

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

_______________________________________________
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Hai Li

author

2015-05-15 17:04 UTC #2 lore raw

PATCH 2/3 drm/msm/dsi: Enable PLL driver in MSM DSI

In reply to Hai Li

This change activates PLL driver for DSI to work with common clock framework.

Signed-off-by Hai Li <[email protected]>

---
 drivers/gpu/drm/msm/dsi/dsi.c         | 14 +++++++
 drivers/gpu/drm/msm/dsi/dsi.h         | 43 ++++++++++++++++---
 drivers/gpu/drm/msm/dsi/dsi_host.c    | 60 ++++++++++++++++++++++----
 drivers/gpu/drm/msm/dsi/dsi_manager.c | 79 +++++++++++++++++++++++++----------
 drivers/gpu/drm/msm/dsi/dsi_phy.c     | 68 ++++++++++++++++++++++++++++++
 5 files changed, 229 insertions(+), 35 deletions(-)

drivers/gpu/drm/msm/dsi/dsi.c +14 -0

index ad50b80..beb26df 100644
@@ -29,6 +29,12 @@ static void dsi_destroy(struct msm_dsi *msm_dsi)
 		return;
 
 	msm_dsi_manager_unregister(msm_dsi);
+
+	if (msm_dsi->phy) {
+		msm_dsi_phy_destroy(msm_dsi->phy);
+		msm_dsi->phy = NULL;
+	}
+
 	if (msm_dsi->host) {
 		msm_dsi_host_destroy(msm_dsi->host);
 		msm_dsi->host = NULL;

@@ -63,6 +69,14 @@ static struct msm_dsi *dsi_init(struct platform_device *pdev)
 	if (ret)
 		goto fail;
 
+	/* Init dsi PHY */
+	msm_dsi->phy = msm_dsi_phy_init(pdev, msm_dsi->phy_type, msm_dsi->id);
+	if (!msm_dsi->phy) {
+		ret = -ENXIO;
+		pr_err("%s: phy init failed\n", __func__);
+		goto fail;
+	}
+
 	/* Register to dsi manager */
 	ret = msm_dsi_manager_register(msm_dsi);
 	if (ret)

drivers/gpu/drm/msm/dsi/dsi.h +37 -6

79 lines not on this page · raw message

drivers/gpu/drm/msm/dsi/dsi_host.c +53 -7

86 lines not on this page · raw message

drivers/gpu/drm/msm/dsi/dsi_manager.c +57 ~~-22~~

101 lines not on this page · raw message

drivers/gpu/drm/msm/dsi/dsi_phy.c +68 -0

104 lines not on this page · raw message

Signature · 2 lines

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

Hai Li

author

2015-05-15 17:04 UTC #3 lore raw

PATCH 3/3 drm/msm/dsi: Separate PHY to another platform device

In reply to Hai Li

There are different types of PHY from one chipset to another, while the DSI host controller is relatively consistent across platforms. Also, the PLL inside PHY is providing the source of DSI byte and pixel clocks, which are used by DSI host controller. Separated devices for clock provider and clock consumer make DSI driver better fit into common clock framework.

Signed-off-by Hai Li <[email protected]>

---
 Documentation/devicetree/bindings/drm/msm/dsi.txt |  59 +++--
 drivers/gpu/drm/msm/dsi/dsi.c                     |  45 +++-
 drivers/gpu/drm/msm/dsi/dsi.h                     |  25 +-
 drivers/gpu/drm/msm/dsi/dsi_host.c                |  25 +-
 drivers/gpu/drm/msm/dsi/dsi_phy.c                 | 266 ++++++++++++++++++----
 5 files changed, 325 insertions(+), 95 deletions(-)

Documentation/devicetree/bindings/drm/msm/dsi.txt +41 ~~-18~~

index b3cf325..2b17281 100644
@@ -1,15 +1,12 @@
 Qualcomm Technologies Inc. adreno/snapdragon DSI output
 
+DSI Controller:
 Required properties:
 - compatible:
   * "qcom,mdss-dsi-ctrl"
-- reg: Physical base address and length of the registers of controller, PLL,
-  PHY and PHY regulator
+- reg: Physical base address and length of the registers of controller
 - reg-names: The names of register regions. The following regions are required:
   * "dsi_ctrl"
-  * "dsi_pll"
-  * "dsi_phy"
-  * "dsi_phy_regulator"
 - qcom,dsi-host-index: The ID of DSI controller hardware instance. This should
   be 0 or 1, since we have 2 DSI controllers at most for now.
 - interrupts: The interrupt signal from the DSI block.

@@ -24,10 +21,10 @@ Required properties:
   * "iface_clk"
   * "mdp_core_clk"
   * "pixel_clk"
-- #clock-cells: The value should be 1.
 - vdd-supply: phandle to vdd regulator device node
 - vddio-supply: phandle to vdd-io regulator device node
 - vdda-supply: phandle to vdda regulator device node
+- qcom,dsi-phy: phandle to DSI PHY device node
 
 Optional properties:
 - panel@0: Node of panel connected to this DSI controller.

@@ -42,22 +39,34 @@ Optional properties:
 - interrupt-parent: phandle to the MDP block if the interrupt signal is routed
   through MDP block
 
+DSI PHY:
+Required properties:
+- compatible: Could be the following
+  * "qcom,dsi-phy-28nm-hpm"
+  * "qcom,dsi-phy-28nm-lp"
+- reg: Physical base address and length of the registers of PLL, PHY and PHY
+  regulator
+- reg-names: The names of register regions. The following regions are required:
+  * "dsi_pll"
+  * "dsi_phy"
+  * "dsi_phy_regulator"
+- qcom,dsi-phy-index: The ID of DSI PHY hardware instance. This should
+  be 0 or 1, since we have 2 DSI PHYs at most for now.
+- power-domains: Should be <&mmcc MDSS_GDSC>.
+- clocks: device clocks
+  See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
+- clock-names: the following clocks are required:
+  * "iface_clk"
+- vddio-supply: phandle to vdd-io regulator device node
+
 Example:
 	mdss_dsi0: qcom,mdss_dsi@fd922800 {
 		compatible = "qcom,mdss-dsi-ctrl";
 		qcom,dsi-host-index = <0>;
 		interrupt-parent = <&mdss_mdp>;
 		interrupts = <4 0>;
-		reg-names =
-			"dsi_ctrl",
-			"dsi_pll",
-			"dsi_phy",
-			"dsi_phy_regulator",
-		reg =	<0xfd922800 0x200>,
-			<0xfd922a00 0xd4>,
-			<0xfd922b00 0x2b0>,
-			<0xfd922d80 0x7b>,
-			<0xfd828000 0x108>;
+		reg-names = "dsi_ctrl";
+		reg = <0xfd922800 0x200>;
 		power-domains = <&mmcc MDSS_GDSC>;
 		clock-names =
 			"bus_clk",

@@ -75,11 +84,12 @@ Example:
 			<&mmcc MDSS_AHB_CLK>,
 			<&mmcc MDSS_MDP_CLK>,
 			<&mmcc MDSS_PCLK0_CLK>;
-		#clock-cells = <1>;
 		vdda-supply = <&pma8084_l2>;
 		vdd-supply = <&pma8084_l22>;
 		vddio-supply = <&pma8084_l12>;
 
+		qcom,dsi-phy = <&mdss_dsi_phy0>;
+
 		qcom,dual-panel-mode;
 		qcom,master-panel;
 		qcom,sync-dual-panel;

@@ -94,4 +104,17 @@ Example:
 		};
 	};
 
-
+	mdss_dsi_phy0: qcom,mdss_dsi_phy@fd922a00 {
+		compatible = "qcom,dsi-phy-28nm-hpm";
+		qcom,dsi-phy-index = <0>;
+		reg-names =
+			"dsi_pll",
+			"dsi_phy",
+			"dsi_phy_regulator";
+		reg =   <0xfd922a00 0xd4>,
+			<0xfd922b00 0x2b0>,
+			<0xfd922d80 0x7b>;
+		clock-names = "iface_clk";
+		clocks = <&mmcc MDSS_AHB_CLK>;
+		vddio-supply = <&pma8084_l12>;
+	}

drivers/gpu/drm/msm/dsi/dsi.c +36 -9

83 lines not on this page · raw message

drivers/gpu/drm/msm/dsi/dsi.h +20 -5

index 8022814..92d697d 100644
@@ -14,6 +14,7 @@
 #ifndef __DSI_CONNECTOR_H__
 #define __DSI_CONNECTOR_H__
 
+#include <linux/of_platform.h>
 #include <linux/platform_device.h>
 
 #include "drm_crtc.h"

@@ -39,12 +40,27 @@
 #define DSI_ENCODER_SLAVE	DSI_0
 
 enum msm_dsi_phy_type {
-	MSM_DSI_PHY_UNKNOWN,
 	MSM_DSI_PHY_28NM_HPM,
 	MSM_DSI_PHY_28NM_LP,
 	MSM_DSI_PHY_MAX
 };
 
+#define DSI_DEV_REGULATOR_MAX	8
+
+/* Regulators for DSI devices */
+struct dsi_reg_entry {
+	char name[32];
+	int min_voltage;
+	int max_voltage;
+	int enable_load;
+	int disable_load;
+};
+
+struct dsi_reg_config {
+	int num;
+	struct dsi_reg_entry regs[DSI_DEV_REGULATOR_MAX];
+};
+
 struct msm_dsi {
 	struct drm_device *dev;
 	struct platform_device *pdev;

@@ -57,7 +73,7 @@ struct msm_dsi {
 	struct drm_panel *panel;
 	unsigned long panel_flags;
 
-	enum msm_dsi_phy_type phy_type;
+	struct device *phy_dev;
 	bool phy_enabled;
 
 	/* the encoders we are hooked to (outside of dsi block) */

@@ -135,9 +151,8 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi);
 
 /* dsi phy */
 struct msm_dsi_phy;
-struct msm_dsi_phy *msm_dsi_phy_init(struct platform_device *pdev,
-			enum msm_dsi_phy_type type, int id);
-void msm_dsi_phy_destroy(struct msm_dsi_phy *phy);
+void msm_dsi_phy_driver_register(void);
+void msm_dsi_phy_driver_unregister(void);
 int msm_dsi_phy_enable(struct msm_dsi_phy *phy, bool is_dual_panel,
 	const unsigned long bit_rate, const unsigned long esc_rate);
 int msm_dsi_phy_disable(struct msm_dsi_phy *phy);

drivers/gpu/drm/msm/dsi/dsi_host.c +2 ~~-23~~

index 1cf9f11..59e524b 100644
@@ -36,35 +36,19 @@
 
 #define DSI_6G_REG_SHIFT	4
 
-#define DSI_REGULATOR_MAX	8
-struct dsi_reg_entry {
-	char name[32];
-	int min_voltage;
-	int max_voltage;
-	int enable_load;
-	int disable_load;
-};
-
-struct dsi_reg_config {
-	int num;
-	struct dsi_reg_entry regs[DSI_REGULATOR_MAX];
-};
-
 struct dsi_config {
 	u32 major;
 	u32 minor;
 	u32 io_offset;
-	enum msm_dsi_phy_type phy_type;
 	struct dsi_reg_config reg_cfg;
 };
 
 static const struct dsi_config dsi_cfgs[] = {
-	{MSM_DSI_VER_MAJOR_V2, 0, 0, MSM_DSI_PHY_UNKNOWN},
+	{MSM_DSI_VER_MAJOR_V2, 0, 0, {0,} },
 	{ /* 8974 v1 */
 		.major = MSM_DSI_VER_MAJOR_6G,
 		.minor = MSM_DSI_6G_VER_MINOR_V1_0,
 		.io_offset = DSI_6G_REG_SHIFT,
-		.phy_type = MSM_DSI_PHY_28NM_HPM,
 		.reg_cfg = {
 			.num = 4,
 			.regs = {

@@ -79,7 +63,6 @@ static const struct dsi_config dsi_cfgs[] = {
 		.major = MSM_DSI_VER_MAJOR_6G,
 		.minor = MSM_DSI_6G_VER_MINOR_V1_1,
 		.io_offset = DSI_6G_REG_SHIFT,
-		.phy_type = MSM_DSI_PHY_28NM_HPM,
 		.reg_cfg = {
 			.num = 4,
 			.regs = {

@@ -94,7 +77,6 @@ static const struct dsi_config dsi_cfgs[] = {
 		.major = MSM_DSI_VER_MAJOR_6G,
 		.minor = MSM_DSI_6G_VER_MINOR_V1_1_1,
 		.io_offset = DSI_6G_REG_SHIFT,
-		.phy_type = MSM_DSI_PHY_28NM_HPM,
 		.reg_cfg = {
 			.num = 4,
 			.regs = {

@@ -109,7 +91,6 @@ static const struct dsi_config dsi_cfgs[] = {
 		.major = MSM_DSI_VER_MAJOR_6G,
 		.minor = MSM_DSI_6G_VER_MINOR_V1_2,
 		.io_offset = DSI_6G_REG_SHIFT,
-		.phy_type = MSM_DSI_PHY_28NM_HPM,
 		.reg_cfg = {
 			.num = 4,
 			.regs = {

@@ -124,7 +105,6 @@ static const struct dsi_config dsi_cfgs[] = {
 		.major = MSM_DSI_VER_MAJOR_6G,
 		.minor = MSM_DSI_6G_VER_MINOR_V1_3_1,
 		.io_offset = DSI_6G_REG_SHIFT,
-		.phy_type = MSM_DSI_PHY_28NM_LP,
 		.reg_cfg = {
 			.num = 4,
 			.regs = {

@@ -197,7 +177,7 @@ struct msm_dsi_host {
 	int id;
 
 	void __iomem *ctrl_base;
-	struct regulator_bulk_data supplies[DSI_REGULATOR_MAX];
+	struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
 	struct clk *mdp_core_clk;
 	struct clk *ahb_clk;
 	struct clk *axi_clk;

@@ -1529,7 +1509,6 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi)
 
 	msm_dsi->host = &msm_host->base;
 	msm_dsi->id = msm_host->id;
-	msm_dsi->phy_type = msm_host->cfg->phy_type;
 
 	DBG("Dsi Host %d initialized", msm_host->id);
 	return 0;

drivers/gpu/drm/msm/dsi/dsi_phy.c +226 ~~-40~~

345 lines not on this page · raw message

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hosted by The Linux Foundation

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