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ath9k: add phy.c

PATCH New Oleksij Rempel 6 participants 12 messages May 15, 2015 – May 26, 2015 Qualcomm Atheros ATH9K wireless driver

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Oleksij Rempel

author
#0 lore raw

PATCH 1/1 ath9k: add phy.c

... and move dup code from ar5008_phy.c and ar9002_phy.c to phy.c

Signed-off-by Oleksij Rempel <[email protected]>
---
 drivers/net/wireless/ath/ath9k/Makefile     |   1 +
 drivers/net/wireless/ath/ath9k/ar5008_phy.c | 144 +----------------------
 drivers/net/wireless/ath/ath9k/ar9002_phy.c | 144 +----------------------
 drivers/net/wireless/ath/ath9k/phy.c        | 170 ++++++++++++++++++++++++++++
 drivers/net/wireless/ath/ath9k/phy.h        |   3 +
 5 files changed, 178 insertions(+), 284 deletions(-)
 create mode 100644 drivers/net/wireless/ath/ath9k/phy.c
drivers/net/wireless/ath/ath9k/Makefile +1 -0
index ecda613..6e129b9 100644
@@ -26,6 +26,7 @@ ath9k_hw-y:=	\
 		ar9002_hw.o \
 		ar9003_hw.o \
 		hw.o \
+		phy.o \
 		ar9003_phy.o \
 		ar9002_phy.o \
 		ar5008_phy.o \
drivers/net/wireless/ath/ath9k/ar5008_phy.c +2 -142

164 lines not on this page · raw message

drivers/net/wireless/ath/ath9k/ar9002_phy.c +2 -142

166 lines not on this page · raw message

drivers/net/wireless/ath/ath9k/phy.c new file +170 -0

170 lines not on this page · raw message

drivers/net/wireless/ath/ath9k/phy.h +3 -0
index 4a1b992..0086ad3 100644
@@ -55,4 +55,7 @@ enum ath9k_ant_div_comb_lna_conf {
 	ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2,
 };
 
+void phy_hw_spur_mitigate(struct ath_hw *ah,
+			  struct ath9k_channel *chan, int bin);
+
 #endif
Signature · 1 line
1.9.1
#1 lore raw

PATCH 1/1 ath9k: add phy.c

Hi Oleksij,

Quoted 1 line · Oleksij Rempel

... and move dup code from ar5008_phy.c and ar9002_phy.c to phy.c

A better subject might be:

ath9k: consolidate common phy functions

"phy.c" doesn't really mean anything to people outside the developers of this particular driver.

Thanks,

Signature · 4 lines
Julian Calaby

Email: julian.calaby at gmail.com
Profile: http://www.google.com/profiles/julian.calaby/
#2 lore raw

PATCH 1/1 ath9k: add phy.c

Quoted 12 lines · Julian Calaby

Hi Oleksij,

Quoted 1 line · Oleksij Rempel

... and move dup code from ar5008_phy.c and ar9002_phy.c to phy.c

A better subject might be:

ath9k: consolidate common phy functions

"phy.c" doesn't really mean anything to people outside the developers of this particular driver.

Jupp.

Is a consolidation also possible/wise/doable also for phy.h? ( I see this snippet in your new phy.c file... )
...
+#include "phy.h"
+#include "ar9002_phy.h"
...

IOW, can ar9002_phy.h move into phy.h?

- sed@ -

#3 lore raw

PATCH 1/1 ath9k: add phy.c

In reply to Oleksij Rempel
Quoted 1 line · Oleksij Rempel

... and move dup code from ar5008_phy.c and ar9002_phy.c to phy.c

[]

drivers/net/wireless/ath/ath9k/phy.c line 28

Quoted 10 lines
drivers/net/wireless/ath/ath9k/phy.c +8 -0
 
+void phy_hw_spur_mitigate(struct ath_hw *ah,
+			  struct ath9k_channel *chan, int bin)
+{
+	int cur_bin;
+	int upper, lower, cur_vit_mask;
+	int i;
+	int8_t mask_m[123];
+	int8_t mask_p[123];

Looking at this code, I'm not sure if mask_m and mask_p are always completely initialized by the loop below.

Perhaps use {} on declaration.

drivers/net/wireless/ath/ath9k/phy.c line 29

Quoted 1 line
drivers/net/wireless/ath/ath9k/phy.c +1 -0
+	int8_t mask_amt;

These int8_t could be s8

drivers/net/wireless/ath/ath9k/phy.c line 39

Quoted 10 lines
drivers/net/wireless/ath/ath9k/phy.c +10 -0
+	int tmp_mask;
+	static int pilot_mask_reg[4] = {
+		AR_PHY_TIMING7, AR_PHY_TIMING8,
+		AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
+	};
+	static int chan_mask_reg[4] = {
+		AR_PHY_TIMING9, AR_PHY_TIMING10,
+		AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
+	};
+	static int inc[4] = { 0, 100, 0, 0 };

static const

drivers/net/wireless/ath/ath9k/phy.c line 65

Quoted 4 lines
drivers/net/wireless/ath/ath9k/phy.c +4 -0
+	cur_vit_mask = 6100;
+	upper = bin + 120;
+	lower = bin - 120;
+

Is this loop guaranteed to always initialize all the mask_p and mask_m indexes used in the or statements below it?

The 123 for -61 and 0 and +61 array indexes is a bit obscure.

Quoted 104 lines
drivers/net/wireless/ath/ath9k/phy.c +104 -0
+	for (i = 0; i < 123; i++) {
+		if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
+			/* workaround for gcc bug #37014 */
+			volatile int tmp_v = abs(cur_vit_mask - bin);
+
+			if (tmp_v < 75)
+				mask_amt = 1;
+			else
+				mask_amt = 0;
+			if (cur_vit_mask < 0)
+				mask_m[abs(cur_vit_mask / 100)] = mask_amt;
+			else
+				mask_p[cur_vit_mask / 100] = mask_amt;
+		}
+		cur_vit_mask -= 100;
+	}
+
+	tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
+		| (mask_m[48] << 26) | (mask_m[49] << 24)
+		| (mask_m[50] << 22) | (mask_m[51] << 20)
+		| (mask_m[52] << 18) | (mask_m[53] << 16)
+		| (mask_m[54] << 14) | (mask_m[55] << 12)
+		| (mask_m[56] << 10) | (mask_m[57] << 8)
+		| (mask_m[58] << 6) | (mask_m[59] << 4)
+		| (mask_m[60] << 2) | (mask_m[61] << 0);
+	REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
+	REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
+
+	tmp_mask = (mask_m[31] << 28)
+		| (mask_m[32] << 26) | (mask_m[33] << 24)
+		| (mask_m[34] << 22) | (mask_m[35] << 20)
+		| (mask_m[36] << 18) | (mask_m[37] << 16)
+		| (mask_m[48] << 14) | (mask_m[39] << 12)
+		| (mask_m[40] << 10) | (mask_m[41] << 8)
+		| (mask_m[42] << 6) | (mask_m[43] << 4)
+		| (mask_m[44] << 2) | (mask_m[45] << 0);
+	REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
+	REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
+
+	tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
+		| (mask_m[18] << 26) | (mask_m[18] << 24)
+		| (mask_m[20] << 22) | (mask_m[20] << 20)
+		| (mask_m[22] << 18) | (mask_m[22] << 16)
+		| (mask_m[24] << 14) | (mask_m[24] << 12)
+		| (mask_m[25] << 10) | (mask_m[26] << 8)
+		| (mask_m[27] << 6) | (mask_m[28] << 4)
+		| (mask_m[29] << 2) | (mask_m[30] << 0);
+	REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
+	REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
+
+	tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
+		| (mask_m[2] << 26) | (mask_m[3] << 24)
+		| (mask_m[4] << 22) | (mask_m[5] << 20)
+		| (mask_m[6] << 18) | (mask_m[7] << 16)
+		| (mask_m[8] << 14) | (mask_m[9] << 12)
+		| (mask_m[10] << 10) | (mask_m[11] << 8)
+		| (mask_m[12] << 6) | (mask_m[13] << 4)
+		| (mask_m[14] << 2) | (mask_m[15] << 0);
+	REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
+	REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
+
+	tmp_mask = (mask_p[15] << 28)
+		| (mask_p[14] << 26) | (mask_p[13] << 24)
+		| (mask_p[12] << 22) | (mask_p[11] << 20)
+		| (mask_p[10] << 18) | (mask_p[9] << 16)
+		| (mask_p[8] << 14) | (mask_p[7] << 12)
+		| (mask_p[6] << 10) | (mask_p[5] << 8)
+		| (mask_p[4] << 6) | (mask_p[3] << 4)
+		| (mask_p[2] << 2) | (mask_p[1] << 0);
+	REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
+	REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
+
+	tmp_mask = (mask_p[30] << 28)
+		| (mask_p[29] << 26) | (mask_p[28] << 24)
+		| (mask_p[27] << 22) | (mask_p[26] << 20)
+		| (mask_p[25] << 18) | (mask_p[24] << 16)
+		| (mask_p[23] << 14) | (mask_p[22] << 12)
+		| (mask_p[21] << 10) | (mask_p[20] << 8)
+		| (mask_p[19] << 6) | (mask_p[18] << 4)
+		| (mask_p[17] << 2) | (mask_p[16] << 0);
+	REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
+	REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
+
+	tmp_mask = (mask_p[45] << 28)
+		| (mask_p[44] << 26) | (mask_p[43] << 24)
+		| (mask_p[42] << 22) | (mask_p[41] << 20)
+		| (mask_p[40] << 18) | (mask_p[39] << 16)
+		| (mask_p[38] << 14) | (mask_p[37] << 12)
+		| (mask_p[36] << 10) | (mask_p[35] << 8)
+		| (mask_p[34] << 6) | (mask_p[33] << 4)
+		| (mask_p[32] << 2) | (mask_p[31] << 0);
+	REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
+	REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
+
+	tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
+		| (mask_p[59] << 26) | (mask_p[58] << 24)
+		| (mask_p[57] << 22) | (mask_p[56] << 20)
+		| (mask_p[55] << 18) | (mask_p[54] << 16)
+		| (mask_p[53] << 14) | (mask_p[52] << 12)
+		| (mask_p[51] << 10) | (mask_p[50] << 8)
+		| (mask_p[49] << 6) | (mask_p[48] << 4)
+		| (mask_p[47] << 2) | (mask_p[46] << 0);
+	REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
+	REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
author
#4 lore raw

PATCH 1/1 ath9k: add phy.c

Am 15.05.2015 um 20:35 schrieb Joe Perches:

Quoted 142 lines · Oleksij Rempel
Quoted 1 line

... and move dup code from ar5008_phy.c and ar9002_phy.c to phy.c

[]

drivers/net/wireless/ath/ath9k/phy.c line 28

Quoted 10 lines
drivers/net/wireless/ath/ath9k/phy.c +8 -0
 
+void phy_hw_spur_mitigate(struct ath_hw *ah,
+			  struct ath9k_channel *chan, int bin)
+{
+	int cur_bin;
+	int upper, lower, cur_vit_mask;
+	int i;
+	int8_t mask_m[123];
+	int8_t mask_p[123];

Looking at this code, I'm not sure if mask_m and mask_p are always completely initialized by the loop below.

Perhaps use {} on declaration.

drivers/net/wireless/ath/ath9k/phy.c line 29

Quoted 1 line
drivers/net/wireless/ath/ath9k/phy.c +1 -0
+	int8_t mask_amt;

These int8_t could be s8

drivers/net/wireless/ath/ath9k/phy.c line 39

Quoted 10 lines
drivers/net/wireless/ath/ath9k/phy.c +10 -0
+	int tmp_mask;
+	static int pilot_mask_reg[4] = {
+		AR_PHY_TIMING7, AR_PHY_TIMING8,
+		AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
+	};
+	static int chan_mask_reg[4] = {
+		AR_PHY_TIMING9, AR_PHY_TIMING10,
+		AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
+	};
+	static int inc[4] = { 0, 100, 0, 0 };

static const

drivers/net/wireless/ath/ath9k/phy.c line 65

Quoted 4 lines
drivers/net/wireless/ath/ath9k/phy.c +4 -0
+	cur_vit_mask = 6100;
+	upper = bin + 120;
+	lower = bin - 120;
+

Is this loop guaranteed to always initialize all the mask_p and mask_m indexes used in the or statements below it?

The 123 for -61 and 0 and +61 array indexes is a bit obscure.

Quoted 96 lines
drivers/net/wireless/ath/ath9k/phy.c +96 -0
+	for (i = 0; i < 123; i++) {
+		if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
+			/* workaround for gcc bug #37014 */
+			volatile int tmp_v = abs(cur_vit_mask - bin);
+
+			if (tmp_v < 75)
+				mask_amt = 1;
+			else
+				mask_amt = 0;
+			if (cur_vit_mask < 0)
+				mask_m[abs(cur_vit_mask / 100)] = mask_amt;
+			else
+				mask_p[cur_vit_mask / 100] = mask_amt;
+		}
+		cur_vit_mask -= 100;
+	}
+
+	tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
+		| (mask_m[48] << 26) | (mask_m[49] << 24)
+		| (mask_m[50] << 22) | (mask_m[51] << 20)
+		| (mask_m[52] << 18) | (mask_m[53] << 16)
+		| (mask_m[54] << 14) | (mask_m[55] << 12)
+		| (mask_m[56] << 10) | (mask_m[57] << 8)
+		| (mask_m[58] << 6) | (mask_m[59] << 4)
+		| (mask_m[60] << 2) | (mask_m[61] << 0);
+	REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
+	REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
+
+	tmp_mask = (mask_m[31] << 28)
+		| (mask_m[32] << 26) | (mask_m[33] << 24)
+		| (mask_m[34] << 22) | (mask_m[35] << 20)
+		| (mask_m[36] << 18) | (mask_m[37] << 16)
+		| (mask_m[48] << 14) | (mask_m[39] << 12)
+		| (mask_m[40] << 10) | (mask_m[41] << 8)
+		| (mask_m[42] << 6) | (mask_m[43] << 4)
+		| (mask_m[44] << 2) | (mask_m[45] << 0);
+	REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
+	REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
+
+	tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
+		| (mask_m[18] << 26) | (mask_m[18] << 24)
+		| (mask_m[20] << 22) | (mask_m[20] << 20)
+		| (mask_m[22] << 18) | (mask_m[22] << 16)
+		| (mask_m[24] << 14) | (mask_m[24] << 12)
+		| (mask_m[25] << 10) | (mask_m[26] << 8)
+		| (mask_m[27] << 6) | (mask_m[28] << 4)
+		| (mask_m[29] << 2) | (mask_m[30] << 0);
+	REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
+	REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
+
+	tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
+		| (mask_m[2] << 26) | (mask_m[3] << 24)
+		| (mask_m[4] << 22) | (mask_m[5] << 20)
+		| (mask_m[6] << 18) | (mask_m[7] << 16)
+		| (mask_m[8] << 14) | (mask_m[9] << 12)
+		| (mask_m[10] << 10) | (mask_m[11] << 8)
+		| (mask_m[12] << 6) | (mask_m[13] << 4)
+		| (mask_m[14] << 2) | (mask_m[15] << 0);
+	REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
+	REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
+
+	tmp_mask = (mask_p[15] << 28)
+		| (mask_p[14] << 26) | (mask_p[13] << 24)
+		| (mask_p[12] << 22) | (mask_p[11] << 20)
+		| (mask_p[10] << 18) | (mask_p[9] << 16)
+		| (mask_p[8] << 14) | (mask_p[7] << 12)
+		| (mask_p[6] << 10) | (mask_p[5] << 8)
+		| (mask_p[4] << 6) | (mask_p[3] << 4)
+		| (mask_p[2] << 2) | (mask_p[1] << 0);
+	REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
+	REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
+
+	tmp_mask = (mask_p[30] << 28)
+		| (mask_p[29] << 26) | (mask_p[28] << 24)
+		| (mask_p[27] << 22) | (mask_p[26] << 20)
+		| (mask_p[25] << 18) | (mask_p[24] << 16)
+		| (mask_p[23] << 14) | (mask_p[22] << 12)
+		| (mask_p[21] << 10) | (mask_p[20] << 8)
+		| (mask_p[19] << 6) | (mask_p[18] << 4)
+		| (mask_p[17] << 2) | (mask_p[16] << 0);
+	REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
+	REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
+
+	tmp_mask = (mask_p[45] << 28)
+		| (mask_p[44] << 26) | (mask_p[43] << 24)
+		| (mask_p[42] << 22) | (mask_p[41] << 20)
+		| (mask_p[40] << 18) | (mask_p[39] << 16)
+		| (mask_p[38] << 14) | (mask_p[37] << 12)
+		| (mask_p[36] << 10) | (mask_p[35] << 8)
+		| (mask_p[34] << 6) | (mask_p[33] << 4)
+		| (mask_p[32] << 2) | (mask_p[31] << 0);
+	REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
+	REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
+
+	tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
+		| (mask_p[59] << 26) | (mask_p[58] << 24)
Quoted 10 lines

drivers/net/wireless/ath/ath9k/phy.c line 169

Quoted 8 lines
drivers/net/wireless/ath/ath9k/phy.c +8 -0
+		| (mask_p[57] << 22) | (mask_p[56] << 20)
+		| (mask_p[55] << 18) | (mask_p[54] << 16)
+		| (mask_p[53] << 14) | (mask_p[52] << 12)
+		| (mask_p[51] << 10) | (mask_p[50] << 8)
+		| (mask_p[49] << 6) | (mask_p[48] << 4)
+		| (mask_p[47] << 2) | (mask_p[46] << 0);
+	REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
+	REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);

Hi Joe,
Thank you for reviewing. This is cleanup patch, no fixes optimisations or regressions should be introduced. If you see some problems in this code, you are welcome to provide a patch on top of this one :)

Signature · 10 lines
Regards,
Oleksij

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#5 lore raw

PATCH 1/1 ath9k: add phy.c

Quoted 9 lines · Oleksij Rempel

Am 15.05.2015 um 20:35 schrieb Joe Perches:

Quoted 8 lines · Oleksij Rempel
Quoted 1 line

... and move dup code from ar5008_phy.c and ar9002_phy.c to phy.c

[]

drivers/net/wireless/ath/ath9k/phy.c line 23

Quoted 5 lines
drivers/net/wireless/ath/ath9k/phy.c +3 -0
 
+void phy_hw_spur_mitigate(struct ath_hw *ah,
+			  struct ath9k_channel *chan, int bin)
+{

[]

Quoted 6 lines
Quoted 3 lines

drivers/net/wireless/ath/ath9k/phy.c line 39

Quoted 1 line
drivers/net/wireless/ath/ath9k/phy.c +1 -0
+	static int inc[4] = { 0, 100, 0, 0 };

static const

This is cleanup patch, no fixes optimisations
or regressions should be introduced.

Hello Oleksij.

One of the old compilation units (ar9002_phy.c) had const on all those arrays, the other did not.

const should be used here.

Quoted 2 lines

If you see some problems in this
code, you are welcome to provide a patch on top of this one :)

I think you should take comments on the patches you submit.

author
#6 lore raw

PATCH 1/1 ath9k: add phy.c

Am 16.05.2015 um 07:36 schrieb Joe Perches:

Quoted 16 lines · Oleksij Rempel
Quoted 10 lines

Am 15.05.2015 um 20:35 schrieb Joe Perches:

Quoted 8 lines · Oleksij Rempel
Quoted 1 line

... and move dup code from ar5008_phy.c and ar9002_phy.c to phy.c

[]

drivers/net/wireless/ath/ath9k/phy.c line 23

Quoted 5 lines
drivers/net/wireless/ath/ath9k/phy.c +3 -0
 
+void phy_hw_spur_mitigate(struct ath_hw *ah,
+			  struct ath9k_channel *chan, int bin)
+{

[]

Quoted 3 lines
Quoted 3 lines

drivers/net/wireless/ath/ath9k/phy.c line 39

Quoted 1 line
drivers/net/wireless/ath/ath9k/phy.c +1 -0
+	static int inc[4] = { 0, 100, 0, 0 };

static const

Quoted 7 lines
Quoted 2 lines

This is cleanup patch, no fixes optimisations
or regressions should be introduced.

Hello Oleksij.

One of the old compilation units (ar9002_phy.c) had const on all those arrays, the other did not.

ok, thanks. changed to const version.

Quoted 6 lines

const should be used here.

Quoted 2 lines

If you see some problems in this
code, you are welcome to provide a patch on top of this one :)

I think you should take comments on the patches you submit.

What do you mean?

Signature · 10 lines
Regards,
Oleksij

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#7 lore raw

PATCH 1/1 ath9k: add phy.c

In reply to Oleksij Rempel
Quoted 3 lines · Oleksij Rempel

... and move dup code from ar5008_phy.c and ar9002_phy.c to phy.c

Signed-off-by Oleksij Rempel <[email protected]>

We already have base functionality for AR5008-AR9002 provided in some ar5008_phy.c, and ar5008_hw_attach_phy_ops is called for those chipsets as well. Please keep the de-duplicated code there instead of adding a new phy.c, because AR9003+ uses a completely different codepath.

- Felix

author
#8 lore raw

PATCH 1/1 ath9k: add phy.c

Am 15.05.2015 um 21:34 schrieb Felix Fietkau:

Quoted 11 lines · Oleksij Rempel
Quoted 3 lines

... and move dup code from ar5008_phy.c and ar9002_phy.c to phy.c

Signed-off-by Oleksij Rempel <[email protected]>

We already have base functionality for AR5008-AR9002 provided in some ar5008_phy.c, and ar5008_hw_attach_phy_ops is called for those chipsets as well. Please keep the de-duplicated code there instead of adding a new phy.c, because AR9003+ uses a completely different codepath.

- Felix

ok, thanks.
Currently i celled this function phy_hw_spur_mitigate(), is it ok or there is some better name for this code?

Signature · 2 lines
Regards,
Oleksij
#9 lore raw

PATCH 1/1 ath9k: add phy.c

Quoted 10 lines · Oleksij Rempel

Am 15.05.2015 um 21:34 schrieb Felix Fietkau:

Quoted 9 lines · Oleksij Rempel
Quoted 3 lines

... and move dup code from ar5008_phy.c and ar9002_phy.c to phy.c

Signed-off-by Oleksij Rempel <[email protected]>

We already have base functionality for AR5008-AR9002 provided in some ar5008_phy.c, and ar5008_hw_attach_phy_ops is called for those chipsets as well. Please keep the de-duplicated code there instead of adding a new phy.c, because AR9003+ uses a completely different codepath.

Quoted 6 lines
Quoted 2 lines

- Felix

ok, thanks.
Currently i celled this function phy_hw_spur_mitigate(), is it ok or there is some better name for this code?

Just use the ar5008 prefix like in the other functions.

- Felix

author
#10 lore raw

PATCH 1/1 ath9k: split ar5008_hw_spur_mitigate and reuse common code in ar9002_hw_spur_mitigate.

[ar5008 and ar9002]_hw_spur_mitigate have big portion of identical code. This patch will move common part of ar5008_hw_spur_mitigate to ar5008_hw_cmn_spur_mitigate and reuse it in ar9002_hw_spur_mitigate.

As noticed by Joe Perches I reuse ar9002_hw_spur_mitigate (const) version of declarations for pilot_mask_reg and chan_mask_reg.

There should be no other difference with original code.

Signed-off-by Oleksij Rempel <[email protected]>
---
 drivers/net/wireless/ath/ath9k/ar5008_phy.c | 155 +++++++++++++++-------------
 drivers/net/wireless/ath/ath9k/ar9002_phy.c | 144 +-------------------------
 drivers/net/wireless/ath/ath9k/hw.h         |   2 +
 3 files changed, 87 insertions(+), 214 deletions(-)
drivers/net/wireless/ath/ath9k/ar5008_phy.c +83 -72
index 6c23d27..8f87930 100644
@@ -254,86 +254,25 @@ static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
 	return 0;
 }
 
-/**
- * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios
- * @ah: atheros hardware structure
- * @chan:
- *
- * For non single-chip solutions. Converts to baseband spur frequency given the
- * input channel frequency and compute register settings below.
- */
-static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
-				    struct ath9k_channel *chan)
+void ar5008_hw_cmn_spur_mitigate(struct ath_hw *ah,
+			  struct ath9k_channel *chan, int bin)
 {
-	int bb_spur = AR_NO_SPUR;
-	int bin, cur_bin;
-	int spur_freq_sd;
-	int spur_delta_phase;
-	int denominator;
+	int cur_bin;
 	int upper, lower, cur_vit_mask;
-	int tmp, new;
 	int i;
-	static int pilot_mask_reg[4] = {
+	int8_t mask_m[123];
+	int8_t mask_p[123];
+	int8_t mask_amt;
+	int tmp_mask;
+	static const int pilot_mask_reg[4] = {
 		AR_PHY_TIMING7, AR_PHY_TIMING8,
 		AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
 	};
-	static int chan_mask_reg[4] = {
+	static const int chan_mask_reg[4] = {
 		AR_PHY_TIMING9, AR_PHY_TIMING10,
 		AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
 	};
-	static int inc[4] = { 0, 100, 0, 0 };
-
-	int8_t mask_m[123];
-	int8_t mask_p[123];
-	int8_t mask_amt;
-	int tmp_mask;
-	int cur_bb_spur;
-	bool is2GHz = IS_CHAN_2GHZ(chan);
-
-	memset(&mask_m, 0, sizeof(int8_t) * 123);
-	memset(&mask_p, 0, sizeof(int8_t) * 123);
-
-	for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
-		cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
-		if (AR_NO_SPUR == cur_bb_spur)
-			break;
-		cur_bb_spur = cur_bb_spur - (chan->channel * 10);
-		if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
-			bb_spur = cur_bb_spur;
-			break;
-		}
-	}
-
-	if (AR_NO_SPUR == bb_spur)
-		return;
-
-	bin = bb_spur * 32;
-
-	tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
-	new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
-		     AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
-		     AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
-		     AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
-
-	REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
-
-	new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
-	       AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
-	       AR_PHY_SPUR_REG_MASK_RATE_SELECT |
-	       AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
-	       SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
-	REG_WRITE(ah, AR_PHY_SPUR_REG, new);
-
-	spur_delta_phase = ((bb_spur * 524288) / 100) &
-		AR_PHY_TIMING11_SPUR_DELTA_PHASE;
-
-	denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
-	spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
-
-	new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
-	       SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
-	       SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
-	REG_WRITE(ah, AR_PHY_TIMING11, new);
+	static const int inc[4] = { 0, 100, 0, 0 };
 
 	cur_bin = -6000;
 	upper = bin + 100;

@@ -343,6 +282,7 @@ static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
 		int pilot_mask = 0;
 		int chan_mask = 0;
 		int bp = 0;
+
 		for (bp = 0; bp < 30; bp++) {
 			if ((cur_bin > lower) && (cur_bin < upper)) {
 				pilot_mask = pilot_mask | 0x1 << bp;

@@ -361,7 +301,6 @@ static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
 
 	for (i = 0; i < 123; i++) {
 		if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
-
 			/* workaround for gcc bug #37014 */
 			volatile int tmp_v = abs(cur_vit_mask - bin);
 

@@ -467,6 +406,78 @@ static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
 }
 
 /**
+ * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios
+ * @ah: atheros hardware structure
+ * @chan:
+ *
+ * For non single-chip solutions. Converts to baseband spur frequency given the
+ * input channel frequency and compute register settings below.
+ */
+static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
+				    struct ath9k_channel *chan)
+{
+	int bb_spur = AR_NO_SPUR;
+	int bin;
+	int spur_freq_sd;
+	int spur_delta_phase;
+	int denominator;
+	int tmp, new;
+	int i;
+
+	int8_t mask_m[123];
+	int8_t mask_p[123];
+	int cur_bb_spur;
+	bool is2GHz = IS_CHAN_2GHZ(chan);
+
+	memset(&mask_m, 0, sizeof(int8_t) * 123);
+	memset(&mask_p, 0, sizeof(int8_t) * 123);
+
+	for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
+		cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
+		if (AR_NO_SPUR == cur_bb_spur)
+			break;
+		cur_bb_spur = cur_bb_spur - (chan->channel * 10);
+		if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
+			bb_spur = cur_bb_spur;
+			break;
+		}
+	}
+
+	if (AR_NO_SPUR == bb_spur)
+		return;
+
+	bin = bb_spur * 32;
+
+	tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
+	new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
+		     AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
+		     AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
+		     AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
+
+	REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
+
+	new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
+	       AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
+	       AR_PHY_SPUR_REG_MASK_RATE_SELECT |
+	       AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
+	       SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
+	REG_WRITE(ah, AR_PHY_SPUR_REG, new);
+
+	spur_delta_phase = ((bb_spur * 524288) / 100) &
+		AR_PHY_TIMING11_SPUR_DELTA_PHASE;
+
+	denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
+	spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
+
+	new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
+	       SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
+	       SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
+	REG_WRITE(ah, AR_PHY_TIMING11, new);
+
+	ar5008_hw_cmn_spur_mitigate(ah, chan, bin);
+}
+
+/**
  * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming
  * @ah: atheros hardware structure
  *
drivers/net/wireless/ath/ath9k/ar9002_phy.c +2 -142

166 lines not on this page · raw message

drivers/net/wireless/ath/ath9k/hw.h +2 -0
index c1d2d03..e8454db 100644
@@ -1119,6 +1119,8 @@ bool ar9003_is_paprd_enabled(struct ath_hw *ah);
 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx);
 void ar9003_hw_init_rate_txpower(struct ath_hw *ah, u8 *rate_array,
 				 struct ath9k_channel *chan);
+void ar5008_hw_cmn_spur_mitigate(struct ath_hw *ah,
+				 struct ath9k_channel *chan, int bin);
 void ar5008_hw_init_rate_txpower(struct ath_hw *ah, int16_t *rate_array,
 				 struct ath9k_channel *chan, int ht40_delta);
Signature · 1 line
1.9.1
Applied
#11 lore raw

Re: ath9k: split ar5008_hw_spur_mitigate and reuse common code inar9002_hw_spur_mitigate.

Quoted 11 lines

[ar5008 and ar9002]_hw_spur_mitigate have big portion of identical code. This patch will move common part of ar5008_hw_spur_mitigate to ar5008_hw_cmn_spur_mitigate and reuse it in ar9002_hw_spur_mitigate.

As noticed by Joe Perches I reuse ar9002_hw_spur_mitigate (const) version of declarations for pilot_mask_reg and chan_mask_reg.

There should be no other difference with original code.

Signed-off-by Oleksij Rempel <[email protected]>

Thanks, applied to wireless-drivers-next.git.

Kalle Valo