ARM: sa1100: add platform functions to handle PWER settings

PATCH RESEND New Dmitry Eremin-Solenikov 2 participants 7 messages May 18, 2015

Subsystems (3)

Arm (32-bit) Arm sub-architectures irqchip drivers

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Dmitry Eremin-Solenikov

author

2015-05-18 14:44 UTC #0 lore raw

PATCH RESEND 1/5 ARM: sa1100: add platform functions to handle PWER settings

PWER settings logically belongs neither to GPIO nor to system IRQ code. Add special functions to handle PWER (for GPIO and for system IRQs) from platform code.

Signed-off-by Dmitry Eremin-Solenikov <[email protected]>

---
 arch/arm/mach-sa1100/generic.c | 24 ++++++++++++++++++++++++
 include/soc/sa1100/pwer.h      | 15 +++++++++++++++
 2 files changed, 39 insertions(+)
 create mode 100644 include/soc/sa1100/pwer.h

arch/arm/mach-sa1100/generic.c +24 -0

index 40e0d86..c651f6e 100644
@@ -23,6 +23,8 @@
 
 #include <video/sa1100fb.h>
 
+#include <soc/sa1100/pwer.h>
+
 #include <asm/div64.h>
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>

@@ -416,3 +418,25 @@ void sa1110_mb_enable(void)
 	local_irq_restore(flags);
 }
 
+int sa11x0_gpio_set_wake(unsigned int gpio, unsigned int on)
+{
+	if (on)
+		PWER |= BIT(gpio);
+	else
+		PWER &= ~BIT(gpio);
+
+	return 0;
+}
+
+int sa11x0_sc_set_wake(unsigned int irq, unsigned int on)
+{
+	if (BIT(irq) != IC_RTCAlrm)
+		return -EINVAL;
+
+	if (on)
+		PWER |= PWER_RTC;
+	else
+		PWER &= ~PWER_RTC;
+
+	return 0;
+}

include/soc/sa1100/pwer.h new file +15 -0

new file mode 100644
index 0000000..15a545b
@@ -0,0 +1,15 @@
+#ifndef SOC_SA1100_PWER_H
+#define SOC_SA1100_PWER_H
+
+/*
+ * Copyright (C) 2015, Dmitry Eremin-Solenikov
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+int sa11x0_gpio_set_wake(unsigned int gpio, unsigned int on);
+int sa11x0_sc_set_wake(unsigned int irq, unsigned int on);
+
+#endif

Signature · 1 line

2.1.4

Dmitry Eremin-Solenikov

author

2015-05-18 14:44 UTC #1 lore raw

PATCH RESEND 2/5 ARM: sa1100: use sa11x0_sc_set_wake() in irq driver

Use new function controlling PWER register in IRQ driver.

Signed-off-by Dmitry Eremin-Solenikov <[email protected]>

---
 arch/arm/mach-sa1100/irq.c | 14 +++-----------
 1 file changed, 3 insertions(+), 11 deletions(-)

arch/arm/mach-sa1100/irq.c +3 ~~-11~~

index 65aebfa..6afaa33 100644
@@ -18,6 +18,8 @@
 #include <linux/ioport.h>
 #include <linux/syscore_ops.h>
 
+#include <soc/sa1100/pwer.h>
+
 #include <mach/hardware.h>
 #include <mach/irqs.h>
 #include <asm/mach/irq.h>

@@ -40,19 +42,9 @@ static void sa1100_unmask_irq(struct irq_data *d)
 	ICMR |= BIT(d->hwirq);
 }
 
-/*
- * Apart form GPIOs, only the RTC alarm can be a wakeup event.
- */
 static int sa1100_set_wake(struct irq_data *d, unsigned int on)
 {
-	if (BIT(d->hwirq) == IC_RTCAlrm) {
-		if (on)
-			PWER |= PWER_RTC;
-		else
-			PWER &= ~PWER_RTC;
-		return 0;
-	}
-	return -EINVAL;
+	return sa11x0_sc_set_wake(d->hwirq, on);
 }
 
 static struct irq_chip sa1100_normal_chip = {

Signature · 1 line

2.1.4

Dmitry Eremin-Solenikov

author

2015-05-18 14:44 UTC #2 lore raw

PATCH RESEND 3/5 ARM: sa1100: use ioremapped memory to access SC registers

In reply to Dmitry Eremin-Solenikov

Use ioremap() and readl/writel_relaxed() to access IRQ controller registers.

Signed-off-by Dmitry Eremin-Solenikov <[email protected]>

---
 arch/arm/mach-sa1100/irq.c | 52 ++++++++++++++++++++++++++++++----------------
 1 file changed, 34 insertions(+), 18 deletions(-)

arch/arm/mach-sa1100/irq.c +34 ~~-18~~

index 6afaa33..08f929e 100644
@@ -20,13 +20,19 @@
 
 #include <soc/sa1100/pwer.h>
 
-#include <mach/hardware.h>
 #include <mach/irqs.h>
-#include <asm/mach/irq.h>
 #include <asm/exception.h>
 
 #include "generic.h"
 
+#define ICIP	0x00  /* IC IRQ Pending reg. */
+#define ICMR	0x04  /* IC Mask Reg.        */
+#define ICLR	0x08  /* IC Level Reg.       */
+#define ICCR	0x0C  /* IC Control Reg.     */
+#define ICFP	0x10  /* IC FIQ Pending reg. */
+#define ICPR	0x20  /* IC Pending Reg.     */
+
+static void __iomem *iobase;
 
 /*
  * We don't need to ACK IRQs on the SA1100 unless they're GPIOs

@@ -34,12 +40,20 @@
  */
 static void sa1100_mask_irq(struct irq_data *d)
 {
-	ICMR &= ~BIT(d->hwirq);
+	u32 reg;
+
+	reg = readl_relaxed(iobase + ICMR);
+	reg &= ~BIT(d->hwirq);
+	writel_relaxed(reg, iobase + ICMR);
 }
 
 static void sa1100_unmask_irq(struct irq_data *d)
 {
-	ICMR |= BIT(d->hwirq);
+	u32 reg;
+
+	reg = readl_relaxed(iobase + ICMR);
+	reg |= BIT(d->hwirq);
+	writel_relaxed(reg, iobase + ICMR);
 }
 
 static int sa1100_set_wake(struct irq_data *d, unsigned int on)

@@ -87,16 +101,14 @@ static int sa1100irq_suspend(void)
 	struct sa1100irq_state *st = &sa1100irq_state;
 
 	st->saved = 1;
-	st->icmr = ICMR;
-	st->iclr = ICLR;
-	st->iccr = ICCR;
+	st->icmr = readl_relaxed(iobase + ICMR);
+	st->iclr = readl_relaxed(iobase + ICLR);
+	st->iccr = readl_relaxed(iobase + ICCR);
 
 	/*
 	 * Disable all GPIO-based interrupts.
 	 */
-	ICMR &= ~(IC_GPIO11_27|IC_GPIO10|IC_GPIO9|IC_GPIO8|IC_GPIO7|
-		  IC_GPIO6|IC_GPIO5|IC_GPIO4|IC_GPIO3|IC_GPIO2|
-		  IC_GPIO1|IC_GPIO0);
+	writel_relaxed(st->icmr & 0xfffff000, iobase + ICMR);
 
 	return 0;
 }

@@ -106,10 +118,10 @@ static void sa1100irq_resume(void)
 	struct sa1100irq_state *st = &sa1100irq_state;
 
 	if (st->saved) {
-		ICCR = st->iccr;
-		ICLR = st->iclr;
+		writel_relaxed(st->iccr, iobase + ICCR);
+		writel_relaxed(st->iclr, iobase + ICLR);
 
-		ICMR = st->icmr;
+		writel_relaxed(st->icmr, iobase + ICMR);
 	}
 }

@@ -132,8 +144,8 @@ sa1100_handle_irq(struct pt_regs *regs)
 	uint32_t icip, icmr, mask;
 
 	do {
-		icip = (ICIP);
-		icmr = (ICMR);
+		icip = readl_relaxed(iobase + ICIP);
+		icmr = readl_relaxed(iobase + ICMR);
 		mask = icip & icmr;
 
 		if (mask == 0)

@@ -148,17 +160,21 @@ void __init sa1100_init_irq(void)
 {
 	request_resource(&iomem_resource, &irq_resource);
 
+	iobase = ioremap(irq_resource.start, SZ_64K);
+	if (WARN_ON(!iobase))
+		return;
+
 	/* disable all IRQs */
-	ICMR = 0;
+	writel_relaxed(0, iobase + ICMR);
 
 	/* all IRQs are IRQ, not FIQ */
-	ICLR = 0;
+	writel_relaxed(0, iobase + ICLR);
 
 	/*
 	 * Whatever the doc says, this has to be set for the wait-on-irq
 	 * instruction to work... on a SA1100 rev 9 at least.
 	 */
-	ICCR = 1;
+	writel_relaxed(1, iobase + ICCR);
 
 	sa1100_normal_irqdomain = irq_domain_add_simple(NULL,
 			32, IRQ_GPIO0_SC,

Signature · 1 line

2.1.4

Dmitry Eremin-Solenikov

author

2015-05-18 14:44 UTC #3 lore raw

PATCH RESEND 4/5 ARM: sa1100: move irq driver to drivers/irqchip/

In reply to Dmitry Eremin-Solenikov

Move current sa11x0 IRQ driver to the irqchip subsystem. The driver is not yet modified to be a proper part of irqchip subsystem, it will be a next step.

Signed-off-by Dmitry Eremin-Solenikov <[email protected]>

---
 arch/arm/mach-sa1100/Makefile                              | 2 +-
 drivers/irqchip/Makefile                                   | 1 +
 arch/arm/mach-sa1100/irq.c => drivers/irqchip/irq-sa11x0.c | 6 +++---
 3 files changed, 5 insertions(+), 4 deletions(-)
 rename arch/arm/mach-sa1100/irq.c => drivers/irqchip/irq-sa11x0.c (96%)

arch/arm/mach-sa1100/Makefile +1 -1

index 61ff91e..ebc4d58 100644
@@ -3,7 +3,7 @@
 #
 
 # Common support
-obj-y := clock.o generic.o irq.o #nmi-oopser.o
+obj-y := clock.o generic.o #nmi-oopser.o
 
 # Specific board support
 obj-$(CONFIG_SA1100_ASSABET)		+= assabet.o

drivers/irqchip/Makefile +1 -0

index dda4927..49f372a 100644
@@ -47,3 +47,4 @@ obj-$(CONFIG_KEYSTONE_IRQ)		+= irq-keystone.o
 obj-$(CONFIG_MIPS_GIC)			+= irq-mips-gic.o
 obj-$(CONFIG_ARCH_MEDIATEK)		+= irq-mtk-sysirq.o
 obj-$(CONFIG_ARCH_DIGICOLOR)		+= irq-digicolor.o
+obj-$(CONFIG_ARCH_SA1100)		+= irq-sa11x0.o

drivers/irqchip/irq-sa11x0.c renamed from arch/arm/mach-sa1100/irq.c +3 -3

similarity index 96%
rename from arch/arm/mach-sa1100/irq.c
rename to drivers/irqchip/irq-sa11x0.c
index 08f929e..a5e1a54 100644
@@ -1,9 +1,9 @@
 /*
- * linux/arch/arm/mach-sa1100/irq.c
+ * drivers/irqchip/irq-sa11x0.c
  *
  * Copyright (C) 1999-2001 Nicolas Pitre
  *
- * Generic IRQ handling for the SA11x0, GPIO 11-27 IRQ demultiplexing.
+ * Generic IRQ handling for the SA11x0.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as

@@ -23,7 +23,7 @@
 #include <mach/irqs.h>
 #include <asm/exception.h>
 
-#include "generic.h"
+#include "../../arch/arm/mach-sa1100/generic.h"
 
 #define ICIP	0x00  /* IC IRQ Pending reg. */
 #define ICMR	0x04  /* IC Mask Reg.        */

Signature · 1 line

2.1.4

Dmitry Eremin-Solenikov

author

2015-05-18 14:44 UTC #4 lore raw

PATCH RESEND 5/5 ARM: sa1100: properly split irqchip driver

In reply to Dmitry Eremin-Solenikov

Finally properly split the irq driver into generic init code and irqchip driver.

Signed-off-by Dmitry Eremin-Solenikov <[email protected]>

---
 arch/arm/mach-sa1100/generic.c     | 13 +++++++++++++
 drivers/irqchip/irq-sa11x0.c       | 18 ++++--------------
 include/linux/irqchip/irq-sa11x0.h | 16 ++++++++++++++++
 3 files changed, 33 insertions(+), 14 deletions(-)
 create mode 100644 include/linux/irqchip/irq-sa11x0.h

arch/arm/mach-sa1100/generic.c +13 -0

index c651f6e..345e63f 100644
@@ -20,6 +20,7 @@
 #include <linux/ioport.h>
 #include <linux/platform_device.h>
 #include <linux/reboot.h>
+#include <linux/irqchip/irq-sa11x0.h>
 
 #include <video/sa1100fb.h>

@@ -377,6 +378,18 @@ void __init sa1100_timer_init(void)
 	pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x90000000), 3686400);
 }
 
+static struct resource irq_resource =
+	DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs");
+
+void __init sa1100_init_irq(void)
+{
+	request_resource(&iomem_resource, &irq_resource);
+
+	sa11x0_init_irq_nodt(IRQ_GPIO0_SC, irq_resource.start);
+
+	sa1100_init_gpio();
+}
+
 /*
  * Disable the memory bus request/grant signals on the SA1110 to
  * ensure that we don't receive spurious memory requests.  We set

drivers/irqchip/irq-sa11x0.c +4 ~~-14~~

index a5e1a54..76b8c1d 100644
@@ -15,16 +15,13 @@
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/irqdomain.h>
-#include <linux/ioport.h>
 #include <linux/syscore_ops.h>
+#include <linux/irqchip/irq-sa11x0.h>
 
 #include <soc/sa1100/pwer.h>
 
-#include <mach/irqs.h>
 #include <asm/exception.h>
 
-#include "../../arch/arm/mach-sa1100/generic.h"
-
 #define ICIP	0x00  /* IC IRQ Pending reg. */
 #define ICMR	0x04  /* IC Mask Reg.        */
 #define ICLR	0x08  /* IC Level Reg.       */

@@ -86,9 +83,6 @@ static struct irq_domain_ops sa1100_normal_irqdomain_ops = {
 
 static struct irq_domain *sa1100_normal_irqdomain;
 
-static struct resource irq_resource =
-	DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs");
-
 static struct sa1100irq_state {
 	unsigned int	saved;
 	unsigned int	icmr;

@@ -156,11 +150,9 @@ sa1100_handle_irq(struct pt_regs *regs)
 	} while (1);
 }
 
-void __init sa1100_init_irq(void)
+void __init sa11x0_init_irq_nodt(int irq_start, resource_size_t io_start)
 {
-	request_resource(&iomem_resource, &irq_resource);
-
-	iobase = ioremap(irq_resource.start, SZ_64K);
+	iobase = ioremap(io_start, SZ_64K);
 	if (WARN_ON(!iobase))
 		return;

@@ -177,10 +169,8 @@ void __init sa1100_init_irq(void)
 	writel_relaxed(1, iobase + ICCR);
 
 	sa1100_normal_irqdomain = irq_domain_add_simple(NULL,
-			32, IRQ_GPIO0_SC,
+			32, irq_start,
 			&sa1100_normal_irqdomain_ops, NULL);
 
 	set_handle_irq(sa1100_handle_irq);
-
-	sa1100_init_gpio();
 }

include/linux/irqchip/irq-sa11x0.h new file +16 -0

new file mode 100644
index 0000000..2f66eca
@@ -0,0 +1,16 @@
+/*
+ * Generic IRQ handling for the SA11x0.
+ *
+ * Copyright (C) 1999-2001 Nicolas Pitre
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_SA11x0_H
+#define __INCLUDE_LINUX_IRQCHIP_IRQ_SA11x0_H
+
+void __init sa11x0_init_irq_nodt(int irq_start, resource_size_t io_start);
+
+#endif

Signature · 1 line

2.1.4

Russell King - ARM Linux

2015-05-18 14:52 UTC #5 lore raw

PATCH RESEND 1/5 ARM: sa1100: add platform functions to handle PWER settings

In reply to Dmitry Eremin-Solenikov

No cover letter, so I'll top-reply to the first patch, since my comments aren't specific to this patch.

Patches 1-3 look fine, no problem there.

Patches 4 and 5 I think should be in the reverse order - update the IRQ code first, and make it independent of things in arch/arm/mach-sa1100, and once that's done, move it out of there.

Quoted 74 lines · Dmitry Eremin-Solenikov

PWER settings logically belongs neither to GPIO nor to system IRQ code. Add special functions to handle PWER (for GPIO and for system IRQs) from platform code.

Signed-off-by Dmitry Eremin-Solenikov <[email protected]>

---
 arch/arm/mach-sa1100/generic.c | 24 ++++++++++++++++++++++++
 include/soc/sa1100/pwer.h      | 15 +++++++++++++++
 2 files changed, 39 insertions(+)
 create mode 100644 include/soc/sa1100/pwer.h

arch/arm/mach-sa1100/generic.c +24 -0

index 40e0d86..c651f6e 100644
@@ -23,6 +23,8 @@
 
 #include <video/sa1100fb.h>
 
+#include <soc/sa1100/pwer.h>
+
 #include <asm/div64.h>
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>

@@ -416,3 +418,25 @@ void sa1110_mb_enable(void)
 	local_irq_restore(flags);
 }
 
+int sa11x0_gpio_set_wake(unsigned int gpio, unsigned int on)
+{
+	if (on)
+		PWER |= BIT(gpio);
+	else
+		PWER &= ~BIT(gpio);
+
+	return 0;
+}
+
+int sa11x0_sc_set_wake(unsigned int irq, unsigned int on)
+{
+	if (BIT(irq) != IC_RTCAlrm)
+		return -EINVAL;
+
+	if (on)
+		PWER |= PWER_RTC;
+	else
+		PWER &= ~PWER_RTC;
+
+	return 0;
+}

include/soc/sa1100/pwer.h new file +15 -0

new file mode 100644
index 0000000..15a545b
@@ -0,0 +1,15 @@
+#ifndef SOC_SA1100_PWER_H
+#define SOC_SA1100_PWER_H
+
+/*
+ * Copyright (C) 2015, Dmitry Eremin-Solenikov
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+int sa11x0_gpio_set_wake(unsigned int gpio, unsigned int on);
+int sa11x0_sc_set_wake(unsigned int irq, unsigned int on);
+
+#endif

Signature · 1 line

2.1.4

Signature · 2 lines

FTTC broadband for 0.8mile line: currently at 10.5Mbps down 400kbps up
according to speedtest.net.

Dmitry Eremin-Solenikov

author

2015-05-18 14:57 UTC #6 lore raw

PATCH RESEND 1/5 ARM: sa1100: add platform functions to handle PWER settings

2015-05-18 17:52 GMT+03:00 Russell King - ARM Linux <[email protected]>:

Quoted 8 lines

No cover letter, so I'll top-reply to the first patch, since my comments aren't specific to this patch.
Patches 1-3 look fine, no problem there.
Patches 4 and 5 I think should be in the reverse order - update the IRQ code first, and make it independent of things in arch/arm/mach-sa1100, and once that's done, move it out of there.

Thank you for the review. I'll push 1-3 to patch tracker now and will resubmit 4,5 in the evening.

Signature · 2 lines

With best wishes
Dmitry