Skip to contentSkip to conversation

drm/i915/bxt: limit WaDisableMaskBasedCammingInRCC to stepping A

PATCH In review Imre Deak 5 participants 17 messages May 19, 2015 – May 21, 2015

Subsystems (2)
DRM drivers Intel i915
lore
Share & tools
lore

Imre Deak

author
#0 lore raw

PATCH 1/4 drm/i915/bxt: limit WaDisableMaskBasedCammingInRCC to stepping A

Also make the WA comment consistent with the rest, where the stepping info is not shown.

Signed-off-by Imre Deak <[email protected]>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

[ The patchset is a follow-up to:
http://lists.freedesktop.org/archives/intel-gfx/2015-May/065989.html ]

drivers/gpu/drm/i915/intel_ringbuffer.c +3 -6
index 9b96ed7..461b9be 100644
@@ -961,12 +961,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 	WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 			  GEN9_CCS_TLB_PREFETCH_ENABLE);
 
-	/*
-	 * FIXME: don't apply the following on BXT for stepping C. On BXT A0
-	 * the flag reads back as 0.
-	 */
-	/* WaDisableMaskBasedCammingInRCC:sklC,bxtA */
-	if (INTEL_REVID(dev) == SKL_REVID_C0 || IS_BROXTON(dev))
+	/* WaDisableMaskBasedCammingInRCC:skl,bxt */
+	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) ||
+	    (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0))
 		WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
 				  PIXEL_MASK_CAMMING_DISABLE);
Signature · 6 lines
2.1.4

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
author
#1 lore raw

PATCH 2/4 drm/i915/skl: add F0 stepping ID

Signed-off-by Imre Deak <[email protected]>
---
 drivers/gpu/drm/i915/i915_drv.h | 1 +
 1 file changed, 1 insertion(+)
drivers/gpu/drm/i915/i915_drv.h +1 -0
index 840f08f..731b5ce 100644
@@ -2378,6 +2378,7 @@ struct drm_i915_cmd_table {
 #define SKL_REVID_C0		(0x2)
 #define SKL_REVID_D0		(0x3)
 #define SKL_REVID_E0		(0x4)
+#define SKL_REVID_F0		(0x5)
 
 #define BXT_REVID_A0		(0x0)
 #define BXT_REVID_B0		(0x3)
Signature · 6 lines
2.1.4

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Reviewed-by on v1 2/4
#2 lore raw

Re: [PATCH 2/4] drm/i915/skl: add F0 stepping ID

Quoted 1 line · Imre Deak
Signed-off-by Imre Deak <[email protected]>
Reviewed-by Damien Lespiau <[email protected]>
Quoted 23 lines
---
 drivers/gpu/drm/i915/i915_drv.h | 1 +
 1 file changed, 1 insertion(+)
drivers/gpu/drm/i915/i915_drv.h +1 -0
index 840f08f..731b5ce 100644
@@ -2378,6 +2378,7 @@ struct drm_i915_cmd_table {
 #define SKL_REVID_C0		(0x2)
 #define SKL_REVID_D0		(0x3)
 #define SKL_REVID_E0		(0x4)
+#define SKL_REVID_F0		(0x5)
 
 #define BXT_REVID_A0		(0x0)
 #define BXT_REVID_B0		(0x3)
Signature · 6 lines
2.1.4

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

#3 lore raw

Re: [PATCH 2/4] drm/i915/skl: add F0 stepping ID

Quoted 4 lines · Damien Lespiau
Quoted 1 line · Imre Deak
Signed-off-by Imre Deak <[email protected]>
Reviewed-by Damien Lespiau <[email protected]>

Merged the first 2 patches from this series to dinq, thanks. -Daniel

Quoted 24 lines
Quoted 24 lines
---
 drivers/gpu/drm/i915/i915_drv.h | 1 +
 1 file changed, 1 insertion(+)
drivers/gpu/drm/i915/i915_drv.h +1 -0
index 840f08f..731b5ce 100644
@@ -2378,6 +2378,7 @@ struct drm_i915_cmd_table {
 #define SKL_REVID_C0		(0x2)
 #define SKL_REVID_D0		(0x3)
 #define SKL_REVID_E0		(0x4)
+#define SKL_REVID_F0		(0x5)
 
 #define BXT_REVID_A0		(0x0)
 #define BXT_REVID_B0		(0x3)
Signature · 6 lines
2.1.4

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Signature · 7 lines
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
author
#4 lore raw

PATCH 3/4 drm/i915/skl: enable WaDisableSbeCacheDispatchPortSharing

In reply to Imre Deak
Signed-off-by Imre Deak <[email protected]>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)
drivers/gpu/drm/i915/intel_ringbuffer.c +6 -7
index 461b9be..2e342db 100644
@@ -967,6 +967,12 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 		WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
 				  PIXEL_MASK_CAMMING_DISABLE);
 
+	/* WaDisableSbeCacheDispatchPortSharing:skl,bxt */
+	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_F0) ||
+	    (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_B0))
+		WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1,
+			       GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
+
 	return 0;
 }
 

@@ -1050,13 +1056,6 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
 	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 			  STALL_DOP_GATING_DISABLE);
 
-	/* WaDisableSbeCacheDispatchPortSharing:bxt */
-	if (INTEL_REVID(dev) <= BXT_REVID_B0) {
-		WA_SET_BIT_MASKED(
-			GEN7_HALF_SLICE_CHICKEN1,
-			GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
-	}
-
 	/* WaForceContextSaveRestoreNonCoherent:bxt */
 	WA_SET_BIT_MASKED(HDC_CHICKEN0,
 			  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
Signature · 6 lines
2.1.4

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
author
#5 lore raw

PATCH 4/4 drm/i915/skl: enable WaForceContextSaveRestoreNonCoherent

In reply to Imre Deak
Signed-off-by Imre Deak <[email protected]>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)
drivers/gpu/drm/i915/intel_ringbuffer.c +4 -4
index 2e342db..0d1522f 100644
@@ -973,6 +973,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 		WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1,
 			       GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
 
+	/* WaForceContextSaveRestoreNonCoherent:skl,bxt */
+	WA_SET_BIT_MASKED(HDC_CHICKEN0,
+			  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
+
 	return 0;
 }
 

@@ -1056,10 +1060,6 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
 	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 			  STALL_DOP_GATING_DISABLE);
 
-	/* WaForceContextSaveRestoreNonCoherent:bxt */
-	WA_SET_BIT_MASKED(HDC_CHICKEN0,
-			  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
-
 	return 0;
 }
Signature · 6 lines
2.1.4

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
#6 lore raw

Re: [PATCH 4/4] drm/i915/skl: enable WaForceContextSaveRestoreNonCoherent

Quoted 10 lines · Imre Deak
Signed-off-by Imre Deak <[email protected]>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)
drivers/gpu/drm/i915/intel_ringbuffer.c +0 -0
index 2e342db..0d1522f 100644

drivers/gpu/drm/i915/intel_ringbuffer.c static int gen9_init_workarounds(struct intel_engine_cs *ring) · line 979

Quoted 7 lines
drivers/gpu/drm/i915/intel_ringbuffer.c +4 -0
@@ -973,6 +973,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 		WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1,
 			       GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
 
+	/* WaForceContextSaveRestoreNonCoherent:skl,bxt */
+	WA_SET_BIT_MASKED(HDC_CHICKEN0,
+			  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
+

I think we need to also set bit 15 as it looks to be master switch for this bit.

-Mika

Quoted 21 lines
drivers/gpu/drm/i915/intel_ringbuffer.c +0 -4
 	return 0;
 }
 

@@ -1056,10 +1060,6 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
 	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 			  STALL_DOP_GATING_DISABLE);
 
-	/* WaForceContextSaveRestoreNonCoherent:bxt */
-	WA_SET_BIT_MASKED(HDC_CHICKEN0,
-			  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
-
 	return 0;
 }
Signature · 6 lines
2.1.4

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

author
#7 lore raw

Re: [PATCH 4/4] drm/i915/skl: enable WaForceContextSaveRestoreNonCoherent

Quoted 15 lines · Mika Kuoppala
Quoted 13 lines · Imre Deak
Signed-off-by Imre Deak <[email protected]>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)
drivers/gpu/drm/i915/intel_ringbuffer.c +0 -0
index 2e342db..0d1522f 100644
@@ -973,6 +973,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 		WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1,
 			       GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
Quoted 7 lines

drivers/gpu/drm/i915/intel_ringbuffer.c static int gen9_init_workarounds(struct intel_engine_cs *ring) · line 979

Quoted 4 lines
drivers/gpu/drm/i915/intel_ringbuffer.c +4 -0
+	/* WaForceContextSaveRestoreNonCoherent:skl,bxt */
+	WA_SET_BIT_MASKED(HDC_CHICKEN0,
+			  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
+

I think we need to also set bit 15 as it looks to be master switch for this bit.

Yes, thanks for catching it.

--Imre

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

author
#8 lore raw

PATCH 1/1 drm/i915/bxt: fix WaForceContextSaveRestoreNonCoherent on steppings B0+

In reply to Imre Deak

On B0 and C0 steppings the workaround enable bit would be overriden by default, so the overriding must be disabled.

The WA was added in
commit 83a24979c40ebbf0fa0cd14df16f74142f373cd3

Author: Nick Hoath <[email protected]>
Date:   Fri Apr 10 13:12:26 2015 +0100

drm/i915/bxt: Add WaForceContextSaveRestoreNonCoherent

Spotted-by Mika Kuoppala <[email protected]>
Signed-off-by Imre Deak <[email protected]>
---
 drivers/gpu/drm/i915/i915_reg.h         | 1 +
 drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++++--
 2 files changed, 6 insertions(+), 2 deletions(-)
drivers/gpu/drm/i915/i915_reg.h +1 -0
index 84af255..5afff3a 100644
@@ -5791,6 +5791,7 @@ enum skl_disp_power_wells {
 
 /* GEN8 chicken */
 #define HDC_CHICKEN0				0x7300
+#define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE	(1<<15)
 #define  HDC_FENCE_DEST_SLM_DISABLE		(1<<14)
 #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1<<11)
 #define  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT	(1<<5)
drivers/gpu/drm/i915/intel_ringbuffer.c +5 -2
index 2e342db..643fe89 100644
@@ -1049,6 +1049,7 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
 {
 	struct drm_device *dev = ring->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	uint32_t tmp;
 
 	gen9_init_workarounds(ring);
 

@@ -1057,8 +1058,10 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
 			  STALL_DOP_GATING_DISABLE);
 
 	/* WaForceContextSaveRestoreNonCoherent:bxt */
-	WA_SET_BIT_MASKED(HDC_CHICKEN0,
-			  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
+	tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
+	if (INTEL_REVID(dev) >= BXT_REVID_B0)
+		tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
+	WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
 
 	return 0;
 }
Signature · 6 lines
2.1.4

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
author
#9 lore raw

PATCH v2 4/4 drm/i915/skl: enable WaForceContextSaveRestoreNonCoherent

v2:
- set the override disable flag too on stepping F0 (mika)

Signed-off-by Imre Deak <[email protected]>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)
drivers/gpu/drm/i915/intel_ringbuffer.c +8 -7
index 643fe89..2472415 100644
@@ -918,6 +918,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 {
 	struct drm_device *dev = ring->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	uint32_t tmp;
 
 	/* WaDisablePartialInstShootdown:skl,bxt */
 	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,

@@ -973,6 +974,13 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 		WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1,
 			       GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
 
+	/* WaForceContextSaveRestoreNonCoherent:skl,bxt */
+	tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
+	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_F0) ||
+	    (IS_BROXTON(dev) && INTEL_REVID(dev) >= BXT_REVID_B0))
+		tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
+	WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
+
 	return 0;
 }
 

@@ -1049,7 +1057,6 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
 {
 	struct drm_device *dev = ring->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	uint32_t tmp;
 
 	gen9_init_workarounds(ring);
 

@@ -1057,12 +1064,6 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
 	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 			  STALL_DOP_GATING_DISABLE);
 
-	/* WaForceContextSaveRestoreNonCoherent:bxt */
-	tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
-	if (INTEL_REVID(dev) >= BXT_REVID_B0)
-		tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
-	WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
-
 	return 0;
 }
Signature · 6 lines
2.1.4

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Reviewed-by on v2 4/4
#10 lore raw

Re: [PATCH v2 4/4] drm/i915/skl: enable WaForceContextSaveRestoreNonCoherent

Quoted 4 lines · Imre Deak

v2:
- set the override disable flag too on stepping F0 (mika)

Signed-off-by Imre Deak <[email protected]>

[PATCH pre4/4] drm/i915/bxt: fix WaForceContextSaveRestoreNonCoherent on steppings B0+

And this patch,

Reviewed-by Mika Kuoppala <[email protected]>
Quoted 53 lines
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)
drivers/gpu/drm/i915/intel_ringbuffer.c +8 -7
index 643fe89..2472415 100644
@@ -918,6 +918,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 {
 	struct drm_device *dev = ring->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	uint32_t tmp;
 
 	/* WaDisablePartialInstShootdown:skl,bxt */
 	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,

@@ -973,6 +974,13 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 		WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1,
 			       GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
 
+	/* WaForceContextSaveRestoreNonCoherent:skl,bxt */
+	tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
+	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_F0) ||
+	    (IS_BROXTON(dev) && INTEL_REVID(dev) >= BXT_REVID_B0))
+		tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
+	WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
+
 	return 0;
 }
 

@@ -1049,7 +1057,6 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
 {
 	struct drm_device *dev = ring->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	uint32_t tmp;
 
 	gen9_init_workarounds(ring);
 

@@ -1057,12 +1064,6 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
 	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 			  STALL_DOP_GATING_DISABLE);
 
-	/* WaForceContextSaveRestoreNonCoherent:bxt */
-	tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
-	if (INTEL_REVID(dev) >= BXT_REVID_B0)
-		tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
-	WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
-
 	return 0;
 }
Signature · 1 line
2.1.4

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

#11 lore raw

Re: [PATCH v2 4/4] drm/i915/skl: enable WaForceContextSaveRestoreNonCoherent

Quoted 5 lines · Mika Kuoppala
Quoted 3 lines · Imre Deak

v2:
- set the override disable flag too on stepping F0 (mika)

Quoted 8 lines
Quoted 1 line
Signed-off-by Imre Deak <[email protected]>

[PATCH pre4/4] drm/i915/bxt: fix WaForceContextSaveRestoreNonCoherent on steppings B0+

And this patch,

Reviewed-by Mika Kuoppala <[email protected]>

Both applied, thanks.
-Daniel

Quoted 54 lines
Quoted 54 lines
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)
drivers/gpu/drm/i915/intel_ringbuffer.c +8 -7
index 643fe89..2472415 100644
@@ -918,6 +918,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 {
 	struct drm_device *dev = ring->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	uint32_t tmp;
 
 	/* WaDisablePartialInstShootdown:skl,bxt */
 	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,

@@ -973,6 +974,13 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 		WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1,
 			       GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
 
+	/* WaForceContextSaveRestoreNonCoherent:skl,bxt */
+	tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
+	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_F0) ||
+	    (IS_BROXTON(dev) && INTEL_REVID(dev) >= BXT_REVID_B0))
+		tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
+	WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
+
 	return 0;
 }
 

@@ -1049,7 +1057,6 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
 {
 	struct drm_device *dev = ring->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	uint32_t tmp;
 
 	gen9_init_workarounds(ring);
 

@@ -1057,12 +1064,6 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
 	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 			  STALL_DOP_GATING_DISABLE);
 
-	/* WaForceContextSaveRestoreNonCoherent:bxt */
-	tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
-	if (INTEL_REVID(dev) >= BXT_REVID_B0)
-		tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
-	WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
-
 	return 0;
 }
Signature · 1 line
2.1.4
Signature · 7 lines
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Tested-by on v1 4/4
#12 lore raw

Re: [PATCH 4/4] drm/i915/skl: enable WaForceContextSaveRestoreNonCoherent

In reply to Imre Deak
Tested-by Intel Graphics QA PRTS (Patch Regression Test System Contact: [email protected])

Task id: 6433 -------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied

PNV                                  234/234              234/234
ILK                                  262/262              262/262
SNB                 -1              282/282              281/282
IVB                                  300/300              300/300
BYT                                  254/254              254/254
BDW                                  275/275              275/275

-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
SNB igt@pm_rpm@dpms-mode-unset-non-lpsp DMESG_WARN(10)PASS(1) DMESG_WARN(1)
(dmesg patch applied)WARNING:at_drivers/gpu/drm/i915/intel_uncore.c:#assert_device_not_suspended[i915]()@WARNING:.* at .* assert_device_not_suspended+0x
Note: You need to pay more attention to line start with '*'
_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Reviewed-by on v1 1/4
#13 lore raw
In reply to Imre Deak
Quoted 16 lines · Imre Deak

Also make the WA comment consistent with the rest, where the stepping info is not shown.

Signed-off-by Imre Deak <[email protected]>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

[ The patchset is a follow-up to:
http://lists.freedesktop.org/archives/intel-gfx/2015-May/065989.html ]

drivers/gpu/drm/i915/intel_ringbuffer.c +0 -0
index 9b96ed7..461b9be 100644

drivers/gpu/drm/i915/intel_ringbuffer.c static int gen9_init_workarounds(struct intel_engine_cs *ring) · line 964

Quoted 10 lines
drivers/gpu/drm/i915/intel_ringbuffer.c +1 -6
@@ -961,12 +961,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 	WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 			  GEN9_CCS_TLB_PREFETCH_ENABLE);
 
-	/*
-	 * FIXME: don't apply the following on BXT for stepping C. On BXT A0
-	 * the flag reads back as 0.
-	 */
-	/* WaDisableMaskBasedCammingInRCC:sklC,bxtA */
-	if (INTEL_REVID(dev) == SKL_REVID_C0 || IS_BROXTON(dev))
+	/* WaDisableMaskBasedCammingInRCC:skl,bxt */

For the record, there seem to be some confusion in the W/A db:

- The W/A seems to have been renamed to WaDisablePixelMaskBasedCammingInRcpbe and indeed there's a bit to do that, but the bug in question talks about bit 14 of 7308, which is the disabling bit for the RCC unit
- The W/A isn't listed in the W/A db for BXT

In doubt, defaulting to trusting the spec and bug db is probably the saner option, so:

Reviewed-by Damien Lespiau <[email protected]>
Signature · 1 line
Damien
Quoted 12 lines
drivers/gpu/drm/i915/intel_ringbuffer.c +2 -0
+	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) ||
+	    (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0))
 		WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
 				  PIXEL_MASK_CAMMING_DISABLE);
Signature · 6 lines
2.1.4

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

#14 lore raw
Quoted 35 lines · Damien Lespiau
Quoted 16 lines · Imre Deak

Also make the WA comment consistent with the rest, where the stepping info is not shown.

Signed-off-by Imre Deak <[email protected]>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

[ The patchset is a follow-up to:
http://lists.freedesktop.org/archives/intel-gfx/2015-May/065989.html ]

drivers/gpu/drm/i915/intel_ringbuffer.c +0 -0
index 9b96ed7..461b9be 100644

drivers/gpu/drm/i915/intel_ringbuffer.c static int gen9_init_workarounds(struct intel_engine_cs *ring) · line 964

Quoted 10 lines
drivers/gpu/drm/i915/intel_ringbuffer.c +1 -6
@@ -961,12 +961,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 	WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 			  GEN9_CCS_TLB_PREFETCH_ENABLE);
 
-	/*
-	 * FIXME: don't apply the following on BXT for stepping C. On BXT A0
-	 * the flag reads back as 0.
-	 */
-	/* WaDisableMaskBasedCammingInRCC:sklC,bxtA */
-	if (INTEL_REVID(dev) == SKL_REVID_C0 || IS_BROXTON(dev))
+	/* WaDisableMaskBasedCammingInRCC:skl,bxt */

For the record, there seem to be some confusion in the W/A db:

- The W/A seems to have been renamed to WaDisablePixelMaskBasedCammingInRcpbe and indeed there's a bit to do that, but the bug in question talks about bit 14 of 7308, which is the disabling bit for the RCC unit
- The W/A isn't listed in the W/A db for BXT

Quoted 4 lines

In doubt, defaulting to trusting the spec and bug db is probably the saner option, so:

Reviewed-by Damien Lespiau <[email protected]>

Spoke too soon. This register is in the render context so has to be written from the ring...

Signature · 5 lines
Damien
_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
author
#15 lore raw
Quoted 36 lines · Damien Lespiau
Quoted 35 lines · Damien Lespiau
Quoted 16 lines · Imre Deak

Also make the WA comment consistent with the rest, where the stepping info is not shown.

Signed-off-by Imre Deak <[email protected]>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

[ The patchset is a follow-up to:
http://lists.freedesktop.org/archives/intel-gfx/2015-May/065989.html ]

drivers/gpu/drm/i915/intel_ringbuffer.c +0 -0
index 9b96ed7..461b9be 100644

drivers/gpu/drm/i915/intel_ringbuffer.c static int gen9_init_workarounds(struct intel_engine_cs *ring) · line 964

Quoted 10 lines
drivers/gpu/drm/i915/intel_ringbuffer.c +1 -6
@@ -961,12 +961,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 	WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 			  GEN9_CCS_TLB_PREFETCH_ENABLE);
 
-	/*
-	 * FIXME: don't apply the following on BXT for stepping C. On BXT A0
-	 * the flag reads back as 0.
-	 */
-	/* WaDisableMaskBasedCammingInRCC:sklC,bxtA */
-	if (INTEL_REVID(dev) == SKL_REVID_C0 || IS_BROXTON(dev))
+	/* WaDisableMaskBasedCammingInRCC:skl,bxt */

For the record, there seem to be some confusion in the W/A db:

- The W/A seems to have been renamed to WaDisablePixelMaskBasedCammingInRcpbe and indeed there's a bit to do that, but the bug in question talks about bit 14 of 7308, which is the disabling bit for the RCC unit
- The W/A isn't listed in the W/A db for BXT

Quoted 7 lines
Quoted 4 lines

In doubt, defaulting to trusting the spec and bug db is probably the saner option, so:

Reviewed-by Damien Lespiau <[email protected]>

Spoke too soon. This register is in the render context so has to be written from the ring...

Not sure what you mean. I thought all WAs inited here are written from the ring.

--Imre

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Reviewed-by
#16 lore raw
Quoted 40 lines · Imre Deak
Quoted 39 lines · Damien Lespiau
Quoted 38 lines · Damien Lespiau
Quoted 16 lines · Imre Deak

Also make the WA comment consistent with the rest, where the stepping info is not shown.

Signed-off-by Imre Deak <[email protected]>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

[ The patchset is a follow-up to:
http://lists.freedesktop.org/archives/intel-gfx/2015-May/065989.html ]

drivers/gpu/drm/i915/intel_ringbuffer.c +0 -0
index 9b96ed7..461b9be 100644

drivers/gpu/drm/i915/intel_ringbuffer.c static int gen9_init_workarounds(struct intel_engine_cs *ring) · line 964

Quoted 10 lines
drivers/gpu/drm/i915/intel_ringbuffer.c +1 -6
@@ -961,12 +961,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 	WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 			  GEN9_CCS_TLB_PREFETCH_ENABLE);
 
-	/*
-	 * FIXME: don't apply the following on BXT for stepping C. On BXT A0
-	 * the flag reads back as 0.
-	 */
-	/* WaDisableMaskBasedCammingInRCC:sklC,bxtA */
-	if (INTEL_REVID(dev) == SKL_REVID_C0 || IS_BROXTON(dev))
+	/* WaDisableMaskBasedCammingInRCC:skl,bxt */

For the record, there seem to be some confusion in the W/A db:

- The W/A seems to have been renamed to WaDisablePixelMaskBasedCammingInRcpbe and indeed there's a bit to do that, but the bug in question talks about bit 14 of 7308, which is the disabling bit for the RCC unit
- The W/A isn't listed in the W/A db for BXT

In doubt, defaulting to trusting the spec and bug db is probably the saner option, so:

Quoted 7 lines
Quoted 4 lines
Quoted 1 line
Reviewed-by Damien Lespiau <[email protected]>

Spoke too soon. This register is in the render context so has to be written from the ring...

Not sure what you mean. I thought all WAs inited here are written from the ring.

Oh, yes, excellent! r-b restored!

Reviewed-by Damien Lespiau <[email protected]>
Signature · 5 lines
Damien
_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx