i2c: brcmstb: Add Broadcom settop SoC i2c controller driver

Adding support for i2c controller driver for Broadcom settop SoCs.

---
- added COMPILE_TEST dependency to CONFIG_I2C_BRCMSTB
- alphabetically ordered delay.h before device.h
- disabled l2 interrupt on a timeout
- removed redundant white spaces
- call brcmstb_i2c_set_bsc_reg_defaults()
before calling i2c_add_adapter()
- removed kfree(dev->bsc_regmap) since using devm_kzalloc() for bsc_regmap

---
 drivers/i2c/busses/Kconfig       |  10 +
 drivers/i2c/busses/Makefile      |   1 +
 drivers/i2c/busses/i2c-brcmstb.c | 697 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 708 insertions(+)
 create mode 100644 drivers/i2c/busses/i2c-brcmstb.c

index 2255af2..c35903a 100644
@@ -392,6 +392,16 @@ config I2C_BCM_KONA
 
 	  If you do not need KONA I2C interface, say N.
 
+config I2C_BRCMSTB
+	tristate "BRCM Settop I2C controller"
+	depends on ARCH_BRCMSTB || COMPILE_TEST
+	default y
+	help
+	  If you say yes to this option, support will be included for the
+	  I2C interface on the Broadcom Settop SoCs.
+
+	  If you do not need I2C interface, say N.
+
 config I2C_BLACKFIN_TWI
 	tristate "Blackfin TWI I2C support"
 	depends on BLACKFIN

index cdf941d..aedea68 100644
@@ -105,6 +105,7 @@ obj-$(CONFIG_I2C_VIPERBOARD)	+= i2c-viperboard.o
 # Other I2C/SMBus bus drivers
 obj-$(CONFIG_I2C_ACORN)		+= i2c-acorn.o
 obj-$(CONFIG_I2C_BCM_KONA)	+= i2c-bcm-kona.o
+obj-$(CONFIG_I2C_BRCMSTB)	+= i2c-brcmstb.o
 obj-$(CONFIG_I2C_CROS_EC_TUNNEL)	+= i2c-cros-ec-tunnel.o
 obj-$(CONFIG_I2C_ELEKTOR)	+= i2c-elektor.o
 obj-$(CONFIG_I2C_OPAL)		+= i2c-opal.o

2.3.2

i2c Device tree binding documentation for brcmstb
SoCs.

---
 .../devicetree/bindings/i2c/i2c-brcmstb.txt        | 28 ++++++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-brcmstb.txt

new file mode 100644
index 0000000..d6f724e
@@ -0,0 +1,28 @@
+Broadcom stb bsc iic master controller
+
+Required properties:
+
+- compatible: should be "brcm,brcmstb-i2c"
+- clock-frequency: 32-bit decimal value of iic master clock freqency in Hz
+		   valid values are 375000, 390000, 187500, 200000
+		   93750, 97500, 46875 and 50000
+- reg: specifies the base physical address and size of the registers
+
+Optional properties :
+
+- interrupt-parent: specifies the phandle to the parent interrupt controller
+  this one is cascaded from
+- interrupts: specifies the interrupt number, the irq line to be used
+- interrupt-names: Interrupt name string
+
+Example:
+
+bsca: i2c@f0406200 {
+      clock-frequency = <390000>;
+      compatible = "brcm,brcmstb-i2c";
+      interrupt-parent = <&irq0_intc>;
+      reg = <0xf0406200 0x58>;
+      interrupts = <0x18>;
+      interrupt-names = "upg_bsca";
+};
+

2.3.2

Hi Kamal,

There's one change still missing (that I mentioned when reviewing v2 of the patchset):

What is the max len that can be supported? BSC_CNT_REG1_MASK = 63? Then you should check against that.

Note Wolfram has introduced a way to validate the supported data length at the i2c-core, which you should adapt:

commit b7f625840267b18ef1011cba0085bb7e237d76f7

Author: Wolfram Sang <wsa-z923LK4zBo2bacvFa/[email protected]>
Date:   Mon Jan 5 23:45:59 2015 +0100

i2c: add quirk checks to core

Let the core do the checks if HW quirks prevent a transfer. Saves code from drivers and adds consistency.
<<<

So you should add struct i2c_adapter_quirks and set the max_read_len and max_write_len.

I have no more comment for the rest of the code.

Thanks,

Ray

Ray,

I am using non combined operation so it not necessary have limit. I am not sending a stop condition till the last byte is written or read. So if the xfer has more than the i2c buffer len we break up the transfers after the initial salve address write into max read/write data buffer size.

Thanks
Kamal

Okay, Kamal. I got it. Thanks for the explanation.

Wolfram, I have no more comment on this patch.

Thanks,

Ray

We are very close.