sunxi: Allwinner A80 SoC support

index 30ec4ac..8e8c84f 100644
@@ -78,18 +78,16 @@ int print_cpuinfo(void)
 
 int sunxi_get_sid(unsigned int *sid)
 {
-#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_A23
 #ifdef CONFIG_AXP221_POWER
 	return axp221_get_sid(sid);
-#else
-	return -ENODEV;
-#endif
-#else
+#elif defined SUNXI_SID_BASE
 	int i;
 
 	for (i = 0; i< 4; i++)
 		sid[i] = readl(SUNXI_SID_BASE + 4 * i);
 
 	return 0;
+#else
+	return -ENODEV;
 #endif
 }

index e6730c0..75ce7b5 100644
@@ -120,13 +120,6 @@ void s_init(void)
  */
 u32 spl_boot_device(void)
 {
-#ifdef CONFIG_SPL_FEL
-	/*
-	 * This is the legacy compile time configuration for a special FEL
-	 * enabled build. It has many restrictions and can only boot over USB.
-	 */
-	return BOOT_DEVICE_BOARD;
-#else
 	/*
 	 * When booting from the SD card, the "eGON.BT0" signature is expected
 	 * to be found in memory at the address 0x0004 (see the "mksunxiboot"

@@ -147,7 +140,6 @@ u32 spl_boot_device(void)
 		return BOOT_DEVICE_MMC1;
 	else
 		return BOOT_DEVICE_BOARD;
-#endif
 }
 
 /* No confirmation data available in SPL yet. Hardcode bootmode */

index d829899..5dd2480 100644
@@ -162,13 +162,6 @@
 
 #define CONFIG_SPL_BOARD_LOAD_IMAGE
 
-#ifdef CONFIG_SPL_FEL
-
-#define CONFIG_SPL_TEXT_BASE		0x2000
-#define CONFIG_SPL_MAX_SIZE		0x4000		/* 16 KiB */
-
-#else /* CONFIG_SPL */
-
 #define CONFIG_SPL_BSS_START_ADDR	0x4ff80000
 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KiB */
 

@@ -186,8 +179,6 @@
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	80	/* 40KiB */
 #define CONFIG_SPL_PAD_TO		32768		/* decimal for 'dd' */
 
-#endif /* CONFIG_SPL */
-
 /* end of 32 KiB in sram */
 #define LOW_LEVEL_SRAM_STACK		0x00008000 /* End of sram */
 #define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK

index 5dd2480..2b90681 100644
@@ -13,6 +13,8 @@
 #ifndef _SUNXI_COMMON_CONFIG_H
 #define _SUNXI_COMMON_CONFIG_H
 
+#include <linux/stringify.h>
+
 #ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT
 /*
  * The U-Boot workarounds bugs in the outdated buggy sunxi-3.4 kernels at the

@@ -39,8 +41,6 @@
 
 #include <asm/arch/cpu.h>	/* get chip and board defs */
 
-#define CONFIG_SYS_TEXT_BASE		0x4a000000
-
 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM_SERIAL)
 # define CONFIG_DW_SERIAL
 #endif

@@ -69,8 +69,34 @@
 /* CPU */
 #define CONFIG_SYS_CACHELINE_SIZE	64
 
-/* DRAM Base */
+/*
+ * The DRAM Base differs between some models. We cannot use macros for the
+ * CONFIG_FOO defines which contain the DRAM base address since they end
+ * up unexpanded in include/autoconf.mk .
+ *
+ * So we have to have this #ifdef #else #endif block for these.
+ */
+#ifdef CONFIG_MACH_SUN9I
+#define SDRAM_OFFSET(x) 0x2##x
+#define CONFIG_SYS_SDRAM_BASE		0x20000000
+#define CONFIG_SYS_LOAD_ADDR		0x22000000 /* default load address */
+#define CONFIG_SYS_TEXT_BASE		0x2a000000
+#define CONFIG_PRE_CON_BUF_ADDR		0x2f000000
+#define CONFIG_SYS_SPL_MALLOC_START	0x2ff00000
+#define CONFIG_SPL_BSS_START_ADDR	0x2ff80000
+#else
+#define SDRAM_OFFSET(x) 0x4##x
 #define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_LOAD_ADDR		0x42000000 /* default load address */
+#define CONFIG_SYS_TEXT_BASE		0x4a000000
+#define CONFIG_PRE_CON_BUF_ADDR		0x4f000000
+#define CONFIG_SYS_SPL_MALLOC_START	0x4ff00000
+#define CONFIG_SPL_BSS_START_ADDR	0x4ff80000
+#endif
+
+#define CONFIG_SPL_BSS_MAX_SIZE		0x00080000 /* 512 KiB */
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00080000 /* 512 KiB */
+
 #define CONFIG_SYS_INIT_RAM_ADDR	0x0
 #define CONFIG_SYS_INIT_RAM_SIZE	0x8000	/* 32 KiB */
 

@@ -129,10 +155,8 @@
 /* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 
-#define CONFIG_SYS_LOAD_ADDR		0x42000000 /* default load address */
-
 /* standalone support */
-#define CONFIG_STANDALONE_LOAD_ADDR	0x42000000
+#define CONFIG_STANDALONE_LOAD_ADDR	CONFIG_SYS_LOAD_ADDR
 
 /* baudrate */
 #define CONFIG_BAUDRATE			115200

@@ -162,9 +186,6 @@
 
 #define CONFIG_SPL_BOARD_LOAD_IMAGE
 
-#define CONFIG_SPL_BSS_START_ADDR	0x4ff80000
-#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KiB */
-
 #define CONFIG_SPL_TEXT_BASE		0x20		/* sram start+header */
 #define CONFIG_SPL_MAX_SIZE		0x5fe0		/* 24KB on sun4i/sun7i */
 

@@ -182,8 +203,6 @@
 /* end of 32 KiB in sram */
 #define LOW_LEVEL_SRAM_STACK		0x00008000 /* End of sram */
 #define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
-#define CONFIG_SYS_SPL_MALLOC_START	0x4ff00000
-#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00080000	/* 512 KiB */
 
 /* I2C */
 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER

@@ -333,8 +352,6 @@ extern int soft_i2c_gpio_scl;
 /* Enable pre-console buffer to get complete log on the VGA console */
 #define CONFIG_PRE_CONSOLE_BUFFER
 #define CONFIG_PRE_CON_BUF_SZ		4096 /* Aprox 2 80*25 screens */
-/* Use the room between the end of bootm_size and the framebuffer */
-#define CONFIG_PRE_CON_BUF_ADDR		0x4f000000
 
 /*
  * 240M RAM (256M minimum minus space for the framebuffer),

@@ -343,11 +360,11 @@ extern int soft_i2c_gpio_scl;
  */
 #define MEM_LAYOUT_ENV_SETTINGS \
 	"bootm_size=0xf000000\0" \
-	"kernel_addr_r=0x42000000\0" \
-	"fdt_addr_r=0x43000000\0" \
-	"scriptaddr=0x43100000\0" \
-	"pxefile_addr_r=0x43200000\0" \
-	"ramdisk_addr_r=0x43300000\0"
+	"kernel_addr_r=" __stringify(SDRAM_OFFSET(2000000)) "\0" \
+	"fdt_addr_r=" __stringify(SDRAM_OFFSET(3000000)) "\0" \
+	"scriptaddr=" __stringify(SDRAM_OFFSET(3100000)) "\0" \
+	"pxefile_addr_r=" __stringify(SDRAM_OFFSET(3200000)) "\0" \
+	"ramdisk_addr_r=" __stringify(SDRAM_OFFSET(3300000)) "\0"
 
 #ifdef CONFIG_MMC
 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)

index 2b90681..76f42f5 100644
@@ -97,8 +97,20 @@
 #define CONFIG_SPL_BSS_MAX_SIZE		0x00080000 /* 512 KiB */
 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x00080000 /* 512 KiB */
 
+#ifdef CONFIG_MACH_SUN9I
+/*
+ * The A80's A1 sram starts at 0x00010000 rather then at 0x00000000 and is
+ * slightly bigger. Note that it is possible to map the first 32 KiB of the
+ * A1 at 0x00000000 like with older SoCs by writing 0x16aa0001 to the
+ * undocumented 0x008000e0 SYS_CTRL register. Where the 16aa is a key and
+ * the 1 actually activates the mapping of the first 32 KiB to 0x00000000.
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x10000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x0a000	/* 40 KiB */
+#else
 #define CONFIG_SYS_INIT_RAM_ADDR	0x0
 #define CONFIG_SYS_INIT_RAM_SIZE	0x8000	/* 32 KiB */
+#endif
 
 #define CONFIG_SYS_INIT_SP_OFFSET \
 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

index 75ce7b5..23aa249 100644
@@ -64,6 +64,10 @@ static int gpio_init(void)
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
 	sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
+	sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
 	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);

index 8e8c84f..a276fad 100644
@@ -11,6 +11,7 @@
 #include <asm/arch/cpu.h>
 #include <asm/arch/clock.h>
 #include <axp221.h>
+#include <errno.h>
 
 #ifdef CONFIG_MACH_SUN6I
 int sunxi_get_ss_bonding_id(void)

@@ -68,6 +69,8 @@ int print_cpuinfo(void)
 	puts("CPU:   Allwinner A23 (SUN8I)\n");
 #elif defined CONFIG_MACH_SUN8I_A33
 	puts("CPU:   Allwinner A33 (SUN8I)\n");
+#elif defined CONFIG_MACH_SUN9I
+	puts("CPU:   Allwinner A80 (SUN9I)\n");
 #else
 #warning Please update cpu_info.c with correct CPU information
 	puts("CPU:   SUNXI Family\n");

index 148123a..496295d 100644
@@ -185,6 +185,7 @@ enum sunxi_gpio_number {
 #define SUN8I_GPH_TWI1		2
 #define SUN6I_GPH_TWI2		2
 #define SUN6I_GPH_UART0		2
+#define SUN9I_GPH_UART0		2
 
 #define SUNXI_GPI_SDC3		2
 #define SUN7I_GPI_TWI3		3

index 5f79cc1..ed60e74 100644
@@ -530,10 +530,11 @@ int misc_init_r(void)
 		}
 	}
 
+#ifndef CONFIG_MACH_SUN9I
 	ret = sunxi_usb_phy_probe();
 	if (ret)
 		return ret;
-
+#endif
 #if defined(CONFIG_MUSB_HOST) || defined(CONFIG_MUSB_GADGET)
 	musb_register(&musb_plat, NULL, (void *)SUNXI_USB0_BASE);
 #endif

new file mode 100644
index 0000000..cd9e08d
@@ -0,0 +1,21 @@
+/*
+ * (C) Copyright 2015 Hans de Goede <[email protected]>
+ *
+ * Configuration settings for the Allwinner A80 (sun9i) CPU
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * A80 specific configuration
+ */
+
+/*
+ * Include common sunxi configuration where most the settings are
+ */
+#include <configs/sunxi-common.h>
+
+#endif /* __CONFIG_H */