Clk drivers for NXP LPC18xx family
Subsystems (3)
v4 cover Clk drivers for NXP LPC18xx family
This patch set adds support for the two main clock peripherals in the LPC18xx/43xx MCU family.
The Clock Generation Unit (CGU) is the base source of all clocks. It has five external inputs and contains PLLs, dividers and muxes. The outputs from the CGU are then routed to a Clock Control Unit (CCU) and a few peripherals directly. There are two CCUs in the MCU. The CCU is a collection of gates and a few dividers that sits between the CGU and most of the peripherals. These clock drivers are needed by the timer at early boot so both are using CLK_OF_DECLARE.
Which clocks that are available depends on the specific device and it's peripherals. It's possible in DT to setup the routing between the CGU and the CCUs.
The biggest change in v4 is the way parent names for CCU clocks are stored and how clock branches are selected for registration in the CCU driver.
* Parent clock names are now stored together with branch name in the clk_branches[] table.
* Selection of which branch clock to register on the two CCU instances is determined by the 'clock-names' property. If a clock name matches with the parent name in the clk_branches[] table that branch clock is registered on the CCU.
Alternativly the clk_branches[] table could be split between the CCUs, but there would still be a need to identify the CCU instance. For example by using different compatability stings in DT or adding an id property to DT.
I belive the best solution is to let the driver decide which branch clocks to register based on the clock routing information already provided in DT. As mentioned above this is now done by using the 'clock-names' property and matching strings in the clk_branches[] table.
Clock tree can be found here: http://slexy.org/raw/s2I3bIFJxg
Changes since v3:
- put CCU parent clock names directly in clk_branches[] table
- use 'clock-names' property to find figure out which branch clocks to register in CCU driver as oppose to clk id
- remove CCU clock list from doc and refer to lpc18xx-ccu.h
- remove patch with of_clk_get_index
Changes since v2:
- use 'clock-controller' as node name in doc
- add patch with of_clk_get_index function
- drop 'clock-indices' and 'clock-output-names' from cgu node
- move base clock names into cgu driver
- use of_clk_get/__clk_get_name in ccu to get parent name for composite clocks.
- other misc fixes to ccu driver and cgu doc
Changes since v1:
- reorganize cgu clk structs
- macros to create cgu clk structs
- move drivers to nxp subdir
- rebase on v4.1-rc1
The last patch (dts changes) are only included in this patch set for illustration purposes. DTS changes will be sent separately to the ARM SoC team later.
Base support for LPC18xx is now in arm-soc next. Pinctrl, gpio, reset and ethernet drivers are also upstream.
Joachim Eastwood (5):
clk: add lpc18xx cgu clk driver
doc: dt: add documentation for lpc1850-cgu clk driver
clk: add lpc18xx ccu clk driver
doc: dt: add documentation for lpc1850-ccu clk driver
ARM: dts: lpc18xx: add clock nodes for cgu and ccu
.../devicetree/bindings/clock/lpc1850-ccu.txt | 77 +++ .../devicetree/bindings/clock/lpc1850-cgu.txt | 131 +++++ arch/arm/boot/dts/lpc18xx.dtsi | 85 ++- arch/arm/boot/dts/lpc4350-hitex-eval.dts | 4 - drivers/clk/Makefile | 1 + drivers/clk/nxp/Makefile | 2 + drivers/clk/nxp/clk-lpc18xx-ccu.c | 293 ++++++++++ drivers/clk/nxp/clk-lpc18xx-cgu.c | 635 +++++++++++++++++++++ include/dt-bindings/clock/lpc18xx-ccu.h | 74 +++ include/dt-bindings/clock/lpc18xx-cgu.h | 41 ++ 10 files changed, 1325 insertions(+), 18 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/lpc1850-ccu.txt create mode 100644 Documentation/devicetree/bindings/clock/lpc1850-cgu.txt create mode 100644 drivers/clk/nxp/Makefile create mode 100644 drivers/clk/nxp/clk-lpc18xx-ccu.c create mode 100644 drivers/clk/nxp/clk-lpc18xx-cgu.c create mode 100644 include/dt-bindings/clock/lpc18xx-ccu.h create mode 100644 include/dt-bindings/clock/lpc18xx-cgu.h
Signature · 1 line
1.8.0
PATCH v4 1/5 clk: add lpc18xx cgu clk driver
Add driver for NXP LPC18xx/43xx Clock Generation Unit (CGU). The CGU contains several clock generators and output stages that route the clocks either directly to peripherals or to a Clock Control Unit (CCU).
--- drivers/clk/Makefile | 1 + drivers/clk/nxp/Makefile | 1 + drivers/clk/nxp/clk-lpc18xx-cgu.c | 635 ++++++++++++++++++++++++++++++++ include/dt-bindings/clock/lpc18xx-cgu.h | 41 +++ 4 files changed, 678 insertions(+) create mode 100644 drivers/clk/nxp/Makefile create mode 100644 drivers/clk/nxp/clk-lpc18xx-cgu.c create mode 100644 include/dt-bindings/clock/lpc18xx-cgu.h
drivers/clk/Makefile +1 -0
@@ -56,6 +56,7 @@ obj-$(CONFIG_ARCH_MMP) += mmp/ endif obj-$(CONFIG_PLAT_ORION) += mvebu/ obj-$(CONFIG_ARCH_MXS) += mxs/ +obj-$(CONFIG_ARCH_LPC18XX) += nxp/ obj-$(CONFIG_MACH_PISTACHIO) += pistachio/ obj-$(CONFIG_COMMON_CLK_PXA) += pxa/ obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/
drivers/clk/nxp/Makefile new file +1 -0
@@ -0,0 +1 @@ +obj-$(CONFIG_ARCH_LPC18XX) += clk-lpc18xx-cgu.o
drivers/clk/nxp/clk-lpc18xx-cgu.c new file +635 -0
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include/dt-bindings/clock/lpc18xx-cgu.h new file +41 -0
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Signature · 1 line
1.8.0
PATCH v4 2/5 doc: dt: add documentation for lpc1850-cgu clk driver
In reply to Joachim EastwoodAdd DT binding documentation for lpc1850-cgu driver.
--- .../devicetree/bindings/clock/lpc1850-cgu.txt | 131 +++++++++++++++++++++ 1 file changed, 131 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/lpc1850-cgu.txt
Documentation/devicetree/bindings/clock/lpc1850-cgu.txt new file +131 -0
@@ -0,0 +1,131 @@ +* NXP LPC1850 Clock Generation Unit (CGU) + +The CGU generates multiple independent clocks for the core and the +peripheral blocks of the LPC18xx. Each independent clock is called +a base clock and itself is one of the inputs to the two Clock +Control Units (CCUs) which control the branch clocks to the +individual peripherals. + +The CGU selects the inputs to the clock generators from multiple +clock sources, controls the clock generation, and routes the outputs +of the clock generators through the clock source bus to the output +stages. Each output stage provides an independent clock source and +corresponds to one of the base clocks for the LPC18xx. + + - Above text taken from NXP LPC1850 User Manual. + + +This binding uses the common clock binding: + Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible: + Should be "nxp,lpc1850-cgu" +- reg: + Shall define the base and range of the address space + containing clock control registers +- #clock-cells: + Shall have value <1>. The permitted clock-specifier values + are the base clock numbers defined below. +- clocks: + Shall contain a list of phandles for the external input + sources to the CGU. The list shall be in the following + order: xtal, 32khz, enet_rx_clk, enet_tx_clk, gp_clkin. +- clock-indices: + Shall be an ordered list of numbers defining the base clock + number provided by the CGU. +- clock-output-names: + Shall be an ordered list of strings defining the names of + the clocks provided by the CGU. + +Which base clocks that are available on the CGU depends on the +specific LPC part. Base clocks are numbered from 0 to 27. + +Number: Name: Description: + 0 BASE_SAFE_CLK Base safe clock (always on) for WWDT + 1 BASE_USB0_CLK Base clock for USB0 + 2 BASE_PERIPH_CLK Base clock for Cortex-M0SUB subsystem, + SPI, and SGPIO + 3 BASE_USB1_CLK Base clock for USB1 + 4 BASE_CPU_CLK System base clock for ARM Cortex-M core + and APB peripheral blocks #0 and #2 + 5 BASE_SPIFI_CLK Base clock for SPIFI + 6 BASE_SPI_CLK Base clock for SPI + 7 BASE_PHY_RX_CLK Base clock for Ethernet PHY Receive clock + 8 BASE_PHY_TX_CLK Base clock for Ethernet PHY Transmit clock + 9 BASE_APB1_CLK Base clock for APB peripheral block # 1 +10 BASE_APB3_CLK Base clock for APB peripheral block # 3 +11 BASE_LCD_CLK Base clock for LCD +12 BASE_ADCHS_CLK Base clock for ADCHS +13 BASE_SDIO_CLK Base clock for SD/MMC +14 BASE_SSP0_CLK Base clock for SSP0 +15 BASE_SSP1_CLK Base clock for SSP1 +16 BASE_UART0_CLK Base clock for UART0 +17 BASE_UART1_CLK Base clock for UART1 +18 BASE_UART2_CLK Base clock for UART2 +19 BASE_UART3_CLK Base clock for UART3 +20 BASE_OUT_CLK Base clock for CLKOUT pin +24-21 - Reserved +25 BASE_AUDIO_CLK Base clock for audio system (I2S) +26 BASE_CGU_OUT0_CLK Base clock for CGU_OUT0 clock output +27 BASE_CGU_OUT1_CLK Base clock for CGU_OUT1 clock output + +BASE_PERIPH_CLK and BASE_SPI_CLK is only available on LPC43xx. +BASE_ADCHS_CLK is only available on LPC4370. + + +Example board file: + +/ { + clocks { + xtal: xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + + xtal32: xtal32 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + enet_rx_clk: enet_rx_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "enet_rx_clk"; + }; + + enet_tx_clk: enet_tx_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "enet_tx_clk"; + }; + + gp_clkin: gp_clkin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "gp_clkin"; + }; + }; + + soc { + cgu: clock-controller at 40050000 { + compatible = "nxp,lpc1850-cgu"; + reg = <0x40050000 0x1000>; + #clock-cells = <1>; + clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>; + }; + + /* A CGU and CCU clock consumer */ + lcdc: lcdc at 40008000 { + ... + clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>; + clock-names = "clcdclk", "apb_pclk"; + ... + }; + }; +};
Signature · 1 line
1.8.0
PATCH v4 3/5 clk: add lpc18xx ccu clk driver
In reply to Joachim EastwoodAdd driver for NXP LPC18xx/43xx Clock Control Unit (CCU). The CCU provides fine grained gating of most clocks present in the SoC.
--- drivers/clk/nxp/Makefile | 1 + drivers/clk/nxp/clk-lpc18xx-ccu.c | 293 ++++++++++++++++++++++++++++++++ include/dt-bindings/clock/lpc18xx-ccu.h | 74 ++++++++ 3 files changed, 368 insertions(+) create mode 100644 drivers/clk/nxp/clk-lpc18xx-ccu.c create mode 100644 include/dt-bindings/clock/lpc18xx-ccu.h
drivers/clk/nxp/Makefile +1 -0
@@ -1 +1,2 @@ obj-$(CONFIG_ARCH_LPC18XX) += clk-lpc18xx-cgu.o +obj-$(CONFIG_ARCH_LPC18XX) += clk-lpc18xx-ccu.o
drivers/clk/nxp/clk-lpc18xx-ccu.c new file +293 -0
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include/dt-bindings/clock/lpc18xx-ccu.h new file +74 -0
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Signature · 1 line
1.8.0
PATCH v4 3/5 clk: add lpc18xx ccu clk driver
Quoting Joachim Eastwood (2015-05-28 13:31:45)
Quoted 58 lines
drivers/clk/nxp/clk-lpc18xx-ccu.c new file +58
-0+static struct lpc18xx_clk_branch clk_branches[] = { + {"base_apb3_clk" ,"apb3_bus" ,CLK_APB3_BUS ,CCU_BRANCH_IS_BUS }, + {"base_apb3_clk" ,"apb3_i2c1" ,CLK_APB3_I2C1 ,0 }, + {"base_apb3_clk" ,"apb3_dac" ,CLK_APB3_DAC ,0 }, + {"base_apb3_clk" ,"apb3_adc0" ,CLK_APB3_ADC0 ,0 }, + {"base_apb3_clk" ,"apb3_adc1" ,CLK_APB3_ADC1 ,0 }, + {"base_apb3_clk" ,"apb3_can0" ,CLK_APB3_CAN0 ,0 }, + + {"base_apb1_clk" ,"apb1_bus" ,CLK_APB1_BUS ,CCU_BRANCH_IS_BUS }, + {"base_apb1_clk" ,"apb1_mc_pwm" ,CLK_APB1_MOTOCON_PWM ,0 }, + {"base_apb1_clk" ,"apb1_i2c0" ,CLK_APB1_I2C0 ,0 }, + {"base_apb1_clk" ,"apb1_i2s" ,CLK_APB1_I2S ,0 }, + {"base_apb1_clk" ,"apb1_can1" ,CLK_APB1_CAN1 ,0 }, + + {"base_spifi_clk" ,"spifi" ,CLK_SPIFI ,0 }, + + {"base_cpu_clk" ,"cpu_bus" ,CLK_CPU_BUS ,CCU_BRANCH_IS_BUS }, + {"base_cpu_clk" ,"cpu_spifi" ,CLK_CPU_SPIFI ,0 }, + {"base_cpu_clk" ,"cpu_gpio" ,CLK_CPU_GPIO ,0 }, + {"base_cpu_clk" ,"cpu_lcd" ,CLK_CPU_LCD ,0 }, + {"base_cpu_clk" ,"cpu_ethernet" ,CLK_CPU_ETHERNET ,0 }, + {"base_cpu_clk" ,"cpu_usb0" ,CLK_CPU_USB0 ,0 }, + {"base_cpu_clk" ,"cpu_emc" ,CLK_CPU_EMC ,0 }, + {"base_cpu_clk" ,"cpu_sdio" ,CLK_CPU_SDIO ,0 }, + {"base_cpu_clk" ,"cpu_dma" ,CLK_CPU_DMA ,0 }, + {"base_cpu_clk" ,"cpu_core" ,CLK_CPU_CORE ,0 }, + {"base_cpu_clk" ,"cpu_sct" ,CLK_CPU_SCT ,0 }, + {"base_cpu_clk" ,"cpu_usb1" ,CLK_CPU_USB1 ,0 }, + {"base_cpu_clk" ,"cpu_emcdiv" ,CLK_CPU_EMCDIV ,CCU_BRANCH_HAVE_DIV2 }, + {"base_cpu_clk" ,"cpu_flasha" ,CLK_CPU_FLASHA ,CCU_BRANCH_HAVE_DIV2 }, + {"base_cpu_clk" ,"cpu_flashb" ,CLK_CPU_FLASHB ,CCU_BRANCH_HAVE_DIV2 }, + {"base_cpu_clk" ,"cpu_m0app" ,CLK_CPU_M0APP ,CCU_BRANCH_HAVE_DIV2 }, + {"base_cpu_clk" ,"cpu_adchs" ,CLK_CPU_ADCHS ,CCU_BRANCH_HAVE_DIV2 }, + {"base_cpu_clk" ,"cpu_eeprom" ,CLK_CPU_EEPROM ,CCU_BRANCH_HAVE_DIV2 }, + {"base_cpu_clk" ,"cpu_wwdt" ,CLK_CPU_WWDT ,0 }, + {"base_cpu_clk" ,"cpu_uart0" ,CLK_CPU_UART0 ,0 }, + {"base_cpu_clk" ,"cpu_uart1" ,CLK_CPU_UART1 ,0 }, + {"base_cpu_clk" ,"cpu_ssp0" ,CLK_CPU_SSP0 ,0 }, + {"base_cpu_clk" ,"cpu_timer0" ,CLK_CPU_TIMER0 ,0 }, + {"base_cpu_clk" ,"cpu_timer1" ,CLK_CPU_TIMER1 ,0 }, + {"base_cpu_clk" ,"cpu_scu" ,CLK_CPU_SCU ,0 }, + {"base_cpu_clk" ,"cpu_creg" ,CLK_CPU_CREG ,0 }, + {"base_cpu_clk" ,"cpu_ritimer" ,CLK_CPU_RITIMER ,0 }, + {"base_cpu_clk" ,"cpu_uart2" ,CLK_CPU_UART2 ,0 }, + {"base_cpu_clk" ,"cpu_uart3" ,CLK_CPU_UART3 ,0 }, + {"base_cpu_clk" ,"cpu_timer2" ,CLK_CPU_TIMER2 ,0 }, + {"base_cpu_clk" ,"cpu_timer3" ,CLK_CPU_TIMER3 ,0 }, + {"base_cpu_clk" ,"cpu_ssp1" ,CLK_CPU_SSP1 ,0 }, + {"base_cpu_clk" ,"cpu_qei" ,CLK_CPU_QEI ,0 }, + + {"base_periph_clk" ,"periph_bus" ,CLK_PERIPH_BUS ,CCU_BRANCH_IS_BUS }, + {"base_periph_clk" ,"periph_core" ,CLK_PERIPH_CORE ,0 }, + {"base_periph_clk" ,"periph_sgpio" ,CLK_PERIPH_SGPIO ,0 }, + + {"base_usb0_clk" ,"usb0" ,CLK_USB0 ,0 }, + {"base_usb1_clk" ,"usb1" ,CLK_USB1 ,0 }, + {"base_spi_clk" ,"spi" ,CLK_SPI ,0 }, + {"base_adchs_clk" ,"adchs" ,CLK_ADCHS ,0 },
drivers/clk/nxp/clk-lpc18xx-ccu.c line 114
Quoted 10 lines
drivers/clk/nxp/clk-lpc18xx-ccu.c new file +10
-0+ + {"base_audio_clk", "audio", CLK_AUDIO, 0}, + {"base_uart3_clk", "apb2_uart3", CLK_APB2_UART3, 0}, + {"base_uart2_clk", "apb2_uart2", CLK_APB2_UART2, 0}, + {"base_uart1_clk", "apb0_uart1", CLK_APB0_UART1, 0}, + {"base_uart0_clk", "apb0_uart0", CLK_APB0_UART0, 0}, + {"base_ssp1_clk", "apb2_ssp1", CLK_APB2_SSP1, 0}, + {"base_ssp0_clk", "apb0_ssp0", CLK_APB0_SSP0, 0}, + {"base_sdio_clk", "sdio", CLK_SDIO, 0}, +};
Hi Joachim,
If it were me, I would have broken this up into two tables, one for each CCU. In general I would structure the code to reflect the fact that two different IP blocks are being accessed. This isn't a deal breaker but I thought I would mention it in case you want to make the change.
Otherwise this series looks good to me. Let me know if you plan a V5 submission.
I can take patches #1-4 into the clk tree. Please add my Acked-by to patch #5. I will create an immutable branch to share with the arm-soc tree so that they can take #5 and have access to the dt-bindings headers.
Regards,
Mike
PATCH v4 3/5 clk: add lpc18xx ccu clk driver
Hi Mike,
Quoted 9 lines
Hi Joachim,
If it were me, I would have broken this up into two tables, one for each CCU. In general I would structure the code to reflect the fact that two different IP blocks are being accessed. This isn't a deal breaker but I thought I would mention it in case you want to make the change.
Otherwise this series looks good to me. Let me know if you plan a V5 submission.
If there is still time for 4.2 and you don't have any more comments on how the driver uses the DT bindings I would rather send a follow up patch that splits the ccu table for 4.3.
Quoted 4 lines
I can take patches #1-4 into the clk tree. Please add my Acked-by to patch #5. I will create an immutable branch to share with the arm-soc tree so that they can take #5 and have access to the dt-bindings headers.
Sounds good. I'll talk to arm-soc team about it. But it isn't critical for me to get the DTS changes in for 4.2, but I would be very grateful for getting the drivers and headers in for 4.2 so that 4.3 is ready and doesn't have any header dependencies for all the driver DTS stuff.
Thanks, Mike.
regards,
Joachim Eastwood
PATCH v4 3/5 clk: add lpc18xx ccu clk driver
Quoting Joachim Eastwood (2015-06-10 07:02:59)
Quoted 23 lines
Hi Mike,
Quoted 9 lines
Hi Joachim,
If it were me, I would have broken this up into two tables, one for each CCU. In general I would structure the code to reflect the fact that two different IP blocks are being accessed. This isn't a deal breaker but I thought I would mention it in case you want to make the change.
Otherwise this series looks good to me. Let me know if you plan a V5 submission.
If there is still time for 4.2 and you don't have any more comments on how the driver uses the DT bindings I would rather send a follow up patch that splits the ccu table for 4.3.
Quoted 4 lines
I can take patches #1-4 into the clk tree. Please add my Acked-by to patch #5. I will create an immutable branch to share with the arm-soc tree so that they can take #5 and have access to the dt-bindings headers.
Quoted 4 lines
Sounds good. I'll talk to arm-soc team about it. But it isn't critical for me to get the DTS changes in for 4.2, but I would be very grateful for getting the drivers and headers in for 4.2 so that 4.3 is ready and doesn't have any header dependencies for all the driver DTS stuff.
Patches #1-4 applied to clk-next for 4.2.
Regards,
Mike
Quoted 6 lines
Thanks, Mike.
regards,
Joachim Eastwood
PATCH v4 3/5 clk: add lpc18xx ccu clk driver
Quoted 24 lines · Michael Turquette
Quoting Joachim Eastwood (2015-06-10 07:02:59)
Quoted 23 lines
Hi Mike,
Quoted 9 lines
Hi Joachim,
If it were me, I would have broken this up into two tables, one for each CCU. In general I would structure the code to reflect the fact that two different IP blocks are being accessed. This isn't a deal breaker but I thought I would mention it in case you want to make the change.
Otherwise this series looks good to me. Let me know if you plan a V5 submission.
If there is still time for 4.2 and you don't have any more comments on how the driver uses the DT bindings I would rather send a follow up patch that splits the ccu table for 4.3.
Quoted 4 lines
I can take patches #1-4 into the clk tree. Please add my Acked-by to patch #5. I will create an immutable branch to share with the arm-soc tree so that they can take #5 and have access to the dt-bindings headers.
Quoted 6 lines
Quoted 4 lines
Sounds good. I'll talk to arm-soc team about it. But it isn't critical for me to get the DTS changes in for 4.2, but I would be very grateful for getting the drivers and headers in for 4.2 so that 4.3 is ready and doesn't have any header dependencies for all the driver DTS stuff.
Patches #1-4 applied to clk-next for 4.2.
Thanks a lot, Mike.
regards,
Joachim Eastwood
PATCH v4 4/5 doc: dt: add documentation for lpc1850-ccu clk driver
In reply to Joachim EastwoodAdd DT binding documentation for lpc1850-ccu clk driver.
--- .../devicetree/bindings/clock/lpc1850-ccu.txt | 77 ++++++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/lpc1850-ccu.txt
Documentation/devicetree/bindings/clock/lpc1850-ccu.txt new file +77 -0
@@ -0,0 +1,77 @@ +* NXP LPC1850 Clock Control Unit (CCU) + +Each CGU base clock has several clock branches which can be turned on +or off independently by the Clock Control Units CCU1 or CCU2. The +branch clocks are distributed between CCU1 and CCU2. + + - Above text taken from NXP LPC1850 User Manual. + +This binding uses the common clock binding: + Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible: + Should be "nxp,lpc1850-ccu" +- reg: + Shall define the base and range of the address space + containing clock control registers +- #clock-cells: + Shall have value <1>. The permitted clock-specifier values + are the branch clock names defined in table below. +- clocks: + Shall contain a list of phandles for the base clocks routed + from the CGU to the specific CCU. See mapping of base clocks + and CCU in table below. +- clock-names: + Shall contain a list of names for the base clock routed + from the CGU to the specific CCU. Valid CCU clock names: + "base_usb0_clk", "base_periph_clk", "base_usb1_clk", + "base_cpu_clk", "base_spifi_clk", "base_spi_clk", + "base_apb1_clk", "base_apb3_clk", "base_adchs_clk", + "base_sdio_clk", "base_ssp0_clk", "base_ssp1_clk", + "base_uart0_clk", "base_uart1_clk", "base_uart2_clk", + "base_uart3_clk", "base_audio_clk" + +Which branch clocks that are available on the CCU depends on the +specific LPC part. Check the user manual for your specific part. + +A list of CCU clocks can be found in dt-bindings/clock/lpc18xx-ccu.h. + +Example board file: + +soc { + ccu1: clock-controller at 40051000 { + compatible = "nxp,lpc1850-ccu"; + reg = <0x40051000 0x1000>; + #clock-cells = <1>; + clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>, + <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>, + <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>, + <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>; + clock-names = "base_apb3_clk", "base_apb1_clk", + "base_spifi_clk", "base_cpu_clk", + "base_periph_clk", "base_usb0_clk", + "base_usb1_clk", "base_spi_clk"; + }; + + ccu2: clock-controller at 40052000 { + compatible = "nxp,lpc1850-ccu"; + reg = <0x40052000 0x1000>; + #clock-cells = <1>; + clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>, + <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>, + <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>, + <&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>; + clock-names = "base_audio_clk", "base_uart3_clk", + "base_uart2_clk", "base_uart1_clk", + "base_uart0_clk", "base_ssp1_clk", + "base_ssp0_clk", "base_sdio_clk"; + }; + + /* A user of CCU brach clocks */ + uart1: serial at 40082000 { + ... + clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>; + ... + }; +};
Signature · 1 line
1.8.0
PATCH v4 5/5 ARM: dts: lpc18xx: add clock nodes for cgu and ccu
In reply to Joachim Eastwood--- arch/arm/boot/dts/lpc18xx.dtsi | 85 ++++++++++++++++++++++++++------ arch/arm/boot/dts/lpc4350-hitex-eval.dts | 4 -- 2 files changed, 71 insertions(+), 18 deletions(-)
arch/arm/boot/dts/lpc18xx.dtsi +71 -14
@@ -13,6 +13,9 @@ #include "armv7-m.dtsi" +#include "dt-bindings/clock/lpc18xx-cgu.h" +#include "dt-bindings/clock/lpc18xx-ccu.h" + / { cpus { #address-cells = <1>;
@@ -22,6 +25,7 @@ compatible = "arm,cortex-m3"; device_type = "cpu"; reg = <0x0>; + clocks = <&ccu1 CLK_CPU_CORE>; }; };
@@ -32,23 +36,76 @@ clock-frequency = <12000000>; }; - /* Temporary hardcode PLL1 until clk drivers are merged */ - pll1: pll1 { - compatible = "fixed-factor-clock"; - clocks = <&xtal>; + xtal32: xtal32 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + enet_rx_clk: enet_rx_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "enet_rx_clk"; + }; + + enet_tx_clk: enet_tx_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "enet_tx_clk"; + }; + + gp_clkin: gp_clkin { + compatible = "fixed-clock"; #clock-cells = <0>; - clock-div = <1>; - clock-mult = <12>; + clock-frequency = <0>; + clock-output-names = "gp_clkin"; }; }; soc { + cgu: clock-controller at 40050000 { + compatible = "nxp,lpc1850-cgu"; + reg = <0x40050000 0x1000>; + #clock-cells = <1>; + clocks = <&xtal>, <&xtal32>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>; + }; + + ccu1: clock-controller at 40051000 { + compatible = "nxp,lpc1850-ccu"; + reg = <0x40051000 0x1000>; + #clock-cells = <1>; + clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>, + <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>, + <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>, + <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>; + clock-names = "base_apb3_clk", "base_apb1_clk", + "base_spifi_clk", "base_cpu_clk", + "base_periph_clk", "base_usb0_clk", + "base_usb1_clk", "base_spi_clk"; + }; + + ccu2: clock-controller at 40052000 { + compatible = "nxp,lpc1850-ccu"; + reg = <0x40052000 0x1000>; + #clock-cells = <1>; + clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>, + <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>, + <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>, + <&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>; + clock-names = "base_audio_clk", "base_uart3_clk", + "base_uart2_clk", "base_uart1_clk", + "base_uart0_clk", "base_ssp1_clk", + "base_ssp0_clk", "base_sdio_clk"; + }; + uart0: serial at 40081000 { compatible = "ns16550a"; reg = <0x40081000 0x1000>; reg-shift = <2>; interrupts = <24>; - clocks = <&pll1>; + clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>; status = "disabled"; };
@@ -57,7 +114,7 @@ reg = <0x40082000 0x1000>; reg-shift = <2>; interrupts = <25>; - clocks = <&pll1>; + clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>; status = "disabled"; };
@@ -65,7 +122,7 @@ compatible = "nxp,lpc3220-timer"; reg = <0x40084000 0x1000>; interrupts = <12>; - clocks = <&pll1>; + clocks = <&ccu1 CLK_CPU_TIMER0>; clock-names = "timerclk"; };
@@ -73,7 +130,7 @@ compatible = "nxp,lpc3220-timer"; reg = <0x40085000 0x1000>; interrupts = <13>; - clocks = <&pll1>; + clocks = <&ccu1 CLK_CPU_TIMER1>; clock-names = "timerclk"; };
@@ -82,7 +139,7 @@ reg = <0x400c1000 0x1000>; reg-shift = <2>; interrupts = <26>; - clocks = <&pll1>; + clocks = <&ccu2 CLK_APB2_UART2>, <&ccu1 CLK_CPU_UART2>; status = "disabled"; };
@@ -91,7 +148,7 @@ reg = <0x400c2000 0x1000>; reg-shift = <2>; interrupts = <27>; - clocks = <&pll1>; + clocks = <&ccu2 CLK_APB2_UART3>, <&ccu1 CLK_CPU_UART3>; status = "disabled"; };
@@ -99,7 +156,7 @@ compatible = "nxp,lpc3220-timer"; reg = <0x400c3000 0x1000>; interrupts = <14>; - clocks = <&pll1>; + clocks = <&ccu1 CLK_CPU_TIMER2>; clock-names = "timerclk"; };
@@ -107,7 +164,7 @@ compatible = "nxp,lpc3220-timer"; reg = <0x400c4000 0x1000>; interrupts = <15>; - clocks = <&pll1>; + clocks = <&ccu1 CLK_CPU_TIMER3>; clock-names = "timerclk"; }; };
arch/arm/boot/dts/lpc4350-hitex-eval.dts +0 -4
@@ -36,10 +36,6 @@ }; }; -&pll1 { - clock-mult = <15>; -}; - &uart0 { status = "okay"; };
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1.8.0