net: dsa: add QCA AR8xxx switch family support

303 lines not on this page · raw message

82 lines not on this page · raw message

index e6f6cc3..fffb9aa 100644
@@ -893,6 +893,7 @@ static SIMPLE_DEV_PM_OPS(dsa_pm_ops, dsa_suspend, dsa_resume);
 
 static const struct of_device_id dsa_of_match_table[] = {
 	{ .compatible = "brcm,bcm7445-switch-v4.0" },
+	{ .compatible = "qca,ar8xxx", },
 	{ .compatible = "marvell,dsa", },
 	{}
 };

index 4ce3ffc..2f0fa4d 100644
@@ -22,6 +22,55 @@
 
 #include "ar8xxx.h"
 
+#define MIB_DESC(_s, _o, _n)	\
+	{			\
+		.size = (_s),	\
+		.offset = (_o),	\
+		.name = (_n),	\
+	}
+
+static const struct ar8xxx_mib_desc ar8327_mib[] = {
+	MIB_DESC(1, 0x00, "RxBroad"),
+	MIB_DESC(1, 0x04, "RxPause"),
+	MIB_DESC(1, 0x08, "RxMulti"),
+	MIB_DESC(1, 0x0c, "RxFcsErr"),
+	MIB_DESC(1, 0x10, "RxAlignErr"),
+	MIB_DESC(1, 0x14, "RxRunt"),
+	MIB_DESC(1, 0x18, "RxFragment"),
+	MIB_DESC(1, 0x1c, "Rx64Byte"),
+	MIB_DESC(1, 0x20, "Rx128Byte"),
+	MIB_DESC(1, 0x24, "Rx256Byte"),
+	MIB_DESC(1, 0x28, "Rx512Byte"),
+	MIB_DESC(1, 0x2c, "Rx1024Byte"),
+	MIB_DESC(1, 0x30, "Rx1518Byte"),
+	MIB_DESC(1, 0x34, "RxMaxByte"),
+	MIB_DESC(1, 0x38, "RxTooLong"),
+	MIB_DESC(2, 0x3c, "RxGoodByte"),
+	MIB_DESC(2, 0x44, "RxBadByte"),
+	MIB_DESC(1, 0x4c, "RxOverFlow"),
+	MIB_DESC(1, 0x50, "Filtered"),
+	MIB_DESC(1, 0x54, "TxBroad"),
+	MIB_DESC(1, 0x58, "TxPause"),
+	MIB_DESC(1, 0x5c, "TxMulti"),
+	MIB_DESC(1, 0x60, "TxUnderRun"),
+	MIB_DESC(1, 0x64, "Tx64Byte"),
+	MIB_DESC(1, 0x68, "Tx128Byte"),
+	MIB_DESC(1, 0x6c, "Tx256Byte"),
+	MIB_DESC(1, 0x70, "Tx512Byte"),
+	MIB_DESC(1, 0x74, "Tx1024Byte"),
+	MIB_DESC(1, 0x78, "Tx1518Byte"),
+	MIB_DESC(1, 0x7c, "TxMaxByte"),
+	MIB_DESC(1, 0x80, "TxOverSize"),
+	MIB_DESC(2, 0x84, "TxByte"),
+	MIB_DESC(1, 0x8c, "TxCollision"),
+	MIB_DESC(1, 0x90, "TxAbortCol"),
+	MIB_DESC(1, 0x94, "TxMultiCol"),
+	MIB_DESC(1, 0x98, "TxSingleCol"),
+	MIB_DESC(1, 0x9c, "TxExcDefer"),
+	MIB_DESC(1, 0xa0, "TxDefer"),
+	MIB_DESC(1, 0xa4, "TxLateCol"),
+};
+
 u32
 ar8xxx_mii_read32(struct mii_bus *bus, int phy_id, int regnum)
 {

@@ -184,6 +233,10 @@ static int ar8xxx_setup(struct dsa_switch *ds)
 	if (ret < 0)
 		return ret;
 
+	/* Enable MIB counters */
+	ar8xxx_reg_set(ds, AR8327_REG_MIB, AR8327_MIB_CPU_KEEP);
+	ar8xxx_write(ds, AR8327_REG_MODULE_EN, AR8327_MODULE_EN_MIB);
+
 	/* Disable forwarding by default on all ports */
 	for (i = 0; i < AR8327_NUM_PORTS; i++)
 		ar8xxx_rmw(ds, AR8327_PORT_LOOKUP_CTRL(i),

@@ -228,6 +281,42 @@ ar8xxx_phy_write(struct dsa_switch *ds, int phy, int regnum, u16 val)
 	return mdiobus_write(bus, phy, regnum, val);
 }
 
+static void ar8xxx_get_strings(struct dsa_switch *ds, int phy, uint8_t *data)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) {
+		strncpy(data + i * ETH_GSTRING_LEN, ar8327_mib[i].name,
+			ETH_GSTRING_LEN);
+	}
+}
+
+static void ar8xxx_get_ethtool_stats(struct dsa_switch *ds, int phy,
+				     uint64_t *data)
+{
+	const struct ar8xxx_mib_desc *mib;
+	uint32_t reg, i, port;
+	u64 hi;
+
+	port = phy_to_port(phy);
+
+	for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) {
+		mib = &ar8327_mib[i];
+		reg = AR8327_PORT_MIB_COUNTER(port) + mib->offset;
+
+		data[i] = ar8xxx_read(ds, reg);
+		if (mib->size == 2) {
+			hi = ar8xxx_read(ds, reg + 4);
+			data[i] |= hi << 32;
+		}
+	}
+}
+
+static int ar8xxx_get_sset_count(struct dsa_switch *ds)
+{
+	return ARRAY_SIZE(ar8327_mib);
+}
+
 static void ar8xxx_poll_link(struct dsa_switch *ds)
 {
 	int i = 0;

@@ -275,13 +364,16 @@ static void ar8xxx_poll_link(struct dsa_switch *ds)
 }
 
 static struct dsa_switch_driver ar8xxx_switch_driver = {
-	.tag_protocol	= DSA_TAG_PROTO_NONE,
-	.probe		= ar8xxx_probe,
-	.setup		= ar8xxx_setup,
-	.set_addr	= ar8xxx_set_addr,
-	.poll_link	= ar8xxx_poll_link,
-	.phy_read	= ar8xxx_phy_read,
-	.phy_write	= ar8xxx_phy_write,
+	.tag_protocol		= DSA_TAG_PROTO_NONE,
+	.probe			= ar8xxx_probe,
+	.setup			= ar8xxx_setup,
+	.set_addr		= ar8xxx_set_addr,
+	.poll_link		= ar8xxx_poll_link,
+	.phy_read		= ar8xxx_phy_read,
+	.phy_write		= ar8xxx_phy_write,
+	.get_strings		= ar8xxx_get_strings,
+	.get_ethtool_stats	= ar8xxx_get_ethtool_stats,
+	.get_sset_count		= ar8xxx_get_sset_count,
 };
 
 static int __init ar8xxx_init(void)

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81 lines not on this page · raw message

index 7c7a125..98cc7ed 100644
@@ -17,6 +17,11 @@
 #define __AR8XXX_H
 
 #include <linux/delay.h>
+#include <linux/regmap.h>
+
+struct ar8xxx_priv {
+	struct regmap *regmap;
+};
 
 struct ar8xxx_mib_desc {
 	unsigned int size;

index fbca63b..64ddf6f 100644
@@ -26,6 +26,7 @@ enum dsa_tag_protocol {
 	DSA_TAG_PROTO_TRAILER,
 	DSA_TAG_PROTO_EDSA,
 	DSA_TAG_PROTO_BRCM,
+	DSA_TAG_PROTO_QCA,
 };
 
 #define DSA_MAX_SWITCHES	4

index fffb9aa..6010a7d 100644
@@ -249,6 +249,11 @@ static int dsa_switch_setup_one(struct dsa_switch *ds, struct device *parent)
 			dst->rcv = brcm_netdev_ops.rcv;
 			break;
 #endif
+#ifdef CONFIG_NET_DSA_TAG_QCA
+		case DSA_TAG_PROTO_QCA:
+			dst->rcv = qca_netdev_ops.rcv;
+			break;
+#endif
 		case DSA_TAG_PROTO_NONE:
 			break;
 		default:

index d5f1f9b..350c94b 100644
@@ -74,5 +74,7 @@ extern const struct dsa_device_ops trailer_netdev_ops;
 /* tag_brcm.c */
 extern const struct dsa_device_ops brcm_netdev_ops;
 
+/* tag_qca.c */
+extern const struct dsa_device_ops qca_netdev_ops;
 
 #endif

index 04ffad3..cd8f552 100644
@@ -925,6 +925,11 @@ int dsa_slave_create(struct dsa_switch *ds, struct device *parent,
 		p->xmit = brcm_netdev_ops.xmit;
 		break;
 #endif
+#ifdef CONFIG_NET_DSA_TAG_QCA
+	case DSA_TAG_PROTO_QCA:
+		p->xmit = qca_netdev_ops.xmit;
+		break;
+#endif
 	default:
 		p->xmit	= dsa_slave_notag_xmit;
 		break;

158 lines not on this page · raw message

index 327abd4..4044614 100644
@@ -292,15 +292,31 @@ static int ar8xxx_setup(struct dsa_switch *ds)
 	if (ret < 0)
 		return ret;
 
+	/* Enable CPU Port */
+	ar8xxx_reg_set(ds, AR8327_REG_GLOBAL_FW_CTRL0,
+		       AR8327_GLOBAL_FW_CTRL0_CPU_PORT_EN);
+
 	/* Enable MIB counters */
 	ar8xxx_reg_set(ds, AR8327_REG_MIB, AR8327_MIB_CPU_KEEP);
 	ar8xxx_write(ds, AR8327_REG_MODULE_EN, AR8327_MODULE_EN_MIB);
 
+	/* Enable QCA header mode on Port 0 */
+	ar8xxx_write(ds, AR8327_REG_PORT_HDR_CTRL(0),
+		     AR8327_PORT_HDR_CTRL_ALL << AR8327_PORT_HDR_CTRL_TX_S |
+		     AR8327_PORT_HDR_CTRL_ALL << AR8327_PORT_HDR_CTRL_RX_S);
+
 	/* Disable forwarding by default on all ports */
 	for (i = 0; i < AR8327_NUM_PORTS; i++)
 		ar8xxx_rmw(ds, AR8327_PORT_LOOKUP_CTRL(i),
 			   AR8327_PORT_LOOKUP_MEMBER, 0);
 
+	/* Forward all unknown frames to CPU port for Linux processing */
+	ar8xxx_write(ds, AR8327_REG_GLOBAL_FW_CTRL1,
+		     BIT(0) << AR8327_GLOBAL_FW_CTRL1_IGMP_DP_S |
+		     BIT(0) << AR8327_GLOBAL_FW_CTRL1_BC_DP_S |
+		     BIT(0) << AR8327_GLOBAL_FW_CTRL1_MC_DP_S |
+		     BIT(0) << AR8327_GLOBAL_FW_CTRL1_UC_DP_S);
+
 	/* Setup connection between CPU ports & PHYs */
 	for (i = 0; i < DSA_MAX_PORTS; i++) {
 		/* CPU port gets connected to all PHYs in the switch */

@@ -312,8 +328,16 @@ static int ar8xxx_setup(struct dsa_switch *ds)
 
 		/* Invividual PHYs gets connected to CPU port only */
 		if (ds->phys_port_mask & BIT(i)) {
-			ar8xxx_rmw(ds, AR8327_PORT_LOOKUP_CTRL(phy_to_port(i)),
+			int phy = phy_to_port(i);
+
+			ar8xxx_rmw(ds, AR8327_PORT_LOOKUP_CTRL(phy),
 				   AR8327_PORT_LOOKUP_MEMBER, BIT(0));
+
+			/* Disable Auto-learning by default so the switch
+			 * doesn't try to forward the frame to another port
+			 */
+			ar8xxx_reg_clear(ds, AR8327_PORT_LOOKUP_CTRL(phy),
+					 AR8327_PORT_LOOKUP_LEARN);
 		}
 	}
 

@@ -423,7 +447,7 @@ static void ar8xxx_poll_link(struct dsa_switch *ds)
 }
 
 static struct dsa_switch_driver ar8xxx_switch_driver = {
-	.tag_protocol		= DSA_TAG_PROTO_NONE,
+	.tag_protocol		= DSA_TAG_PROTO_QCA,
 	.priv_size		= sizeof(struct ar8xxx_priv),
 	.probe			= ar8xxx_probe,
 	.setup			= ar8xxx_setup,

index 98cc7ed..e68b92a 100644
@@ -62,6 +62,28 @@ struct ar8xxx_mib_desc {
 #define   AR8XXX_PORT_STATUS_LINK_AUTO	BIT(9)
 #define   AR8XXX_PORT_STATUS_LINK_PAUSE	BIT(10)
 
+#define AR8327_REG_PORT_HDR_CTRL(_i)		(0x9c + (_i * 4))
+#define   AR8327_PORT_HDR_CTRL_RX_MASK		GENMASK(3, 2)
+#define   AR8327_PORT_HDR_CTRL_RX_S		2
+#define   AR8327_PORT_HDR_CTRL_TX_MASK		GENMASK(1, 0)
+#define   AR8327_PORT_HDR_CTRL_TX_S		0
+#define   AR8327_PORT_HDR_CTRL_ALL		2
+#define   AR8327_PORT_HDR_CTRL_MGMT		1
+#define   AR8327_PORT_HDR_CTRL_NONE		0
+
+#define AR8327_REG_GLOBAL_FW_CTRL0		0x620
+#define   AR8327_GLOBAL_FW_CTRL0_CPU_PORT_EN	BIT(10)
+
+#define AR8327_REG_GLOBAL_FW_CTRL1		0x624
+#define   AR8327_GLOBAL_FW_CTRL1_IGMP_DP_MASK	GENMASK(30, 24)
+#define   AR8327_GLOBAL_FW_CTRL1_IGMP_DP_S	24
+#define   AR8327_GLOBAL_FW_CTRL1_BC_DP_MASK	GENMASK(22, 16)
+#define   AR8327_GLOBAL_FW_CTRL1_BC_DP_S	16
+#define   AR8327_GLOBAL_FW_CTRL1_MC_DP_MASK	GENMASK(14, 8)
+#define   AR8327_GLOBAL_FW_CTRL1_MC_DP_S	8
+#define   AR8327_GLOBAL_FW_CTRL1_UC_DP_MASK	GENMASK(6, 0)
+#define   AR8327_GLOBAL_FW_CTRL1_UC_DP_S	0
+
 #define AR8327_PORT_LOOKUP_CTRL(_i)		(0x660 + (_i) * 0xc)
 #define   AR8327_PORT_LOOKUP_MEMBER		GENMASK(6, 0)
 #define   AR8327_PORT_LOOKUP_IN_MODE		GENMASK(9, 8)

index 4044614..7559249 100644
@@ -19,6 +19,7 @@
 #include <net/dsa.h>
 #include <linux/phy.h>
 #include <linux/of_net.h>
+#include <linux/of_platform.h>
 
 #include "ar8xxx.h"
 

@@ -260,6 +261,9 @@ static int ar8xxx_set_pad_ctrl(struct dsa_switch *ds, int port, int mode)
 		ar8xxx_write(ds, AR8327_REG_PORT5_PAD_CTRL,
 			     AR8327_PORT_PAD_RGMII_RX_DELAY_EN);
 		break;
+	case PHY_INTERFACE_MODE_SGMII:
+		ar8xxx_write(ds, reg, AR8327_PORT_PAD_SGMII_EN);
+		break;
 	default:
 		pr_err("xMII mode %d not supported\n", mode);
 		return -EINVAL;

@@ -268,6 +272,48 @@ static int ar8xxx_set_pad_ctrl(struct dsa_switch *ds, int port, int mode)
 	return 0;
 }
 
+static int ar8xxx_of_setup(struct dsa_switch *ds)
+{
+	struct device_node *dn = ds->pd->of_node;
+	const char *s_phymode;
+	int ret, mode;
+	u32 phy_id, ctrl;
+
+	/* If port6-phy-mode property exists, configure it accordingly */
+	if (!of_property_read_string(dn, "qca,port6-phy-mode", &s_phymode)) {
+		for (mode = 0; mode < PHY_INTERFACE_MODE_MAX; mode++)
+			if (!strcasecmp(s_phymode, phy_modes(mode)))
+				break;
+
+		if (mode == PHY_INTERFACE_MODE_MAX)
+			pr_err("Unknown phy-mode: \"%s\"\n", s_phymode);
+
+		ret = ar8xxx_set_pad_ctrl(ds, 6, mode);
+		if (ret < 0)
+			return ret;
+	}
+
+	/* If a phy ID is specified for PORT6 mac, connect them together */
+	if (!of_property_read_u32(dn, "qca,port6-phy-id", &phy_id)) {
+		ar8xxx_rmw(ds, AR8327_PORT_LOOKUP_CTRL(6),
+			   AR8327_PORT_LOOKUP_MEMBER, BIT(phy_to_port(phy_id)));
+		ar8xxx_rmw(ds, AR8327_PORT_LOOKUP_CTRL(phy_to_port(phy_id)),
+			   AR8327_PORT_LOOKUP_MEMBER, BIT(6));
+
+		/* We want the switch to be pass-through and act like a PHY on
+		 * these ports. So BC/MC/UC & IGMP frames need to be accepted
+		 */
+		ctrl = BIT(phy_to_port(phy_id)) | BIT(6);
+		ar8xxx_reg_set(ds, AR8327_REG_GLOBAL_FW_CTRL1,
+			       ctrl << AR8327_GLOBAL_FW_CTRL1_IGMP_DP_S |
+			       ctrl << AR8327_GLOBAL_FW_CTRL1_BC_DP_S |
+			       ctrl << AR8327_GLOBAL_FW_CTRL1_MC_DP_S |
+			       ctrl << AR8327_GLOBAL_FW_CTRL1_UC_DP_S);
+	}
+
+	return 0;
+}
+
 static int ar8xxx_setup(struct dsa_switch *ds)
 {
 	struct ar8xxx_priv *priv = ds_to_priv(ds);

@@ -341,6 +387,10 @@ static int ar8xxx_setup(struct dsa_switch *ds)
 		}
 	}
 
+	ret = ar8xxx_of_setup(ds);
+	if (ret < 0)
+		return ret;
+
 	return 0;
 }