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FAILED: patch "[PATCH] clk: at91: pll: fix input range validity check" failed to apply to 3.14-stable tree

PATCH [email protected] 1 participant 1 message Jun 23, 2015

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Stable branch Common clk Arm/Microchip (AT91) SoC support
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The patch below does not apply to the 3.14-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.

thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

Quoted 1 line

From 6c7b03e1aef2e92176435f4fa562cc483422d20f Mon Sep 17 00:00:00 2001

From: Boris Brezillon <[email protected]>
Date: Fri, 27 Mar 2015 23:53:15 +0100
Subject: [PATCH] clk: at91: pll: fix input range validity check

The PLL impose a certain input range to work correctly, but it appears that this input range does not apply on the input clock (or parent clock) but on the input clock after it has passed the PLL divisor.
Fix the implementation accordingly.

Cc <[email protected]> # v3.14+
Signed-off-by Boris Brezillon <[email protected]>
Reported-by Jonas Andersson <[email protected]>
drivers/clk/at91/clk-pll.c +10 -2
index 6ec79dbc0840..cbbe40377ad6 100644
@@ -173,8 +173,7 @@ static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,
 	int i = 0;
 
 	/* Check if parent_rate is a valid input rate */
-	if (parent_rate < characteristics->input.min ||
-	    parent_rate > characteristics->input.max)
+	if (parent_rate < characteristics->input.min)
 		return -ERANGE;
 
 	/*

@@ -187,6 +186,15 @@ static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,
 	if (!mindiv)
 		mindiv = 1;
 
+	if (parent_rate > characteristics->input.max) {
+		tmpdiv = DIV_ROUND_UP(parent_rate, characteristics->input.max);
+		if (tmpdiv > PLL_DIV_MAX)
+			return -ERANGE;
+
+		if (tmpdiv > mindiv)
+			mindiv = tmpdiv;
+	}
+
 	/*
 	 * Calculate the maximum divider which is limited by PLL register
 	 * layout (limited by the MUL or DIV field size).

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