Updated Skylake Frontend profiling patchkit

PATCH New Andi Kleen 2 participants 6 messages Jun 30, 2015 – Sep 18, 2015

Subsystems (2)

x86 perf events

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Andi Kleen

author

2015-06-30 23:33 UTC #0 lore raw

Reworked the extra reg test val patch to just change the default value.

Andi Kleen

author

2015-06-30 23:33 UTC #1 lore raw

PATCH 1/3 x86, perf: Make merge_attr global to use from perf_event_intel

From: Andi Kleen <[email protected]>

merge_attr allows to merge two sysfs attribute tables. Export it to be usable by other files too.

Next patch is going to use that to extend the sysfs format attributes for a CPU.

Signed-off-by Andi Kleen <[email protected]>

---
 arch/x86/kernel/cpu/perf_event.c | 2 +-
 arch/x86/kernel/cpu/perf_event.h | 3 +++
 2 files changed, 4 insertions(+), 1 deletion(-)

arch/x86/kernel/cpu/perf_event.c +1 -1

index 5801a14..81e2a74 100644
@@ -1561,7 +1561,7 @@ static void __init filter_events(struct attribute **attrs)
 }
 
 /* Merge two pointer arrays */
-static __init struct attribute **merge_attr(struct attribute **a, struct attribute **b)
+__init struct attribute **merge_attr(struct attribute **a, struct attribute **b)
 {
 	struct attribute **new;
 	int j, i;

arch/x86/kernel/cpu/perf_event.h +3 -0

index 0db9de4..3598f67 100644
@@ -795,6 +795,8 @@ static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip)
 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event);
 ssize_t intel_event_sysfs_show(char *page, u64 config);
 
+struct attribute **merge_attr(struct attribute **a, struct attribute **b);
+
 #ifdef CONFIG_CPU_SUP_AMD
 
 int amd_pmu_init(void);

@@ -940,6 +942,7 @@ static inline int is_ht_workaround_enabled(void)
 {
 	return !!(x86_pmu.flags & PMU_FL_EXCL_ENABLED);
 }
+
 #else /* CONFIG_CPU_SUP_INTEL */
 
 static inline void reserve_ds_buffers(void)

Signature · 1 line

2.4.2

Andi Kleen

author

2015-06-30 23:33 UTC #2 lore raw

PATCH 2/3 x86, perf: Use 0x11 as extra reg test value

In reply to Andi Kleen

From: Andi Kleen <[email protected]>

The next patch adds a new perf extra reg where 0x1ff is not a valid value. Use 0x11 instead.

Signed-off-by Andi Kleen <[email protected]>

---
 arch/x86/kernel/cpu/perf_event_intel.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

arch/x86/kernel/cpu/perf_event_intel.c +1 -1

index 7c397e8..28b985c 100644
@@ -3575,7 +3575,7 @@ __init int intel_pmu_init(void)
 	 */
 	if (x86_pmu.extra_regs) {
 		for (er = x86_pmu.extra_regs; er->msr; er++) {
-			er->extra_msr_access = check_msr(er->msr, 0x1ffUL);
+			er->extra_msr_access = check_msr(er->msr, 0x11UL);
 			/* Disable LBR select mapping */
 			if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
 				x86_pmu.lbr_sel_map = NULL;

Signature · 1 line

2.4.2

tip-bot for Andi Kleen

merge bot

2015-08-04 09:01 UTC #3 lore raw

[tip:perf/core] perf/x86/intel: Use 0x11 as extra reg test value

perf/x86/intel: Use 0x11 as extra reg test value

Commit-ID:  8c4fe7095d633dd5543690ea5c3d522c5cd989b6
Gitweb:     http://git.kernel.org/tip/8c4fe7095d633dd5543690ea5c3d522c5cd989b6
Author:     Andi Kleen <[email protected]>
AuthorDate: Tue, 30 Jun 2015 16:33:24 -0700
Committer:  Ingo Molnar <[email protected]>
CommitDate: Tue, 4 Aug 2015 10:16:59 +0200

perf/x86/intel: Use 0x11 as extra reg test value

The next patch adds a new perf extra register where 0x1ff is not a valid value. Use 0x11 instead.

Signed-off-by Andi Kleen <[email protected]>

Signed-off-by Peter Zijlstra (Intel) <[email protected]>

Cc Linus Torvalds <[email protected]>

Cc Peter Zijlstra <[email protected]>

Cc Thomas Gleixner <[email protected]>

Link http://lkml.kernel.org/r/[email protected] open here

Signed-off-by Ingo Molnar <[email protected]>

---
 arch/x86/kernel/cpu/perf_event_intel.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

arch/x86/kernel/cpu/perf_event_intel.c +1 -1

index 28fc272..a478e3c 100644
@@ -3579,7 +3579,7 @@ __init int intel_pmu_init(void)
 	 */
 	if (x86_pmu.extra_regs) {
 		for (er = x86_pmu.extra_regs; er->msr; er++) {
-			er->extra_msr_access = check_msr(er->msr, 0x1ffUL);
+			er->extra_msr_access = check_msr(er->msr, 0x11UL);
 			/* Disable LBR select mapping */
 			if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
 				x86_pmu.lbr_sel_map = NULL;

Andi Kleen

author

2015-06-30 23:34 UTC #4 lore raw

PATCH 3/3 x86, perf: Add PEBS frontend profiling for Skylake

In reply to Andi Kleen

From: Andi Kleen <[email protected]>

Skylake has a new FRONTEND_LATENCY PEBS event to accurate profile frontend problems (like ITLB or decoding issues)

The new event is configured through a separate MSR, which selects a range of sub events.

Define the extra MSR as a extra reg and export support for it through sysfs. To avoid duplicating the existing tables use a new function to add new entries to existing tables.

v2: Don't use custom test value.

Signed-off-by Andi Kleen <[email protected]>

---
 arch/x86/include/asm/msr-index.h       |  2 ++
 arch/x86/kernel/cpu/perf_event.h       |  1 +
 arch/x86/kernel/cpu/perf_event_intel.c | 11 ++++++++++-
 3 files changed, 13 insertions(+), 1 deletion(-)

arch/x86/include/asm/msr-index.h +2 -0

index 96a00de..a5371dc 100644
@@ -133,6 +133,8 @@
 #define DEBUGCTLMSR_BTS_OFF_USR		(1UL << 10)
 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI	(1UL << 11)
 
+#define MSR_PEBS_FRONTEND		0x000003f7
+
 #define MSR_IA32_POWER_CTL		0x000001fc
 
 #define MSR_IA32_MC0_CTL		0x00000400

arch/x86/kernel/cpu/perf_event.h +1 -0

index 3598f67..d9055c1 100644
@@ -47,6 +47,7 @@ enum extra_reg_type {
 	EXTRA_REG_RSP_1 = 1,	/* offcore_response_1 */
 	EXTRA_REG_LBR   = 2,	/* lbr_select */
 	EXTRA_REG_LDLAT = 3,	/* ld_lat_threshold */
+	EXTRA_REG_FE    = 4,    /* fe_* */
 
 	EXTRA_REG_MAX		/* number of entries needed */
 };

arch/x86/kernel/cpu/perf_event_intel.c +10 -1

index 28b985c..66e713e 100644
@@ -205,6 +205,7 @@ static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
 	INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
 	INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
 	INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
+	INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x3fff17, FE),
 	EVENT_EXTRA_END
 };

@@ -2875,6 +2876,8 @@ PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
 
 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
 
+PMU_FORMAT_ATTR(frontend, "config1:0-23");
+
 static struct attribute *intel_arch3_formats_attr[] = {
 	&format_attr_event.attr,
 	&format_attr_umask.attr,

@@ -2891,6 +2894,11 @@ static struct attribute *intel_arch3_formats_attr[] = {
 	NULL,
 };
 
+static struct attribute *skl_format_attr[] = {
+	&format_attr_frontend.attr,
+	NULL,
+};
+
 static __initconst const struct x86_pmu core_pmu = {
 	.name			= "core",
 	.handle_irq		= x86_pmu_handle_irq,

@@ -3500,7 +3508,8 @@ __init int intel_pmu_init(void)
 
 		x86_pmu.hw_config = hsw_hw_config;
 		x86_pmu.get_event_constraints = hsw_get_event_constraints;
-		x86_pmu.cpu_events = hsw_events_attrs;
+		x86_pmu.format_attrs = merge_attr(intel_arch3_formats_attr,
+						  skl_format_attr);
 		WARN_ON(!x86_pmu.format_attrs);
 		x86_pmu.cpu_events = hsw_events_attrs;
 		pr_cont("Skylake events, ");

Signature · 1 line

2.4.2

tip-bot for Andi Kleen

merge bot

2015-09-18 08:47 UTC #5 lore raw

[tip:perf/core] perf/x86/intel/pebs: Add PEBS frontend profiling for Skylake

perf/x86/intel/pebs: Add PEBS frontend profiling for Skylake

Commit-ID:  d0dc8494cd6904f8ad035d9ad97f313948f35d0c
Gitweb:     http://git.kernel.org/tip/d0dc8494cd6904f8ad035d9ad97f313948f35d0c
Author:     Andi Kleen <[email protected]>
AuthorDate: Wed, 9 Sep 2015 14:53:59 -0700
Committer:  Ingo Molnar <[email protected]>
CommitDate: Fri, 18 Sep 2015 09:20:22 +0200

perf/x86/intel/pebs: Add PEBS frontend profiling for Skylake

Skylake has a new FRONTEND_LATENCY PEBS event to accurately profile frontend problems (like ITLB or decoding issues).

The new event is configured through a separate MSR, which selects a range of sub events.

Define the extra MSR as a extra reg and export support for it through sysfs. To avoid duplicating the existing tables use a new function to add new entries to existing tables.

Signed-off-by Andi Kleen <[email protected]>

Signed-off-by Peter Zijlstra (Intel) <[email protected]>

Acked-by Thomas Gleixner <[email protected]>

Cc Linus Torvalds <[email protected]>

Cc Peter Zijlstra <[email protected]>

Link http://lkml.kernel.org/r/[email protected] open here

Signed-off-by Ingo Molnar <[email protected]>

---
 arch/x86/include/asm/msr-index.h       |  2 ++
 arch/x86/kernel/cpu/perf_event.h       |  1 +
 arch/x86/kernel/cpu/perf_event_intel.c | 11 ++++++++++-
 3 files changed, 13 insertions(+), 1 deletion(-)

arch/x86/include/asm/msr-index.h +2 -0

index c1c0a1c..54390bc 100644
@@ -141,6 +141,8 @@
 #define DEBUGCTLMSR_BTS_OFF_USR		(1UL << 10)
 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI	(1UL << 11)
 
+#define MSR_PEBS_FRONTEND		0x000003f7
+
 #define MSR_IA32_POWER_CTL		0x000001fc
 
 #define MSR_IA32_MC0_CTL		0x00000400

arch/x86/kernel/cpu/perf_event.h +1 -0

index 5edf6d8..165be83 100644
@@ -47,6 +47,7 @@ enum extra_reg_type {
 	EXTRA_REG_RSP_1 = 1,	/* offcore_response_1 */
 	EXTRA_REG_LBR   = 2,	/* lbr_select */
 	EXTRA_REG_LDLAT = 3,	/* ld_lat_threshold */
+	EXTRA_REG_FE    = 4,    /* fe_* */
 
 	EXTRA_REG_MAX		/* number of entries needed */
 };

arch/x86/kernel/cpu/perf_event_intel.c +10 -1

index 1d84b41..ef74c9d 100644
@@ -205,6 +205,7 @@ static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
 	INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
 	INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
 	INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
+	INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x3fff17, FE),
 	EVENT_EXTRA_END
 };

@@ -2891,6 +2892,8 @@ PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
 
 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
 
+PMU_FORMAT_ATTR(frontend, "config1:0-23");
+
 static struct attribute *intel_arch3_formats_attr[] = {
 	&format_attr_event.attr,
 	&format_attr_umask.attr,

@@ -2907,6 +2910,11 @@ static struct attribute *intel_arch3_formats_attr[] = {
 	NULL,
 };
 
+static struct attribute *skl_format_attr[] = {
+	&format_attr_frontend.attr,
+	NULL,
+};
+
 static __initconst const struct x86_pmu core_pmu = {
 	.name			= "core",
 	.handle_irq		= x86_pmu_handle_irq,

@@ -3516,7 +3524,8 @@ __init int intel_pmu_init(void)
 
 		x86_pmu.hw_config = hsw_hw_config;
 		x86_pmu.get_event_constraints = hsw_get_event_constraints;
-		x86_pmu.cpu_events = hsw_events_attrs;
+		x86_pmu.format_attrs = merge_attr(intel_arch3_formats_attr,
+						  skl_format_attr);
 		WARN_ON(!x86_pmu.format_attrs);
 		x86_pmu.cpu_events = hsw_events_attrs;
 		pr_cont("Skylake events, ");