Patch "arm/arm64: KVM: Keep elrsr/aisr in sync with software model" has been added to the 3.14-stable tree

This is a note to let you know that I've just added the patch titled

arm/arm64: KVM: Keep elrsr/aisr in sync with software model

to the 3.14-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
arm-arm64-kvm-keep-elrsr-aisr-in-sync-with-software-model.patch
and it can be found in the queue-3.14 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From: Christoffer Dall <[email protected]>
Date: Fri, 13 Mar 2015 17:02:56 +0000
Subject: arm/arm64: KVM: Keep elrsr/aisr in sync with software model
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From: Christoffer Dall <[email protected]>

commit ae705930fca6322600690df9dc1c7d0516145a93 upstream.

[Note the upstream one of this patch requires applying full GICv3 support but it's out of the scope of stable kernel. So this patch has a huge modification for stable kernel comparing to the upstream one.]

There is an interesting bug in the vgic code, which manifests itself when the KVM run loop has a signal pending or needs a vmid generation rollover after having disabled interrupts but before actually switching to the guest.

In this case, we flush the vgic as usual, but we sync back the vgic state and exit to userspace before entering the guest. The consequence is that we will be syncing the list registers back to the software model using the GICH_ELRSR and GICH_EISR from the last execution of the guest, potentially overwriting a list register containing an interrupt.

This showed up during migration testing where we would capture a state where the VM has masked the arch timer but there were no interrupts, resulting in a hung test.

---
 virt/kvm/arm/vgic.c |   10 ++++++++++
 1 file changed, 10 insertions(+)

@@ -1042,6 +1042,7 @@ static bool vgic_queue_irq(struct kvm_vc
 			  lr, irq, vgic_cpu->vgic_lr[lr]);
 		BUG_ON(!test_bit(lr, vgic_cpu->lr_used));
 		vgic_cpu->vgic_lr[lr] |= GICH_LR_PENDING_BIT;
+		__clear_bit(lr, (unsigned long *)vgic_cpu->vgic_elrsr);
 		return true;
 	}
 

@@ -1055,6 +1056,7 @@ static bool vgic_queue_irq(struct kvm_vc
 	vgic_cpu->vgic_lr[lr] = MK_LR_PEND(sgi_source_id, irq);
 	vgic_cpu->vgic_irq_lr_map[irq] = lr;
 	set_bit(lr, vgic_cpu->lr_used);
+	__clear_bit(lr, (unsigned long *)vgic_cpu->vgic_elrsr);
 
 	if (!vgic_irq_is_edge(vcpu, irq))
 		vgic_cpu->vgic_lr[lr] |= GICH_LR_EOI;

@@ -1209,6 +1211,14 @@ static bool vgic_process_maintenance(str
 	if (vgic_cpu->vgic_misr & GICH_MISR_U)
 		vgic_cpu->vgic_hcr &= ~GICH_HCR_UIE;
 
+	/*
+	 * In the next iterations of the vcpu loop, if we sync the vgic state
+	 * after flushing it, but before entering the guest (this happens for
+	 * pending signals and vmid rollovers), then make sure we don't pick
+	 * up any old maintenance interrupts here.
+	 */
+	memset(vgic_cpu->vgic_eisr, 0, sizeof(vgic_cpu->vgic_eisr[0]) * 2);
+
 	return level_pending;
 }
 

Patches currently in stable-queue which might be from [email protected] are

queue-3.14/arm64-kvm-fix-hcr-setting-for-32bit-guests.patch queue-3.14/arm64-kvm-do-not-use-pgd_index-to-index-stage-2-pgd.patch queue-3.14/arm64-kvm-fix-tlb-invalidation-by-ipa-vmid.patch queue-3.14/arm-arm64-kvm-keep-elrsr-aisr-in-sync-with-software-model.patch queue-3.14/arm-arm64-kvm-require-in-kernel-vgic-for-the-arch-timers.patch