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clk: qcom: Set CLK_SET_RATE_PARENT on ce1 clocks

PATCH In review Stephen Boyd 2 participants 2 messages Jul 15, 2015

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Stephen Boyd

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#0 lore raw

PATCH 1/1 clk: qcom: Set CLK_SET_RATE_PARENT on ce1 clocks

The other ce clocks have the flag set, but ce1 doesn't, so clk_set_rate() doesn't propagate up the tree to the ce1_src_clk. Set the flag as this is supported.

Reported-by Bjorn Andersson <[email protected]>
Fixes 02824653200b ("clk: qcom: Add APQ8084 Global Clock Controller support")
Fixes d33faa9ead8d ("clk: qcom: Add support for MSM8974's global clock controller (GCC)")
Signed-off-by Stephen Boyd <[email protected]>
---
 drivers/clk/qcom/gcc-apq8084.c | 1 +
 drivers/clk/qcom/gcc-msm8974.c | 1 +
 2 files changed, 2 insertions(+)
drivers/clk/qcom/gcc-apq8084.c +1 -0
index 05b7a25b80e8..3563019b8e3c 100644
@@ -2105,6 +2105,7 @@ static struct clk_branch gcc_ce1_clk = {
 				"ce1_clk_src",
 			},
 			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
drivers/clk/qcom/gcc-msm8974.c +1 -0
index 2c289702119f..2bcf87538f9d 100644
@@ -1783,6 +1783,7 @@ static struct clk_branch gcc_ce1_clk = {
 				"ce1_clk_src",
 			},
 			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
Signature · 2 lines
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Tested-by on v1 1/1
#1 lore raw
Quoted 9 lines · Stephen Boyd

The other ce clocks have the flag set, but ce1 doesn't, so clk_set_rate() doesn't propagate up the tree to the ce1_src_clk. Set the flag as this is supported.

Reported-by Bjorn Andersson <[email protected]>
Fixes 02824653200b ("clk: qcom: Add APQ8084 Global Clock Controller support")
Fixes d33faa9ead8d ("clk: qcom: Add support for MSM8974's global clock controller (GCC)")
Signed-off-by Stephen Boyd <[email protected]>

---

Thanks, test ok on 8974.

Tested-by Bjorn Andersson <[email protected]>

Regards,
Bjorn