ARM: AM335x: dts: Fix wrong GPMC size mapping for omaps

PATCH Applied Daniel Schultz 2 participants 4 messages Jul 15, 2015 – Jul 16, 2015

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Arm (32-bit) Arm sub-architectures

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Daniel Schultz

author

2015-07-15 13:48 UTC #0 lore raw

PATCH 1/2 ARM: AM335x: dts: Fix wrong GPMC size mapping for omaps

Patch is based on Linux upstream patch:
commit e2c5eb78a3cc9b0d69ae924c33da50a4cd6d1fa4
Author: Tony Lindgren <[email protected]>

The GPMC binding is obviously very confusing as the values are all over the place. People seem to confuse the GPMC partition size for the chip select, and the device IO size within the GPMC partition easily.

The ranges entry contains the GPMC partition size. And the reg entry contains the size of the IO registers of the device connected to the GPMC.

Let's fix the issue according to the following table:

Device GPMC partition size Device IO size
connected in the ranges entry in the reg entry

NAND 0x01000000 (16MB) 4
16550 0x01000000 (16MB) 8
smc91x 0x01000000 (16MB) 0xf
smc911x 0x01000000 (16MB) 0xff
OneNAND 0x01000000 (16MB) 0x20000 (128KB)
16MB NOR 0x01000000 (16MB) 0x01000000 (16MB)
32MB NOR 0x02000000 (32MB) 0x02000000 (32MB)
64MB NOR 0x04000000 (64MB) 0x04000000 (64MB)
128MB NOR 0x08000000 (128MB) 0x08000000 (128MB)
256MB NOR 0x10000000 (256MB) 0x10000000 (256MB)

Let's also add comments to the fixed entries while at it.

Signed-off-by Daniel Schultz <[email protected]>

---
 arch/arm/dts/am335x-phytec-phycard-som.dtsi | 4 ++--
 arch/arm/dts/am335x-phytec-phycore-som.dtsi | 4 ++--
 arch/arm/dts/am335x-phytec-phyflex-som.dtsi | 4 ++--
 3 files changed, 6 insertions(+), 6 deletions(-)

arch/arm/dts/am335x-phytec-phycard-som.dtsi +2 -2

index 1f1036f..c0b2456 100644
@@ -144,9 +144,9 @@
 	status = "okay";
 	pinctrl-names = "default";
 	pinctrl-0 = <&nandflash_pins_s0>;
-	ranges = <0 0 0x08000000 0x10000000>;	/* CS0: NAND */
+	ranges = <0 0 0x08000000 0x1000000>;	/* CS0: 16MB for NAND */
 	nand: nand@0,0 {
-		reg = <0 0 0>; /* CS0, offset 0 */
+		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
 		nand-bus-width = <8>;
 		ti,nand-ecc-opt = "bch8";
 		gpmc,device-nand = "true";

arch/arm/dts/am335x-phytec-phycore-som.dtsi +2 -2

index ed8e257..5cc4455 100644
@@ -228,9 +228,9 @@
 	status = "okay";
 	pinctrl-names = "default";
 	pinctrl-0 = <&nandflash_pins_s0>;
-	ranges = <0 0 0x08000000 0x10000000>;	/* CS0: NAND */
+	ranges = <0 0 0x08000000 0x1000000>;	/* CS0: 16MB for NAND */
 	nand: nand@0,0 {
-		reg = <0 0 0>; /* CS0, offset 0 */
+		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
 		nand-bus-width = <8>;
 		ti,nand-ecc-opt = "bch8";
 		gpmc,device-nand = "true";

arch/arm/dts/am335x-phytec-phyflex-som.dtsi +2 -2

index fc9c9ba..71f0a97 100644
@@ -240,9 +240,9 @@
 	status = "okay";
 	pinctrl-names = "default";
 	pinctrl-0 = <&nandflash_pins_s0>;
-	ranges = <0 0 0x08000000 0x10000000>;	/* CS0: NAND */
+	ranges = <0 0 0x08000000 0x1000000>;	/* CS0: 16MB for NAND */
 	nand: nand@0,0 {
-		reg = <0 0 0>; /* CS0, offset 0 */
+		reg = <0 0 4>; /* CS0, offset 0, IO size 4  */
 		nand-bus-width = <8>;
 		ti,nand-ecc-opt = "bch8";
 		gpmc,device-nand = "true";

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Daniel Schultz

author

2015-07-15 13:48 UTC #1 lore raw

PATCH 2/2 ARM: am335x: Changed timer

The dmtimer0 is too inaccurate to be used for measurements. We switch to the more accurate dmtimer2.

Signed-off-by Daniel Schultz <[email protected]>

---
 arch/arm/mach-omap/Kconfig                       |  4 +-
 arch/arm/mach-omap/Makefile                      |  2 +-
 arch/arm/mach-omap/dmtimer0.c                    | 85 ----------------------
 arch/arm/mach-omap/dmtimer2.c                    | 89 ++++++++++++++++++++++++
 arch/arm/mach-omap/include/mach/am33xx-silicon.h |  3 +
 5 files changed, 95 insertions(+), 88 deletions(-)
 delete mode 100644 arch/arm/mach-omap/dmtimer0.c
 create mode 100644 arch/arm/mach-omap/dmtimer2.c

arch/arm/mach-omap/Kconfig +2 -2

index af35975..0372906 100644
@@ -43,7 +43,7 @@ config ARCH_AM33XX
 	select CPU_V7
 	select GENERIC_GPIO
 	select OFTREE
-	select OMAP_CLOCK_SOURCE_DMTIMER0
+	select OMAP_CLOCK_SOURCE_DMTIMER2
 	help
 	  Say Y here if you are using Texas Instrument's AM33xx based platform

@@ -51,7 +51,7 @@ config ARCH_AM33XX
 config OMAP_CLOCK_SOURCE_S32K
 	bool
 
-config OMAP_CLOCK_SOURCE_DMTIMER0
+config OMAP_CLOCK_SOURCE_DMTIMER2
 	bool
 
 config OMAP_GPMC

arch/arm/mach-omap/Makefile +1 -1

index 65072b9..e518755 100644
@@ -18,7 +18,7 @@
 obj-$(CONFIG_ARCH_OMAP) += syslib.o omap_devices.o omap_generic.o omap_fb.o
 pbl-$(CONFIG_ARCH_OMAP) += syslib.o
 obj-$(CONFIG_OMAP_CLOCK_SOURCE_S32K) += s32k_clksource.o
-obj-$(CONFIG_OMAP_CLOCK_SOURCE_DMTIMER0) += dmtimer0.o
+obj-$(CONFIG_OMAP_CLOCK_SOURCE_DMTIMER2) += dmtimer2.o
 obj-$(CONFIG_ARCH_OMAP3) += omap3_generic.o auxcr.o
 pbl-$(CONFIG_ARCH_OMAP3) += omap3_generic.o auxcr.o
 obj-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o

arch/arm/mach-omap/dmtimer0.c deleted +0 ~~-85~~

85 lines not on this page · raw message

arch/arm/mach-omap/dmtimer2.c new file +89 -0

89 lines not on this page · raw message

arch/arm/mach-omap/include/mach/am33xx-silicon.h +3 -0

index 7c209ec..ee0b846 100644
@@ -62,6 +62,9 @@
 
 /* DTMTimer0 */
 #define AM33XX_DMTIMER0_BASE		(AM33XX_L4_WKUP_BASE + 0x205000)
+/* DMTIimer2 */
+#define AM33XX_DMTIMER2_BASE		(AM33XX_L4_PER_BASE + 0x40000)
+#define AM33XX_CM_DPLL			(AM33XX_L4_WKUP_BASE + 0x200500)
 
 /* PRM */
 #define AM33XX_PRM_BASE			(AM33XX_L4_WKUP_BASE + 0x200000)

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Sascha Hauer

2015-07-16 06:30 UTC #2 lore raw

Re: [PATCH 2/2] ARM: am335x: Changed timer

arch/arm/mach-omap/dmtimer0.c

Quoted 50 lines · Daniel Schultz

The dmtimer0 is too inaccurate to be used for measurements. We switch to the more accurate dmtimer2.

Signed-off-by Daniel Schultz <[email protected]>

---
 arch/arm/mach-omap/Kconfig                       |  4 +-
 arch/arm/mach-omap/Makefile                      |  2 +-
 arch/arm/mach-omap/dmtimer0.c                    | 85 ----------------------
 arch/arm/mach-omap/dmtimer2.c                    | 89 ++++++++++++++++++++++++
 arch/arm/mach-omap/include/mach/am33xx-silicon.h |  3 +
 5 files changed, 95 insertions(+), 88 deletions(-)
 delete mode 100644 arch/arm/mach-omap/dmtimer0.c
 create mode 100644 arch/arm/mach-omap/dmtimer2.c

arch/arm/mach-omap/Kconfig +2 -2

index af35975..0372906 100644
@@ -43,7 +43,7 @@ config ARCH_AM33XX
 	select CPU_V7
 	select GENERIC_GPIO
 	select OFTREE
-	select OMAP_CLOCK_SOURCE_DMTIMER0
+	select OMAP_CLOCK_SOURCE_DMTIMER2
 	help
 	  Say Y here if you are using Texas Instrument's AM33xx based platform

@@ -51,7 +51,7 @@ config ARCH_AM33XX
 config OMAP_CLOCK_SOURCE_S32K
 	bool
 
-config OMAP_CLOCK_SOURCE_DMTIMER0
+config OMAP_CLOCK_SOURCE_DMTIMER2
 	bool
 
 config OMAP_GPMC

arch/arm/mach-omap/Makefile +1 -1

index 65072b9..e518755 100644
@@ -18,7 +18,7 @@
 obj-$(CONFIG_ARCH_OMAP) += syslib.o omap_devices.o omap_generic.o omap_fb.o
 pbl-$(CONFIG_ARCH_OMAP) += syslib.o
 obj-$(CONFIG_OMAP_CLOCK_SOURCE_S32K) += s32k_clksource.o
-obj-$(CONFIG_OMAP_CLOCK_SOURCE_DMTIMER0) += dmtimer0.o
+obj-$(CONFIG_OMAP_CLOCK_SOURCE_DMTIMER2) += dmtimer2.o
 obj-$(CONFIG_ARCH_OMAP3) += omap3_generic.o auxcr.o
 pbl-$(CONFIG_ARCH_OMAP3) += omap3_generic.o auxcr.o
 obj-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o

arch/arm/mach-omap/dmtimer0.c +0 -0

If you're renaming this, can you rename to dmtimer.c please? The instance number shouldn't be in the filename. While at it you could also use a static void *base instead of the address define directly. This will make it more easy to support other timers later.

Sascha

Signature · 9 lines

Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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Sascha Hauer

Applied

2015-07-16 07:34 UTC #3 lore raw

In reply to Daniel Schultz

Quoted 29 lines · Daniel Schultz

Patch is based on Linux upstream patch:
commit e2c5eb78a3cc9b0d69ae924c33da50a4cd6d1fa4
Author: Tony Lindgren <[email protected]>
The GPMC binding is obviously very confusing as the values are all over the place. People seem to confuse the GPMC partition size for the chip select, and the device IO size within the GPMC partition easily.
The ranges entry contains the GPMC partition size. And the reg entry contains the size of the IO registers of the device connected to the GPMC.
Let's fix the issue according to the following table:
Device GPMC partition size Device IO size
connected in the ranges entry in the reg entry
NAND 0x01000000 (16MB) 4
16550 0x01000000 (16MB) 8
smc91x 0x01000000 (16MB) 0xf
smc911x 0x01000000 (16MB) 0xff
OneNAND 0x01000000 (16MB) 0x20000 (128KB)
16MB NOR 0x01000000 (16MB) 0x01000000 (16MB)
32MB NOR 0x02000000 (32MB) 0x02000000 (32MB)
64MB NOR 0x04000000 (64MB) 0x04000000 (64MB)
128MB NOR 0x08000000 (128MB) 0x08000000 (128MB)
256MB NOR 0x10000000 (256MB) 0x10000000 (256MB)

Quoted 3 lines

Let's also add comments to the fixed entries while at it.
Signed-off-by Daniel Schultz <[email protected]>

Applied this one, thanks

Sascha

Signature · 9 lines

Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

_______________________________________________
barebox mailing list
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http://lists.infradead.org/mailman/listinfo/barebox