Remove struct clk based provider APIs
Subsystems (26)
cover Remove struct clk based provider APIs
This is the beginning of an effort to remove struct clk from provider drivers. I've split the patches out to be per-SoC to make review easier, except for the automated conversions done by Coccinelle. Those go into one patch.
Stephen Boyd (26):
clk: Add clk_hw_get_num_parents()
clk: Replace __clk_get_num_parents with clk_hw_get_num_parents()
clk: Remove __clk_get_num_parents()
clk: Add clk_hw_get_flags()
clk: Convert __clk_get_flags() to clk_hw_get_flags()
clk: Add clk_hw_*() API for use by providers
clk: ti: Remove CLK_IS_BASIC check
ARM: OMAP: Convert __clk_get_rate() to provider/consumer APIs
MIPS: alchemy: Convert to clk_hw based provider APIs
clk: at91: Convert to clk_hw based provider APIs
clk: bcm: Convert to clk_hw based provider APIs
clk: Convert basic types to clk_hw based provider APIs
clk: mmp: Convert to clk_hw based provider APIs
clk: mvebu: Convert to clk_hw based provider APIs
clk: stm32f4: Convert to clk_hw based provider APIs
clk: qcom: Convert to clk_hw based provider APIs
clk: rockchip: Convert to clk_hw based provider APIs
clk: samsung: Convert to clk_hw based provider APIs
clk: sirf: Convert to clk_hw based provider APIs
clk: spear: Convert to clk_hw based provider APIs
clk: sunxi: Convert to clk_hw based provider APIs
clk: tegra: Convert to clk_hw based provider APIs
clk: tegra: Convert to clk_hw based provider APIs
clk: versatile: Convert to clk_hw based provider APIs drm/msm/dsi: Convert to clk_hw based provider APIs
clk: Remove unused provider APIs
arch/arm/mach-omap2/clkt34xx_dpll3m2.c | 6 +- arch/mips/alchemy/common/clock.c | 12 ++-- drivers/clk/at91/clk-peripheral.c | 6 +- drivers/clk/at91/clk-programmable.c | 10 ++-- drivers/clk/at91/clk-usb.c | 14 ++--- drivers/clk/bcm/clk-kona.c | 20 +++---- drivers/clk/clk-cdce706.c | 2 +- drivers/clk/clk-composite.c | 18 +++--- drivers/clk/clk-divider.c | 8 +-- drivers/clk/clk-fixed-factor.c | 5 +- drivers/clk/clk-mux.c | 2 +- drivers/clk/clk-si5351.c | 4 +- drivers/clk/clk-stm32f4.c | 5 +- drivers/clk/clk.c | 93 +++++++++++++++--------------- drivers/clk/mmp/clk-gate.c | 3 +- drivers/clk/mmp/clk-mix.c | 43 +++++++------- drivers/clk/mvebu/clk-cpu.c | 6 +- drivers/clk/qcom/clk-pll.c | 8 +-- drivers/clk/qcom/clk-rcg.c | 23 ++++---- drivers/clk/qcom/clk-rcg2.c | 33 +++++------ drivers/clk/qcom/common.c | 2 +- drivers/clk/qcom/mmcc-msm8960.c | 12 ++-- drivers/clk/rockchip/clk-pll.c | 18 +++--- drivers/clk/samsung/clk-cpu.c | 4 +- drivers/clk/samsung/clk-s3c2410-dclk.c | 2 +- drivers/clk/shmobile/clk-div6.c | 4 +- drivers/clk/sirf/clk-common.c | 12 ++-- drivers/clk/spear/clk-vco-pll.c | 2 +- drivers/clk/st/clk-flexgen.c | 2 +- drivers/clk/sunxi/clk-factors.c | 14 ++--- drivers/clk/sunxi/clk-sun6i-ar100.c | 10 ++-- drivers/clk/sunxi/clk-sunxi.c | 14 ++--- drivers/clk/tegra/clk-emc.c | 10 ++-- drivers/clk/tegra/clk-pll.c | 10 ++-- drivers/clk/ti/autoidle.c | 14 ++--- drivers/clk/ti/clk.c | 4 +- drivers/clk/ti/clkt_dpll.c | 11 ++-- drivers/clk/ti/clock.h | 2 +- drivers/clk/ti/clockdomain.c | 4 +- drivers/clk/ti/divider.c | 8 +-- drivers/clk/ti/dpll.c | 4 +- drivers/clk/ti/dpll3xxx.c | 33 +++++------ drivers/clk/ti/dpll44xx.c | 4 +- drivers/clk/ti/gate.c | 6 +- drivers/clk/ti/interface.c | 2 +- drivers/clk/ti/mux.c | 2 +- drivers/clk/versatile/clk-sp810.c | 2 +- drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c | 4 +- include/linux/clk-provider.h | 15 +++-- 49 files changed, 267 insertions(+), 285 deletions(-)
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH 1/26 clk: Add clk_hw_get_num_parents()
Most provider drivers don't need to deal with struct clk, but they may want to call __clk_get_num_parents() and so they have to get the struct clk out of struct clk_hw so they can ask the framework for the number of parents. Hide this all behind a clk_hw specific API.
--- drivers/clk/clk.c | 6 ++++++ include/linux/clk-provider.h | 1 + 2 files changed, 7 insertions(+)
drivers/clk/clk.c +6 -0
@@ -289,6 +289,12 @@ u8 __clk_get_num_parents(struct clk *clk) }EXPORT_SYMBOL_GPL (__clk_get_num_parents); +unsigned int clk_hw_get_num_parents (struct clk_hw *hw) +{ +return hw->core->num_parents; +} +EXPORT_SYMBOL_GPL (clk_hw_get_num_parents); +struct clk *__clk_get_parent (struct clk *clk) {if (!clk)
include/linux/clk-provider.h +1 -0
@@ -609,6 +609,7 @@ void devm_clk_unregister(struct device *dev, struct clk *clk);const char *__clk_get_name (struct clk *clk);struct clk_hw *__clk_get_hw (struct clk *clk);u8 __clk_get_num_parents (struct clk *clk); +unsigned int clk_hw_get_num_parents (struct clk_hw *hw);struct clk *__clk_get_parent (struct clk *clk);struct clk *clk_get_parent_by_index (struct clk *clk,u8 index);unsigned int __clk_get_enable_count (struct clk *clk);
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH 2/26 clk: Replace __clk_get_num_parents with clk_hw_get_num_parents()
In reply to Stephen BoydMostly converted with the following semantic patch:
@@
struct clk_hw *E;
@@
-__clk_get_num_parents(E->clk)
+clk_hw_get_num_parents(E)
--- drivers/clk/at91/clk-programmable.c | 2 +- drivers/clk/at91/clk-usb.c | 2 +- drivers/clk/clk-composite.c | 2 +- drivers/clk/clk-mux.c | 2 +- drivers/clk/mmp/clk-mix.c | 8 ++++---- drivers/clk/qcom/clk-rcg.c | 4 ++-- drivers/clk/qcom/clk-rcg2.c | 2 +- drivers/clk/qcom/common.c | 2 +- drivers/clk/qcom/mmcc-msm8960.c | 2 +- drivers/clk/samsung/clk-s3c2410-dclk.c | 2 +- drivers/clk/shmobile/clk-div6.c | 4 ++-- drivers/clk/sunxi/clk-factors.c | 2 +- drivers/clk/sunxi/clk-sun6i-ar100.c | 2 +- drivers/clk/sunxi/clk-sunxi.c | 2 +- drivers/clk/ti/mux.c | 2 +- 15 files changed, 20 insertions(+), 20 deletions(-)
drivers/clk/at91/clk-programmable.c +1 -1
@@ -64,7 +64,7 @@ static int clk_programmable_determine_rate(struct clk_hw *hw,int shift;int i; -for (i =0 ; i <__clk_get_num_parents (hw->clk); i++) { +for (i =0 ; i <clk_hw_get_num_parents (hw); i++) { parent =clk_get_parent_by_index (hw->clk, i);if (!parent)continue ;
drivers/clk/at91/clk-usb.c +1 -1
@@ -66,7 +66,7 @@ static int at91sam9x5_clk_usb_determine_rate(struct clk_hw *hw,int tmp_diff;int i; -for (i =0 ; i <__clk_get_num_parents (hw->clk); i++) { +for (i =0 ; i <clk_hw_get_num_parents (hw); i++) {int div; parent =clk_get_parent_by_index (hw->clk, i);
drivers/clk/clk-composite.c +1 -1
@@ -92,7 +92,7 @@ static int clk_composite_determine_rate(struct clk_hw *hw,return 0 ; } -for (i =0 ; i <__clk_get_num_parents (mux_hw->clk); i++) { +for (i =0 ; i <clk_hw_get_num_parents (mux_hw); i++) { parent =clk_get_parent_by_index (mux_hw->clk, i);if (!parent)continue ;
drivers/clk/clk-mux.c +1 -1
@@ -31,7 +31,7 @@static u8 clk_mux_get_parent (struct clk_hw *hw) {struct clk_mux *mux =to_clk_mux (hw); -int num_parents =__clk_get_num_parents (hw->clk); +int num_parents =clk_hw_get_num_parents (hw);u32 val;/*
drivers/clk/mmp/clk-mix.c +4 -4
@@ -63,7 +63,7 @@ static unsigned int _get_div(struct mmp_clk_mix *mix, unsigned int val)static unsigned int _get_mux (struct mmp_clk_mix *mix,unsigned int val) { -int num_parents =__clk_get_num_parents (mix->hw.clk); +int num_parents =clk_hw_get_num_parents (hw);int i;if (mix->mux_flags &CLK_MUX_INDEX_BIT )
@@ -241,7 +241,7 @@ static int mmp_clk_mix_determine_rate(struct clk_hw *hw, } } }else { -for (i =0 ; i <__clk_get_num_parents (mix_clk); i++) { +for (i =0 ; i <clk_hw_get_num_parents (hw); i++) { parent =clk_get_parent_by_index (mix_clk, i); parent_rate =__clk_get_rate (parent); div_val_max =_get_maxdiv (mix);
@@ -408,13 +408,13 @@ static int mmp_clk_set_rate(struct clk_hw *hw, unsigned long rate,else return -EINVAL ; }else { -for (i =0 ; i <__clk_get_num_parents (mix_clk); i++) { +for (i =0 ; i <clk_hw_get_num_parents (hw); i++) { parent =clk_get_parent_by_index (mix_clk, i); parent_rate =__clk_get_rate (parent);if (parent_rate == best_parent_rate)break ; } -if (i <__clk_get_num_parents (mix_clk)) +if (i <clk_hw_get_num_parents (hw))return _set_rate (mix,_get_mux_val (mix, i),_get_div_val (mix, best_divisor),1 ,1 );else
drivers/clk/qcom/clk-rcg.c +2 -2
@@ -45,7 +45,7 @@ static u32 src_to_ns(struct src_sel *s, u8 src, u32 ns)static u8 clk_rcg_get_parent (struct clk_hw *hw) {struct clk_rcg *rcg =to_clk_rcg (hw); -int num_parents =__clk_get_num_parents (hw->clk); +int num_parents =clk_hw_get_num_parents (hw);u32 ns;int i, ret;
@@ -72,7 +72,7 @@ static int reg_to_bank(struct clk_dyn_rcg *rcg, u32 bank)static u8 clk_dyn_rcg_get_parent (struct clk_hw *hw) {struct clk_dyn_rcg *rcg =to_clk_dyn_rcg (hw); -int num_parents =__clk_get_num_parents (hw->clk); +int num_parents =clk_hw_get_num_parents (hw);u32 ns, reg;int bank;int i, ret;
drivers/clk/qcom/clk-rcg2.c +1 -1
@@ -63,7 +63,7 @@ static int clk_rcg2_is_enabled(struct clk_hw *hw)static u8 clk_rcg2_get_parent (struct clk_hw *hw) {struct clk_rcg2 *rcg =to_clk_rcg2 (hw); -int num_parents =__clk_get_num_parents (hw->clk); +int num_parents =clk_hw_get_num_parents (hw);u32 cfg;int i, ret;
drivers/clk/qcom/common.c +1 -1
@@ -46,7 +46,7 @@ EXPORT_SYMBOL_GPL(qcom_find_freq);int qcom_find_src_index (struct clk_hw *hw,const struct parent_map *map,u8 src) { -int i, num_parents =__clk_get_num_parents (hw->clk); +int i, num_parents =clk_hw_get_num_parents (hw);for (i =0 ; i < num_parents; i++)if (src == map[i].src)
drivers/clk/qcom/mmcc-msm8960.c +1 -1
@@ -510,7 +510,7 @@ static int pix_rdi_set_parent(struct clk_hw *hw, u8 index)u32 val;struct clk_pix_rdi *rdi =to_clk_pix_rdi (hw);struct clk *clk = hw->clk; -int num_parents =__clk_get_num_parents (hw->clk); +int num_parents =clk_hw_get_num_parents (hw);/* * These clocks select three inputs via two muxes. One mux selects
drivers/clk/samsung/clk-s3c2410-dclk.c +1 -1
@@ -61,7 +61,7 @@ struct s3c24xx_clkout {static u8 s3c24xx_clkout_get_parent (struct clk_hw *hw) {struct s3c24xx_clkout *clkout =to_s3c24xx_clkout (hw); -int num_parents =__clk_get_num_parents (hw->clk); +int num_parents =clk_hw_get_num_parents (hw);u32 val; val =readl_relaxed (S3C24XX_MISCCR ) >> clkout->shift;
drivers/clk/shmobile/clk-div6.c +2 -2
@@ -133,7 +133,7 @@ static u8 cpg_div6_clock_get_parent(struct clk_hw *hw) hw_index = (clk_readl (clock->reg) >> clock->src_shift) & (BIT (clock->src_width) -1 ); -for (i =0 ; i <__clk_get_num_parents (hw->clk); i++) { +for (i =0 ; i <clk_hw_get_num_parents (hw); i++) {if (clock->parents[i] == hw_index)return i; }
@@ -149,7 +149,7 @@ static int cpg_div6_clock_set_parent(struct clk_hw *hw, u8 index)u8 hw_index;u32 mask; -if (index >=__clk_get_num_parents (hw->clk)) +if (index >=clk_hw_get_num_parents (hw))return -EINVAL ; mask = ~((BIT (clock->src_width) -1 ) << clock->src_shift);
drivers/clk/sunxi/clk-factors.c +1 -1
@@ -87,7 +87,7 @@ static int clk_factors_determine_rate(struct clk_hw *hw,unsigned long parent_rate, best =0 , child_rate, best_child_rate =0 ;/* find the parent that can help provide the fastest rate <= rate */ - num_parents =__clk_get_num_parents (clk); + num_parents =clk_hw_get_num_parents (hw);for (i =0 ; i < num_parents; i++) { parent =clk_get_parent_by_index (clk, i);if (!parent)
drivers/clk/sunxi/clk-sun6i-ar100.c +1 -1
@@ -47,7 +47,7 @@ static unsigned long ar100_recalc_rate(struct clk_hw *hw,static int ar100_determine_rate (struct clk_hw *hw,struct clk_rate_request *req) { -int nparents =__clk_get_num_parents (hw->clk); +int nparents =clk_hw_get_num_parents (hw);long best_rate = -EINVAL ;int i;
drivers/clk/sunxi/clk-sunxi.c +1 -1
@@ -128,7 +128,7 @@ static int sun6i_ahb1_clk_determine_rate(struct clk_hw *hw,unsigned long parent_rate, best =0 , child_rate, best_child_rate =0 ;/* find the parent that can help provide the fastest rate <= rate */ - num_parents =__clk_get_num_parents (clk); + num_parents =clk_hw_get_num_parents (hw);for (i =0 ; i < num_parents; i++) { parent =clk_get_parent_by_index (clk, i);if (!parent)
drivers/clk/ti/mux.c +1 -1
@@ -31,7 +31,7 @@static u8 ti_clk_mux_get_parent (struct clk_hw *hw) {struct clk_mux *mux =to_clk_mux (hw); -int num_parents =__clk_get_num_parents (hw->clk); +int num_parents =clk_hw_get_num_parents (hw);u32 val;/*
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH 02/26] clk: Replace __clk_get_num_parents with clk_hw_get_num_parents()
Quoted 10 lines · On Fri, 31 Jul 2015 10:03:42 -0700 Stephen Boyd <[email protected]> wrote:
Mostly converted with the following semantic patch:
@@
structclk_hw*E;
@@(quoted diff) +1
-1-__clk_get_num_parents(E->clk) +clk_hw_get_num_parents(E)Cc Boris Brezillon <[email protected]>
Quoted 265 lines
Cc Chao Xie <[email protected]>Cc Krzysztof Kozlowski <[email protected]>Cc Javier Martinez Canillas <[email protected]>Cc Tomasz Figa <[email protected]>Cc Maxime Ripard <[email protected]>Cc "Emilio López" <[email protected]>Cc Tero Kristo <[email protected]>Cc Geert Uytterhoeven <[email protected]>Signed-off-by Stephen Boyd <[email protected]>--- drivers/clk/at91/clk-programmable.c | 2 +- drivers/clk/at91/clk-usb.c | 2 +- drivers/clk/clk-composite.c | 2 +- drivers/clk/clk-mux.c | 2 +- drivers/clk/mmp/clk-mix.c | 8 ++++---- drivers/clk/qcom/clk-rcg.c | 4 ++-- drivers/clk/qcom/clk-rcg2.c | 2 +- drivers/clk/qcom/common.c | 2 +- drivers/clk/qcom/mmcc-msm8960.c | 2 +- drivers/clk/samsung/clk-s3c2410-dclk.c | 2 +- drivers/clk/shmobile/clk-div6.c | 4 ++-- drivers/clk/sunxi/clk-factors.c | 2 +- drivers/clk/sunxi/clk-sun6i-ar100.c | 2 +- drivers/clk/sunxi/clk-sunxi.c | 2 +- drivers/clk/ti/mux.c | 2 +- 15 files changed, 20 insertions(+), 20 deletions(-)drivers/clk/at91/clk-programmable.c +1
-1@@ -64,7 +64,7 @@ static int clk_programmable_determine_rate(struct clk_hw *hw,int shift;int i; -for (i =0 ; i <__clk_get_num_parents (hw->clk); i++) { +for (i =0 ; i <clk_hw_get_num_parents (hw); i++) { parent =clk_get_parent_by_index (hw->clk, i);if (!parent)continue ;drivers/clk/at91/clk-usb.c +1
-1@@ -66,7 +66,7 @@ static int at91sam9x5_clk_usb_determine_rate(struct clk_hw *hw,int tmp_diff;int i; -for (i =0 ; i <__clk_get_num_parents (hw->clk); i++) { +for (i =0 ; i <clk_hw_get_num_parents (hw); i++) {int div; parent =clk_get_parent_by_index (hw->clk, i);drivers/clk/clk-composite.c +1
-1@@ -92,7 +92,7 @@ static int clk_composite_determine_rate(struct clk_hw *hw,return 0 ; } -for (i =0 ; i <__clk_get_num_parents (mux_hw->clk); i++) { +for (i =0 ; i <clk_hw_get_num_parents (mux_hw); i++) { parent =clk_get_parent_by_index (mux_hw->clk, i);if (!parent)continue ;drivers/clk/clk-mux.c +1
-1@@ -31,7 +31,7 @@static u8 clk_mux_get_parent (struct clk_hw *hw) {struct clk_mux *mux =to_clk_mux (hw); -int num_parents =__clk_get_num_parents (hw->clk); +int num_parents =clk_hw_get_num_parents (hw);u32 val;/* drivers/clk/mmp/clk-mix.c +4
-4@@ -63,7 +63,7 @@ static unsigned int _get_div(struct mmp_clk_mix *mix, unsigned int val)static unsigned int _get_mux (struct mmp_clk_mix *mix,unsigned int val) { -int num_parents =__clk_get_num_parents (mix->hw.clk); +int num_parents =clk_hw_get_num_parents (hw);int i;if (mix->mux_flags &CLK_MUX_INDEX_BIT )@@ -241,7 +241,7 @@ static int mmp_clk_mix_determine_rate(struct clk_hw *hw, } } }else { -for (i =0 ; i <__clk_get_num_parents (mix_clk); i++) { +for (i =0 ; i <clk_hw_get_num_parents (hw); i++) { parent =clk_get_parent_by_index (mix_clk, i); parent_rate =__clk_get_rate (parent); div_val_max =_get_maxdiv (mix);@@ -408,13 +408,13 @@ static int mmp_clk_set_rate(struct clk_hw *hw, unsigned long rate,else return -EINVAL ; }else { -for (i =0 ; i <__clk_get_num_parents (mix_clk); i++) { +for (i =0 ; i <clk_hw_get_num_parents (hw); i++) { parent =clk_get_parent_by_index (mix_clk, i); parent_rate =__clk_get_rate (parent);if (parent_rate == best_parent_rate)break ; } -if (i <__clk_get_num_parents (mix_clk)) +if (i <clk_hw_get_num_parents (hw))return _set_rate (mix,_get_mux_val (mix, i),_get_div_val (mix, best_divisor),1 ,1 );else drivers/clk/qcom/clk-rcg.c +2
-2@@ -45,7 +45,7 @@ static u32 src_to_ns(struct src_sel *s, u8 src, u32 ns)static u8 clk_rcg_get_parent (struct clk_hw *hw) {struct clk_rcg *rcg =to_clk_rcg (hw); -int num_parents =__clk_get_num_parents (hw->clk); +int num_parents =clk_hw_get_num_parents (hw);u32 ns;int i, ret;@@ -72,7 +72,7 @@ static int reg_to_bank(struct clk_dyn_rcg *rcg, u32 bank)static u8 clk_dyn_rcg_get_parent (struct clk_hw *hw) {struct clk_dyn_rcg *rcg =to_clk_dyn_rcg (hw); -int num_parents =__clk_get_num_parents (hw->clk); +int num_parents =clk_hw_get_num_parents (hw);u32 ns, reg;int bank;int i, ret;drivers/clk/qcom/clk-rcg2.c +1
-1@@ -63,7 +63,7 @@ static int clk_rcg2_is_enabled(struct clk_hw *hw)static u8 clk_rcg2_get_parent (struct clk_hw *hw) {struct clk_rcg2 *rcg =to_clk_rcg2 (hw); -int num_parents =__clk_get_num_parents (hw->clk); +int num_parents =clk_hw_get_num_parents (hw);u32 cfg;int i, ret;drivers/clk/qcom/common.c +1
-1@@ -46,7 +46,7 @@ EXPORT_SYMBOL_GPL(qcom_find_freq);int qcom_find_src_index (struct clk_hw *hw,const struct parent_map *map,u8 src) { -int i, num_parents =__clk_get_num_parents (hw->clk); +int i, num_parents =clk_hw_get_num_parents (hw);for (i =0 ; i < num_parents; i++)if (src == map[i].src)drivers/clk/qcom/mmcc-msm8960.c +1
-1@@ -510,7 +510,7 @@ static int pix_rdi_set_parent(struct clk_hw *hw, u8 index)u32 val;struct clk_pix_rdi *rdi =to_clk_pix_rdi (hw);struct clk *clk = hw->clk; -int num_parents =__clk_get_num_parents (hw->clk); +int num_parents =clk_hw_get_num_parents (hw);/* * These clocks select three inputs via two muxes. One mux selects drivers/clk/samsung/clk-s3c2410-dclk.c +1
-1@@ -61,7 +61,7 @@ struct s3c24xx_clkout {static u8 s3c24xx_clkout_get_parent (struct clk_hw *hw) {struct s3c24xx_clkout *clkout =to_s3c24xx_clkout (hw); -int num_parents =__clk_get_num_parents (hw->clk); +int num_parents =clk_hw_get_num_parents (hw);u32 val; val =readl_relaxed (S3C24XX_MISCCR ) >> clkout->shift;drivers/clk/shmobile/clk-div6.c +2
-2@@ -133,7 +133,7 @@ static u8 cpg_div6_clock_get_parent(struct clk_hw *hw) hw_index = (clk_readl (clock->reg) >> clock->src_shift) & (BIT (clock->src_width) -1 ); -for (i =0 ; i <__clk_get_num_parents (hw->clk); i++) { +for (i =0 ; i <clk_hw_get_num_parents (hw); i++) {if (clock->parents[i] == hw_index)return i; }@@ -149,7 +149,7 @@ static int cpg_div6_clock_set_parent(struct clk_hw *hw, u8 index)u8 hw_index;u32 mask; -if (index >=__clk_get_num_parents (hw->clk)) +if (index >=clk_hw_get_num_parents (hw))return -EINVAL ; mask = ~((BIT (clock->src_width) -1 ) << clock->src_shift);drivers/clk/sunxi/clk-factors.c +1
-1@@ -87,7 +87,7 @@ static int clk_factors_determine_rate(struct clk_hw *hw,unsigned long parent_rate, best =0 , child_rate, best_child_rate =0 ;/* find the parent that can help provide the fastest rate <= rate */ - num_parents =__clk_get_num_parents (clk); + num_parents =clk_hw_get_num_parents (hw);for (i =0 ; i < num_parents; i++) { parent =clk_get_parent_by_index (clk, i);if (!parent)drivers/clk/sunxi/clk-sun6i-ar100.c +1
-1@@ -47,7 +47,7 @@ static unsigned long ar100_recalc_rate(struct clk_hw *hw,static int ar100_determine_rate (struct clk_hw *hw,struct clk_rate_request *req) { -int nparents =__clk_get_num_parents (hw->clk); +int nparents =clk_hw_get_num_parents (hw);long best_rate = -EINVAL ;int i;drivers/clk/sunxi/clk-sunxi.c +1
-1@@ -128,7 +128,7 @@ static int sun6i_ahb1_clk_determine_rate(struct clk_hw *hw,unsigned long parent_rate, best =0 , child_rate, best_child_rate =0 ;/* find the parent that can help provide the fastest rate <= rate */ - num_parents =__clk_get_num_parents (clk); + num_parents =clk_hw_get_num_parents (hw);for (i =0 ; i < num_parents; i++) { parent =clk_get_parent_by_index (clk, i);if (!parent)drivers/clk/ti/mux.c +1
-1@@ -31,7 +31,7 @@static u8 ti_clk_mux_get_parent (struct clk_hw *hw) {struct clk_mux *mux =to_clk_mux (hw); -int num_parents =__clk_get_num_parents (hw->clk); +int num_parents =clk_hw_get_num_parents (hw);u32 val;/*
Signature · 3 lines
Boris Brezillon, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com
Re: [PATCH 02/26] clk: Replace __clk_get_num_parents with clk_hw_get_num_parents()
In reply to Stephen Boyddrivers/clk/mmp/clk-mix.c static unsigned int _get_div(struct mmp_clk_mix *mix, unsigned int val) · line 66
Quoted 10 lines · Stephen Boyd
drivers/clk/mmp/clk-mix.c +1
-1@@ -63,7 +63,7 @@ static unsigned int _get_div(struct mmp_clk_mix *mix, unsigned int val)static unsigned int _get_mux (struct mmp_clk_mix *mix,unsigned int val) { -int num_parents =__clk_get_num_parents (mix->hw.clk); +int num_parents =clk_hw_get_num_parents (hw);
Shouldn't this be:
int num_parents = clk_hw_get_num_parents(&mix->hw);
?
drivers/clk/mmp/clk-mix.c static unsigned int _get_div(struct mmp_clk_mix *mix, unsigned int val) · line 69
Quoted 3 lines
drivers/clk/mmp/clk-mix.c +0
-0int i;if (mix->mux_flags &CLK_MUX_INDEX_BIT )
With the above fixed
Signature · 2 lines
Thanks, Sylwester
Re: [PATCH 02/26] clk: Replace __clk_get_num_parents with clk_hw_get_num_parents()
Quoted 7 lines · Sylwester Nawrocki
Quoted 6 lines · Stephen Boyd
drivers/clk/mmp/clk-mix.c +0
-0@@ -63,7 +63,7 @@ static unsigned int _get_div(struct mmp_clk_mix *mix, unsigned int val)
Quoted 7 lines
drivers/clk/mmp/clk-mix.c static unsigned int _get_div(struct mmp_clk_mix *mix, unsigned int val) · line 66
Quoted 4 lines
drivers/clk/mmp/clk-mix.c +1
-1static unsigned int _get_mux (struct mmp_clk_mix *mix,unsigned int val) { -int num_parents =__clk_get_num_parents (mix->hw.clk); +int num_parents =clk_hw_get_num_parents (hw);Shouldn't this be:
int num_parents = clk_hw_get_num_parents(&mix->hw);
Yes thanks! I really gotta fix that script....
Here's the interdiff for this file:
drivers/clk/mmp/clk-mix.c +2 -2
@@ -63,7 +63,7 @@ static unsigned int _get_div(struct mmp_clk_mix *mix, unsigned int val)static unsigned int _get_mux (struct mmp_clk_mix *mix,unsigned int val) { -int num_parents =clk_hw_get_num_parents (hw); +int num_parents =clk_hw_get_num_parents (&mix->hw);int i;if (mix->mux_flags &CLK_MUX_INDEX_BIT )
@@ -116,7 +116,7 @@ static void _filter_clk_table(struct mmp_clk_mix *mix,struct clk_hw *parent, *hw;unsigned long parent_rate; - hw = &mix->hw + hw = &mix->hw;for (i =0 ; i < table_size; i++) { item = &table[i];
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH 02/26] clk: Replace __clk_get_num_parents with clk_hw_get_num_parents()
In reply to Stephen BoydReview
Quoted 8 lines · Stephen Boyd
Mostly converted with the following semantic patch:
@@
structclk_hw*E;
@@(quoted diff) +1
-1-__clk_get_num_parents(E->clk) +clk_hw_get_num_parents(E)
I don't understand why this is considered a clock provider API. How is a clock consumer, such as cpufreq, supposed to find out the number of parents or similar information, so that it knows what its options are for calling clk_set_parent()?
This is the caller I had in mind:
http://patchwork.ozlabs.org/patch/507619/
Surely asking the clock to describe itself is better than what that cpufreq driver currently does, which is to look in the device tree and make assumptions about how that maps to what the clock provider driver does...
-Scott
Re: [PATCH 02/26] clk: Replace __clk_get_num_parents with clk_hw_get_num_parents()
Quoted 15 lines · Scott Wood
Review
Quoted 8 lines · Stephen Boyd
Mostly converted with the following semantic patch:
@@
structclk_hw*E;
@@(quoted diff) +1
-1-__clk_get_num_parents(E->clk) +clk_hw_get_num_parents(E)I don't understand why this is considered a clock provider API. How is a clock consumer, such as cpufreq, supposed to find out the number of parents or similar information, so that it knows what its options are for calling
clk_set_parent()?
Quoted 7 lines
This is the caller I had in mind:
http://patchwork.ozlabs.org/patch/507619/Surely asking the clock to describe itself is better than what that cpufreq driver currently does, which is to look in the device tree and make assumptions about how that maps to what the clock provider driver does...
All the APIs that were converted were private to the common clock framework and in clk-provider.h, not clk.h. clk.h is the consumer API that's supported by more than just the common clock framework, so whatever we do for the consumer API needs to be put there.
For example, we recently added a clk_has_parent() API that can be used to probe for possible parents of a clock. Perhaps we need something else in this case so that consumers can iterate over each parent of a clock? Feel free to suggest a consumer API.
Is there any reason why we can't use DT OPPs for the code that you're patching here? At a quick glance it looks like we could leave this driver behind and move to cpufreq-dt.c and then use OPPs to populate the possible frequencies and affinity.
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH 02/26] clk: Replace __clk_get_num_parents with clk_hw_get_num_parents()
Quoted 26 lines · Stephen Boyd
Quoted 16 lines · Scott Wood
Review
Quoted 8 lines · Stephen Boyd
Mostly converted with the following semantic patch:
@@
structclk_hw*E;
@@(quoted diff) +1
-1-__clk_get_num_parents(E->clk) +clk_hw_get_num_parents(E)I don't understand why this is considered a clock provider API. How is a clock consumer, such as cpufreq, supposed to find out the number of parents
or similar information, so that it knows what its options are for callingclk_set_parent()?Quoted 8 lines
This is the caller I had in mind:
http://patchwork.ozlabs.org/patch/507619/Surely asking the clock to describe itself is better than what that cpufreq
driver currently does, which is to look in the device tree and make assumptions about how that maps to what the clock provider driver does...
Quoted 5 lines
All the APIs that were converted were private to the common clock framework and in
clk-provider.h, notclk.h.clk.his the consumer API that's supported by more than just the common clock framework, so whatever we do for the consumer API needs to be put there.
I realize that's the theory, though it didn't seem to be adhered to particularly closely (e.g. even lib/vsprintf.c includes clk-provider.h, for access to __clk_get_name), and indeed the entire way the API and struct are split seemed quite odd to me (and the out-of-date Documentation/clk.txt didn't help).
Quoted 4 lines
For example, we recently added a
clk_has_parent()API that can be used to probe for possible parents of a clock. Perhaps we need something else in this case so that consumers can iterate over each parent of a clock? Feel free to suggest a consumer API.
OK. The suggestion is that functions which are potentially useful to something other than the clock provider itself be moved to clk.h and operate on struct clk *. At a minimum, I need "get_name" and "get_num_parents" (I'll add a patch to do so on respin, if there's no objection to the concept), but some of the others are probably reasonable to expose as well.
Quoted 4 lines
Is there any reason why we can't use DT OPPs for the code that you're patching here? At a quick glance it looks like we could leave this driver behind and move to
cpufreq-dt.cand then use OPPs to populate the possible frequencies and affinity.
One reason is that I want to maintain compatibility with existing device trees.
However, even ignoring that, cpufreq-dt doesn't seem like a good fit. It requires specifying voltage, which is beyond the scope of the DFS mechanism on these chips.
It also requires assembling a list of valid frequencies in the device tree, which is not knowable at compile-time as it depends on how PLLs were configured in the reset control words, and in some cases the revision of the SoC due to errata -- and even if that information were constant, it would be extra maintenance work to keep the redundant information accurate, and if errors were introduced into the device tree we'd have the same sort of compatibility problems I'm trying to fix with
http://patchwork.ozlabs.org/patch/507621/
-Scott
Re: [PATCH 02/26] clk: Replace __clk_get_num_parents with clk_hw_get_num_parents()
Quoted 33 lines · Scott Wood
Quoted 26 lines · Stephen Boyd
Quoted 16 lines · Scott Wood
Review
Quoted 8 lines · Stephen Boyd
Mostly converted with the following semantic patch:
@@
structclk_hw*E;
@@(quoted diff) +1
-1-__clk_get_num_parents(E->clk) +clk_hw_get_num_parents(E)I don't understand why this is considered a clock provider API. How is a clock consumer, such as cpufreq, supposed to find out the number of parents
or similar information, so that it knows what its options are for callingclk_set_parent()?Quoted 8 lines
This is the caller I had in mind:
http://patchwork.ozlabs.org/patch/507619/Surely asking the clock to describe itself is better than what that cpufreq
driver currently does, which is to look in the device tree and make assumptions about how that maps to what the clock provider driver does...Quoted 5 lines
All the APIs that were converted were private to the common clock framework and in
clk-provider.h, notclk.h.clk.his the consumer API that's supported by more than just the common clock framework, so whatever we do for the consumer API needs to be put there.
Quoted 5 lines
I realize that's the theory, though it didn't seem to be adhered to particularly closely (e.g. even
lib/vsprintf.cincludesclk-provider.h, for access to__clk_get_name), and indeed the entire way the API and struct are split seemed quite odd to me (and the out-of-dateDocumentation/clk.txtdidn't help).
Yeah I think we need a clk_get_name() API in clk.h instead of __clk_get_name() in clk-provider.h. The consumer/provider split is still a work in progress.
Quoted 11 lines
Quoted 5 lines
For example, we recently added a
clk_has_parent()API that can be used to probe for possible parents of a clock. Perhaps we need something else in this case so that consumers can iterate over each parent of a clock? Feel free to suggest a consumer API.OK. The suggestion is that functions which are potentially useful to something other than the clock provider itself be moved to
clk.hand operate on struct clk *. At a minimum, I need "get_name" and "get_num_parents" (I'll add a patch to do so on respin, if there's no objection to the concept), but some of the others are probably reasonable to expose as well.
Sure, let's take up the review on the next spin of patches. Please include Russell on clk API patches too please, as he's the maintainer there.
Quoted 6 lines
Quoted 5 lines
Is there any reason why we can't use DT OPPs for the code that you're patching here? At a quick glance it looks like we could leave this driver behind and move to
cpufreq-dt.cand then use OPPs to populate the possible frequencies and affinity.
Quoted 6 lines
One reason is that I want to maintain compatibility with existing device trees.
However, even ignoring that, cpufreq-dt doesn't seem like a good fit. It requires specifying voltage, which is beyond the scope of the DFS mechanism on these chips.
Hm.. cpufreq-dt doesn't mandate voltage setting. Maybe I'm reading the code wrong though.
Quoted 10 lines
It also requires assembling a list of valid frequencies in the device tree, which is not knowable at compile-time as it depends on how PLLs were configured in the reset control words, and in some cases the revision of the SoC due to errata -- and even if that information were constant, it would be extra maintenance work to keep the redundant information accurate, and if errors were introduced into the device tree we'd have the same sort of compatibility problems I'm trying to fix with
http://patchwork.ozlabs.org/patch/507621/
Ok, fair enough. The v2 bindings for OPPs are still progressing and they're moving towards a way to consolidate data that might work here. I'm not sure though, Viresh is probably better to ask.
Just one more final thought, but what if the clock provider populated the OPPs for the CPU devices and the cpufreq-dt was used? I don't know how the code is structured or if this QorIQ clock controller is used for more than just CPU clocks, but that may be another option where provider APIs are available.
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH 02/26] clk: Replace __clk_get_num_parents with clk_hw_get_num_parents()
Quoted 10 lines · Stephen Boyd
Quoted 9 lines · Scott Wood
Quoted 4 lines · Stephen Boyd
Is there any reason why we can't use DT OPPs for the code that you're patching here? At a quick glance it looks like we could leave this driver behind and move to
cpufreq-dt.cand then use OPPs to populate the possible frequencies and affinity.One reason is that I want to maintain compatibility with existing device trees.
Quoted 7 lines
Quoted 4 lines
However, even ignoring that, cpufreq-dt doesn't seem like a good fit. It requires specifying voltage, which is beyond the scope of the DFS mechanism
on these chips.Hm.. cpufreq-dt doesn't mandate voltage setting. Maybe I'm reading the code wrong though.
I was referring to the device tree binding, but didn't look far enough to see the v2 binding.
Quoted 13 lines
Quoted 12 lines
It also requires assembling a list of valid frequencies in the device tree,
which is not knowable at compile-time as it depends on how PLLs were configured in the reset control words, and in some cases the revision of the
SoC due to errata -- and even if that information were constant, it would be
extra maintenance work to keep the redundant information accurate, and if errors were introduced into the device tree we'd have the same sort of compatibility problems I'm trying to fix with
http://patchwork.ozlabs.org/patch/507621/
Quoted 3 lines
Ok, fair enough. The v2 bindings for OPPs are still progressing and they're moving towards a way to consolidate data that might work here. I'm not sure though, Viresh is probably better to ask.
If you mean operating-points-v2, based on the current binding document, I'm not sure how that addresses the above issues.
Quoted 5 lines
Just one more final thought, but what if the clock provider populated the OPPs for the CPU devices and the cpufreq-dt was used? I don't know how the code is structured or if this QorIQ clock controller is used for more than just CPU clocks, but that may be another option where provider APIs are available.
I'm not sure how to do that, and it's not clear what the benefit would be on this hardware. Pretty much all we need the cpufreq driver to do is to look at a clock with multiple parents, and select from the options that are available.
-Scott
PATCH 3/26 clk: Remove __clk_get_num_parents()
In reply to Stephen Boyd... as all the users have been converted toclk_hw_get_num_parents() now.
--- drivers/clk/clk.c | 6 ------ include/linux/clk-provider.h | 1 - 2 files changed, 7 deletions(-)
drivers/clk/clk.c +0 -6
@@ -283,12 +283,6 @@ struct clk_hw *__clk_get_hw(struct clk *clk) }EXPORT_SYMBOL_GPL (__clk_get_hw); -u8 __clk_get_num_parents (struct clk *clk) -{ -return !clk ?0 : clk->core->num_parents; -} -EXPORT_SYMBOL_GPL (__clk_get_num_parents); -unsigned int clk_hw_get_num_parents (struct clk_hw *hw) {return hw->core->num_parents;
include/linux/clk-provider.h +0 -1
@@ -608,7 +608,6 @@ void devm_clk_unregister(struct device *dev, struct clk *clk);/* helper functions */ const char *__clk_get_name (struct clk *clk);struct clk_hw *__clk_get_hw (struct clk *clk); -u8 __clk_get_num_parents (struct clk *clk);unsigned int clk_hw_get_num_parents (struct clk_hw *hw);struct clk *__clk_get_parent (struct clk *clk);struct clk *clk_get_parent_by_index (struct clk *clk,u8 index);
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH 4/26 clk: Add clk_hw_get_flags()
In reply to Stephen Boyd--- drivers/clk/clk.c | 6 ++++++ include/linux/clk-provider.h | 1 + 2 files changed, 7 insertions(+)
drivers/clk/clk.c +6 -0
@@ -418,6 +418,12 @@ unsigned long __clk_get_flags(struct clk *clk) }EXPORT_SYMBOL_GPL (__clk_get_flags); +unsigned long clk_hw_get_flags (struct clk_hw *hw) +{ +return hw->core->flags; +} +EXPORT_SYMBOL_GPL (clk_hw_get_flags); +bool __clk_is_prepared (struct clk *clk) {if (!clk)
include/linux/clk-provider.h +1 -0
@@ -614,6 +614,7 @@ struct clk *clk_get_parent_by_index(struct clk *clk, u8 index);unsigned int __clk_get_enable_count (struct clk *clk);unsigned long __clk_get_rate (struct clk *clk);unsigned long __clk_get_flags (struct clk *clk); +unsigned long clk_hw_get_flags (struct clk_hw *hw);bool __clk_is_prepared (struct clk *clk);bool __clk_is_enabled (struct clk *clk);struct clk *__clk_lookup (const char *name);
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH 5/26 clk: Convert __clk_get_flags() to clk_hw_get_flags()
In reply to Stephen BoydMostly converted with the following snippet:
@@
struct clk_hw *E;
@@
-__clk_get_flags(E->clk)
+clk_hw_get_flags(E)
--- drivers/clk/clk-cdce706.c | 2 +- drivers/clk/clk-composite.c | 2 +- drivers/clk/clk-divider.c | 2 +- drivers/clk/clk-fixed-factor.c | 2 +- drivers/clk/clk-si5351.c | 4 ++-- drivers/clk/clk-stm32f4.c | 2 +- drivers/clk/qcom/clk-rcg.c | 2 +- drivers/clk/qcom/clk-rcg2.c | 2 +- drivers/clk/st/clk-flexgen.c | 2 +- drivers/clk/sunxi/clk-factors.c | 2 +- drivers/clk/sunxi/clk-sunxi.c | 2 +- drivers/clk/ti/clk.c | 4 ++-- drivers/clk/ti/clockdomain.c | 4 ++-- drivers/clk/ti/divider.c | 2 +- drivers/clk/ti/dpll.c | 4 ++-- drivers/clk/ti/dpll3xxx.c | 2 +- drivers/clk/ti/interface.c | 2 +- 17 files changed, 21 insertions(+), 21 deletions(-)
drivers/clk/clk-cdce706.c +1 -1
@@ -310,7 +310,7 @@ static long cdce706_divider_round_rate(struct clk_hw *hw, unsigned long rate,if (!mul) div =CDCE706_DIVIDER_DIVIDER_MAX ; -if (__clk_get_flags (hw->clk) &CLK_SET_RATE_PARENT ) { +if (clk_hw_get_flags (hw) &CLK_SET_RATE_PARENT ) {unsigned long best_diff = rate;unsigned long best_div =0 ;struct clk *gp_clk = cdce->clkin_clk[cdce->clkin[0 ].parent];
drivers/clk/clk-composite.c +1 -1
@@ -78,7 +78,7 @@ static int clk_composite_determine_rate(struct clk_hw *hw, mux_hw && mux_ops && mux_ops->set_parent) { req->best_parent_hw =NULL ; -if (__clk_get_flags (hw->clk) &CLK_SET_RATE_NO_REPARENT ) { +if (clk_hw_get_flags (hw) &CLK_SET_RATE_NO_REPARENT ) { parent =clk_get_parent (mux_hw->clk); req->best_parent_hw =__clk_get_hw (parent); req->best_parent_rate =__clk_get_rate (parent);
drivers/clk/clk-divider.c +1 -1
@@ -290,7 +290,7 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate, maxdiv =_get_maxdiv (table, width, flags); -if (!(__clk_get_flags (hw->clk) &CLK_SET_RATE_PARENT )) { +if (!(clk_hw_get_flags (hw) &CLK_SET_RATE_PARENT )) { parent_rate = *best_parent_rate; bestdiv =_div_round (table, parent_rate, rate, flags); bestdiv = bestdiv ==0 ?1 : bestdiv;
drivers/clk/clk-fixed-factor.c +1 -1
@@ -41,7 +41,7 @@ static long clk_factor_round_rate(struct clk_hw *hw, unsigned long rate, {struct clk_fixed_factor *fix =to_clk_fixed_factor (hw); -if (__clk_get_flags (hw->clk) &CLK_SET_RATE_PARENT ) { +if (clk_hw_get_flags (hw) &CLK_SET_RATE_PARENT ) {unsigned long best_parent; best_parent = (rate / fix->mult) * fix->div;
drivers/clk/clk-si5351.c +2 -2
@@ -663,7 +663,7 @@ static long si5351_msynth_round_rate(struct clk_hw *hw, unsigned long rate, divby4 =1 ;/* multisync can set pll */ -if (__clk_get_flags (hwdata->hw.clk) &CLK_SET_RATE_PARENT ) { +if (clk_hw_get_flags (hwdata->hw) &CLK_SET_RATE_PARENT ) {/* * find largest integer divider for max * vco frequency and given target rate
@@ -1013,7 +1013,7 @@ static long si5351_clkout_round_rate(struct clk_hw *hw, unsigned long rate, rate =SI5351_CLKOUT_MIN_FREQ ;/* request frequency if multisync master */ -if (__clk_get_flags (hwdata->hw.clk) &CLK_SET_RATE_PARENT ) { +if (clk_hw_get_flags (hwdata->hw) &CLK_SET_RATE_PARENT ) {/* use r divider for frequencies below 1MHz */ rdiv =SI5351_OUTPUT_CLK_DIV_1 ; while (rate < SI5351_MULTISYNTH_MIN_FREQ &&
drivers/clk/clk-stm32f4.c +1 -1
@@ -175,7 +175,7 @@ static long clk_apb_mul_round_rate(struct clk_hw *hw, unsigned long rate,if (readl (base +STM32F4_RCC_CFGR ) &BIT (am->bit_idx)) mult =2 ; -if (__clk_get_flags (hw->clk) &CLK_SET_RATE_PARENT ) { +if (clk_hw_get_flags (hw) &CLK_SET_RATE_PARENT ) {unsigned long best_parent = rate / mult; *prate =
drivers/clk/qcom/clk-rcg.c +1 -1
@@ -420,7 +420,7 @@ static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f,if (index <0 )return index; - clk_flags =__clk_get_flags (hw->clk); + clk_flags =clk_hw_get_flags (hw); p =clk_get_parent_by_index (hw->clk, index);if (clk_flags &CLK_SET_RATE_PARENT ) { rate = rate * f->pre_div;
drivers/clk/qcom/clk-rcg2.c +1 -1
@@ -192,7 +192,7 @@ static int _freq_tbl_determine_rate(struct clk_hw *hw,if (index <0 )return index; - clk_flags =__clk_get_flags (hw->clk); + clk_flags =clk_hw_get_flags (hw); p =clk_get_parent_by_index (hw->clk, index);if (clk_flags &CLK_SET_RATE_PARENT ) {if (f->pre_div) {
drivers/clk/st/clk-flexgen.c +1 -1
@@ -109,7 +109,7 @@ static long flexgen_round_rate(struct clk_hw *hw, unsigned long rate,/* Round div according to exact prate and wished rate */ div =clk_best_div (*prate, rate); -if (__clk_get_flags (hw->clk) &CLK_SET_RATE_PARENT ) { +if (clk_hw_get_flags (hw) &CLK_SET_RATE_PARENT ) { *prate = rate * div;return rate; }
drivers/clk/sunxi/clk-factors.c +1 -1
@@ -92,7 +92,7 @@ static int clk_factors_determine_rate(struct clk_hw *hw, parent =clk_get_parent_by_index (clk, i);if (!parent)continue ; -if (__clk_get_flags (clk) &CLK_SET_RATE_PARENT ) +if (clk_hw_get_flags (hw) &CLK_SET_RATE_PARENT ) parent_rate =__clk_round_rate (parent, req->rate);else parent_rate =__clk_get_rate (parent);
drivers/clk/sunxi/clk-sunxi.c +1 -1
@@ -133,7 +133,7 @@ static int sun6i_ahb1_clk_determine_rate(struct clk_hw *hw, parent =clk_get_parent_by_index (clk, i);if (!parent)continue ; -if (__clk_get_flags (clk) &CLK_SET_RATE_PARENT ) +if (clk_hw_get_flags (hw) &CLK_SET_RATE_PARENT ) parent_rate =__clk_round_rate (parent, req->rate);else parent_rate =__clk_get_rate (parent);
drivers/clk/ti/clk.c +2 -2
@@ -339,11 +339,11 @@ struct clk __init *ti_clk_register_clk(struct ti_clk *setup)if (!IS_ERR (clk)) { setup->clk = clk;if (setup->clkdm_name) { -if (__clk_get_flags (clk) &CLK_IS_BASIC ) { + clk_hw =__clk_get_hw (clk); +if (clk_hw_get_flags (clk_hw) &CLK_IS_BASIC ) {pr_warn ("can't setup clkdm for basic clk %s\n" , setup->name); }else { - clk_hw =__clk_get_hw (clk);to_clk_hw_omap (clk_hw)->clkdm_name = setup->clkdm_name;omap2_init_clk_clkdm (clk_hw);
drivers/clk/ti/clockdomain.c +2 -2
@@ -120,12 +120,12 @@ static void __init of_ti_clockdomain_setup(struct device_node *node) __func__, node->full_name, i, PTR_ERR(clk));continue ; } -if (__clk_get_flags (clk) &CLK_IS_BASIC ) { + clk_hw =__clk_get_hw (clk); +if (clk_hw_get_flags (clk_hw) &CLK_IS_BASIC ) {pr_warn ("can't setup clkdm for basic clk %s\n" ,__clk_get_name (clk));continue ; } - clk_hw =__clk_get_hw (clk);to_clk_hw_omap (clk_hw)->clkdm_name = clkdm_name;omap2_init_clk_clkdm (clk_hw); }
drivers/clk/ti/divider.c +1 -1
@@ -155,7 +155,7 @@ static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate, maxdiv =_get_maxdiv (divider); -if (!(__clk_get_flags (hw->clk) &CLK_SET_RATE_PARENT )) { +if (!(clk_hw_get_flags (hw) &CLK_SET_RATE_PARENT )) { parent_rate = *best_parent_rate; bestdiv =DIV_ROUND_UP (parent_rate, rate); bestdiv = bestdiv ==0 ?1 : bestdiv;
drivers/clk/ti/dpll.c +2 -2
@@ -163,7 +163,7 @@ static void __init _register_dpll(struct clk_hw *hw, clk =clk_register (NULL , &clk_hw->hw);if (!IS_ERR (clk)) { -omap2_init_clk_hw_omap_clocks (clk); +omap2_init_clk_hw_omap_clocks (&clk_hw->hw);of_clk_add_provider (node, of_clk_src_simple_get, clk);kfree (clk_hw->hw.init->parent_names);kfree (clk_hw->hw.init);
@@ -320,7 +320,7 @@ static void _register_dpll_x2(struct device_node *node,if (IS_ERR (clk)) {kfree (clk_hw); }else { -omap2_init_clk_hw_omap_clocks (clk); +omap2_init_clk_hw_omap_clocks (&clk_hw->hw);of_clk_add_provider (node, of_clk_src_simple_get, clk); } }
drivers/clk/ti/dpll3xxx.c +1 -1
@@ -711,7 +711,7 @@ static struct clk_hw_omap *omap3_find_clkoutx2_dpll(struct clk_hw *hw)do { parent =__clk_get_parent (hw->clk); hw =__clk_get_hw (parent); - }while (hw && (__clk_get_flags (hw->clk) &CLK_IS_BASIC )); + }while (hw && (clk_hw_get_flags (hw) &CLK_IS_BASIC ));if (!hw)break ; pclk =to_clk_hw_omap (hw);
drivers/clk/ti/interface.c +1 -1
@@ -63,7 +63,7 @@ static struct clk *_register_interface(struct device *dev, const char *name,if (IS_ERR (clk))kfree (clk_hw);else -omap2_init_clk_hw_omap_clocks (clk); +omap2_init_clk_hw_omap_clocks (&clk_hw->hw);return clk; }
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH 05/26] clk: Convert __clk_get_flags() to clk_hw_get_flags()
Quoted 9 lines · Stephen Boyd
Mostly converted with the following snippet:
@@
structclk_hw*E;
@@(quoted diff) +1
-1-__clk_get_flags(E->clk) +clk_hw_get_flags(E)
Quoted 7 lines
Cc Tero Kristo <[email protected]>Cc Maxime Ripard <[email protected]>Cc Max Filippov <[email protected]>Cc Sebastian Hesselbarth <[email protected]>Cc Daniel Thompson <[email protected]>Cc Coquelin <[email protected]>Signed-off-by Stephen Boyd <[email protected]>
I guess this already is in some branch to get merged. Anyway, of course you get my belated
for the clk-si5351 part.
Quoted 271 lines
--- drivers/clk/clk-cdce706.c | 2 +- drivers/clk/clk-composite.c | 2 +- drivers/clk/clk-divider.c | 2 +- drivers/clk/clk-fixed-factor.c | 2 +- drivers/clk/clk-si5351.c | 4 ++-- drivers/clk/clk-stm32f4.c | 2 +- drivers/clk/qcom/clk-rcg.c | 2 +- drivers/clk/qcom/clk-rcg2.c | 2 +- drivers/clk/st/clk-flexgen.c | 2 +- drivers/clk/sunxi/clk-factors.c | 2 +- drivers/clk/sunxi/clk-sunxi.c | 2 +- drivers/clk/ti/clk.c | 4 ++-- drivers/clk/ti/clockdomain.c | 4 ++-- drivers/clk/ti/divider.c | 2 +- drivers/clk/ti/dpll.c | 4 ++-- drivers/clk/ti/dpll3xxx.c | 2 +- drivers/clk/ti/interface.c | 2 +- 17 files changed, 21 insertions(+), 21 deletions(-)drivers/clk/clk-cdce706.c +1
-1@@ -310,7 +310,7 @@ static long cdce706_divider_round_rate(struct clk_hw *hw, unsigned long rate,if (!mul) div =CDCE706_DIVIDER_DIVIDER_MAX ; -if (__clk_get_flags (hw->clk) &CLK_SET_RATE_PARENT ) { +if (clk_hw_get_flags (hw) &CLK_SET_RATE_PARENT ) {unsigned long best_diff = rate;unsigned long best_div =0 ;struct clk *gp_clk = cdce->clkin_clk[cdce->clkin[0 ].parent];drivers/clk/clk-composite.c +1
-1@@ -78,7 +78,7 @@ static int clk_composite_determine_rate(struct clk_hw *hw, mux_hw && mux_ops && mux_ops->set_parent) { req->best_parent_hw =NULL ; -if (__clk_get_flags (hw->clk) &CLK_SET_RATE_NO_REPARENT ) { +if (clk_hw_get_flags (hw) &CLK_SET_RATE_NO_REPARENT ) { parent =clk_get_parent (mux_hw->clk); req->best_parent_hw =__clk_get_hw (parent); req->best_parent_rate =__clk_get_rate (parent);drivers/clk/clk-divider.c +1
-1@@ -290,7 +290,7 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate, maxdiv =_get_maxdiv (table, width, flags); -if (!(__clk_get_flags (hw->clk) &CLK_SET_RATE_PARENT )) { +if (!(clk_hw_get_flags (hw) &CLK_SET_RATE_PARENT )) { parent_rate = *best_parent_rate; bestdiv =_div_round (table, parent_rate, rate, flags); bestdiv = bestdiv ==0 ?1 : bestdiv;drivers/clk/clk-fixed-factor.c +1
-1@@ -41,7 +41,7 @@ static long clk_factor_round_rate(struct clk_hw *hw, unsigned long rate, {struct clk_fixed_factor *fix =to_clk_fixed_factor (hw); -if (__clk_get_flags (hw->clk) &CLK_SET_RATE_PARENT ) { +if (clk_hw_get_flags (hw) &CLK_SET_RATE_PARENT ) {unsigned long best_parent; best_parent = (rate / fix->mult) * fix->div;drivers/clk/clk-si5351.c +2
-2@@ -663,7 +663,7 @@ static long si5351_msynth_round_rate(struct clk_hw *hw, unsigned long rate, divby4 =1 ;/* multisync can set pll */ -if (__clk_get_flags (hwdata->hw.clk) &CLK_SET_RATE_PARENT ) { +if (clk_hw_get_flags (hwdata->hw) &CLK_SET_RATE_PARENT ) {/* * find largest integer divider for max * vco frequency and given target rate @@ -1013,7 +1013,7 @@ static long si5351_clkout_round_rate(struct clk_hw *hw, unsigned long rate, rate =SI5351_CLKOUT_MIN_FREQ ;/* request frequency if multisync master */ -if (__clk_get_flags (hwdata->hw.clk) &CLK_SET_RATE_PARENT ) { +if (clk_hw_get_flags (hwdata->hw) &CLK_SET_RATE_PARENT ) {/* use r divider for frequencies below 1MHz */ rdiv =SI5351_OUTPUT_CLK_DIV_1 ; while (rate < SI5351_MULTISYNTH_MIN_FREQ &&drivers/clk/clk-stm32f4.c +1
-1@@ -175,7 +175,7 @@ static long clk_apb_mul_round_rate(struct clk_hw *hw, unsigned long rate,if (readl (base +STM32F4_RCC_CFGR ) &BIT (am->bit_idx)) mult =2 ; -if (__clk_get_flags (hw->clk) &CLK_SET_RATE_PARENT ) { +if (clk_hw_get_flags (hw) &CLK_SET_RATE_PARENT ) {unsigned long best_parent = rate / mult; *prate =drivers/clk/qcom/clk-rcg.c +1
-1@@ -420,7 +420,7 @@ static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f,if (index <0 )return index; - clk_flags =__clk_get_flags (hw->clk); + clk_flags =clk_hw_get_flags (hw); p =clk_get_parent_by_index (hw->clk, index);if (clk_flags &CLK_SET_RATE_PARENT ) { rate = rate * f->pre_div;drivers/clk/qcom/clk-rcg2.c +1
-1@@ -192,7 +192,7 @@ static int _freq_tbl_determine_rate(struct clk_hw *hw,if (index <0 )return index; - clk_flags =__clk_get_flags (hw->clk); + clk_flags =clk_hw_get_flags (hw); p =clk_get_parent_by_index (hw->clk, index);if (clk_flags &CLK_SET_RATE_PARENT ) {if (f->pre_div) {drivers/clk/st/clk-flexgen.c +1
-1@@ -109,7 +109,7 @@ static long flexgen_round_rate(struct clk_hw *hw, unsigned long rate,/* Round div according to exact prate and wished rate */ div =clk_best_div (*prate, rate); -if (__clk_get_flags (hw->clk) &CLK_SET_RATE_PARENT ) { +if (clk_hw_get_flags (hw) &CLK_SET_RATE_PARENT ) { *prate = rate * div;return rate; }drivers/clk/sunxi/clk-factors.c +1
-1@@ -92,7 +92,7 @@ static int clk_factors_determine_rate(struct clk_hw *hw, parent =clk_get_parent_by_index (clk, i);if (!parent)continue ; -if (__clk_get_flags (clk) &CLK_SET_RATE_PARENT ) +if (clk_hw_get_flags (hw) &CLK_SET_RATE_PARENT ) parent_rate =__clk_round_rate (parent, req->rate);else parent_rate =__clk_get_rate (parent);drivers/clk/sunxi/clk-sunxi.c +1
-1@@ -133,7 +133,7 @@ static int sun6i_ahb1_clk_determine_rate(struct clk_hw *hw, parent =clk_get_parent_by_index (clk, i);if (!parent)continue ; -if (__clk_get_flags (clk) &CLK_SET_RATE_PARENT ) +if (clk_hw_get_flags (hw) &CLK_SET_RATE_PARENT ) parent_rate =__clk_round_rate (parent, req->rate);else parent_rate =__clk_get_rate (parent);drivers/clk/ti/clk.c +2
-2@@ -339,11 +339,11 @@ struct clk __init *ti_clk_register_clk(struct ti_clk *setup)if (!IS_ERR (clk)) { setup->clk = clk;if (setup->clkdm_name) { -if (__clk_get_flags (clk) &CLK_IS_BASIC ) { + clk_hw =__clk_get_hw (clk); +if (clk_hw_get_flags (clk_hw) &CLK_IS_BASIC ) {pr_warn ("can't setup clkdm for basic clk %s\n" , setup->name); }else { - clk_hw =__clk_get_hw (clk);to_clk_hw_omap (clk_hw)->clkdm_name = setup->clkdm_name;omap2_init_clk_clkdm (clk_hw);drivers/clk/ti/clockdomain.c +2
-2@@ -120,12 +120,12 @@ static void __init of_ti_clockdomain_setup(struct device_node *node) __func__, node->full_name, i, PTR_ERR(clk));continue ; } -if (__clk_get_flags (clk) &CLK_IS_BASIC ) { + clk_hw =__clk_get_hw (clk); +if (clk_hw_get_flags (clk_hw) &CLK_IS_BASIC ) {pr_warn ("can't setup clkdm for basic clk %s\n" ,__clk_get_name (clk));continue ; } - clk_hw =__clk_get_hw (clk);to_clk_hw_omap (clk_hw)->clkdm_name = clkdm_name;omap2_init_clk_clkdm (clk_hw); }drivers/clk/ti/divider.c +1
-1@@ -155,7 +155,7 @@ static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate, maxdiv =_get_maxdiv (divider); -if (!(__clk_get_flags (hw->clk) &CLK_SET_RATE_PARENT )) { +if (!(clk_hw_get_flags (hw) &CLK_SET_RATE_PARENT )) { parent_rate = *best_parent_rate; bestdiv =DIV_ROUND_UP (parent_rate, rate); bestdiv = bestdiv ==0 ?1 : bestdiv;drivers/clk/ti/dpll.c +2
-2@@ -163,7 +163,7 @@ static void __init _register_dpll(struct clk_hw *hw, clk =clk_register (NULL , &clk_hw->hw);if (!IS_ERR (clk)) { -omap2_init_clk_hw_omap_clocks (clk); +omap2_init_clk_hw_omap_clocks (&clk_hw->hw);of_clk_add_provider (node, of_clk_src_simple_get, clk);kfree (clk_hw->hw.init->parent_names);kfree (clk_hw->hw.init);@@ -320,7 +320,7 @@ static void _register_dpll_x2(struct device_node *node,if (IS_ERR (clk)) {kfree (clk_hw); }else { -omap2_init_clk_hw_omap_clocks (clk); +omap2_init_clk_hw_omap_clocks (&clk_hw->hw);of_clk_add_provider (node, of_clk_src_simple_get, clk); } }drivers/clk/ti/dpll3xxx.c +1
-1@@ -711,7 +711,7 @@ static struct clk_hw_omap *omap3_find_clkoutx2_dpll(struct clk_hw *hw)do { parent =__clk_get_parent (hw->clk); hw =__clk_get_hw (parent); - }while (hw && (__clk_get_flags (hw->clk) &CLK_IS_BASIC )); + }while (hw && (clk_hw_get_flags (hw) &CLK_IS_BASIC ));if (!hw)break ; pclk =to_clk_hw_omap (hw);drivers/clk/ti/interface.c +1
-1@@ -63,7 +63,7 @@ static struct clk *_register_interface(struct device *dev, const char *name,if (IS_ERR (clk))kfree (clk_hw);else -omap2_init_clk_hw_omap_clocks (clk); +omap2_init_clk_hw_omap_clocks (&clk_hw->hw);return clk; }
PATCH 6/26 clk: Add clk_hw_*() API for use by providers
In reply to Stephen Boydclk providers shouldn't need to use the consumer API (clk.h). Add a provider API to replace the __clk_*() APIs that take struct clk_hw as their first argument instead of a struct clk pointer.
--- drivers/clk/clk.c | 49 ++++++++++++++++++++++++++++++++++++++++++++ include/linux/clk-provider.h | 7 +++++++ 2 files changed, 56 insertions(+)
drivers/clk/clk.c +49 -0
@@ -277,6 +277,12 @@ const char *__clk_get_name(struct clk *clk) }EXPORT_SYMBOL_GPL (__clk_get_name); +const char *clk_hw_get_name (struct clk_hw *hw) +{ +return hw->core->name; +} +EXPORT_SYMBOL_GPL (clk_hw_get_name); +struct clk_hw *__clk_get_hw (struct clk *clk) {return !clk ?NULL : clk->core->hw;
@@ -299,6 +305,12 @@ struct clk *__clk_get_parent(struct clk *clk) }EXPORT_SYMBOL_GPL (__clk_get_parent); +struct clk_hw *clk_hw_get_parent (struct clk_hw *hw) +{ +return hw->core->parent ? hw->core->parent->hw :NULL ; +} +EXPORT_SYMBOL_GPL (clk_hw_get_parent); +static struct clk_core *__clk_lookup_subtree (const char *name,struct clk_core *core) {
@@ -369,6 +381,16 @@ struct clk *clk_get_parent_by_index(struct clk *clk, u8 index) }EXPORT_SYMBOL_GPL (clk_get_parent_by_index); +struct clk_hw *clk_hw_get_parent_by_index (struct clk_hw *hw,unsigned int index) +{ +struct clk_core *parent; + + parent =clk_core_get_parent_by_index (hw->core, index); + +return !parent ?NULL : parent->hw; +} +EXPORT_SYMBOL_GPL (clk_hw_get_parent_by_index); +unsigned int __clk_get_enable_count (struct clk *clk) {return !clk ?0 : clk->core->enable_count;
@@ -404,6 +426,12 @@ unsigned long __clk_get_rate(struct clk *clk) }EXPORT_SYMBOL_GPL (__clk_get_rate); +unsigned long clk_hw_get_rate (struct clk_hw *hw) +{ +return clk_core_get_rate_nolock (hw->core); +} +EXPORT_SYMBOL_GPL (clk_hw_get_rate); +static unsigned long __clk_get_accuracy (struct clk_core *core) {if (!core)
@@ -432,6 +460,11 @@ bool __clk_is_prepared(struct clk *clk)return clk_core_is_prepared (clk->core); } +bool clk_hw_is_prepared (struct clk_hw *hw) +{ +return clk_core_is_prepared (hw->core); +} +bool __clk_is_enabled (struct clk *clk) {if (!clk)
@@ -866,6 +899,22 @@ unsigned long __clk_round_rate(struct clk *clk, unsigned long rate) }EXPORT_SYMBOL_GPL (__clk_round_rate); +unsigned long clk_hw_round_rate (struct clk_hw *hw,unsigned long rate) +{ +int ret; +struct clk_rate_request req; + +clk_core_get_boundaries (hw->core, &req.min_rate, &req.max_rate); + req.rate = rate; + + ret =clk_core_round_rate_nolock (hw->core, &req); +if (ret) +return 0 ; + +return req.rate; +} +EXPORT_SYMBOL_GPL (clk_hw_round_rate); +/** * clk_round_rate - round the given rate for a clk * @clk: the clk for which we are rounding a rate
include/linux/clk-provider.h +7 -0
@@ -607,15 +607,21 @@ void devm_clk_unregister(struct device *dev, struct clk *clk);/* helper functions */ const char *__clk_get_name (struct clk *clk); +const char *clk_hw_get_name (struct clk_hw *hw);struct clk_hw *__clk_get_hw (struct clk *clk);unsigned int clk_hw_get_num_parents (struct clk_hw *hw);struct clk *__clk_get_parent (struct clk *clk); +struct clk_hw *clk_hw_get_parent (struct clk_hw *hw);struct clk *clk_get_parent_by_index (struct clk *clk,u8 index); +struct clk_hw *clk_hw_get_parent_by_index (struct clk_hw *hw, +unsigned int index);unsigned int __clk_get_enable_count (struct clk *clk);unsigned long __clk_get_rate (struct clk *clk); +unsigned long clk_hw_get_rate (struct clk_hw *hw);unsigned long __clk_get_flags (struct clk *clk);unsigned long clk_hw_get_flags (struct clk_hw *hw);bool __clk_is_prepared (struct clk *clk); +bool clk_hw_is_prepared (struct clk_hw *hw);bool __clk_is_enabled (struct clk *clk);struct clk *__clk_lookup (const char *name); int __clk_mux_determine_rate(struct clk_hw *hw,
@@ -637,6 +643,7 @@ static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)* FIXME clock api without lock protection */ unsigned long __clk_round_rate (struct clk *clk,unsigned long rate); +unsigned long clk_hw_round_rate (struct clk_hw *hw,unsigned long rate);struct of_device_id ;
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH 7/26 clk: ti: Remove CLK_IS_BASIC check
In reply to Stephen BoydThis code is never called with a basic clock type, so the check here is not doing anything useful and is blocking the removal of __clk_get_flags(). Remove the check so we can delete the __clk_get_flags() API.
--- drivers/clk/ti/autoidle.c | 6 ------ 1 file changed, 6 deletions(-)
drivers/clk/ti/autoidle.c +0 -6
@@ -47,9 +47,6 @@ int omap2_clk_deny_idle(struct clk *clk) {struct clk_hw_omap *c; -if (__clk_get_flags (clk) &CLK_IS_BASIC ) -return -EINVAL ; - c =to_clk_hw_omap (__clk_get_hw (clk));if (c->ops && c->ops->deny_idle) c->ops->deny_idle (c);
@@ -66,9 +63,6 @@ int omap2_clk_allow_idle(struct clk *clk) {struct clk_hw_omap *c; -if (__clk_get_flags (clk) &CLK_IS_BASIC ) -return -EINVAL ; - c =to_clk_hw_omap (__clk_get_hw (clk));if (c->ops && c->ops->allow_idle) c->ops->allow_idle (c);
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH 8/26 ARM: OMAP: Convert __clk_get_rate() to provider/consumer APIs
In reply to Stephen BoydWe're removing struct clk from the clk provider API, so switch to clk_get_rate() and clk_hw_get_rate() here appropriately.
--- arch/arm/mach-omap2/clkt34xx_dpll3m2.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
arch/arm/mach-omap2/clkt34xx_dpll3m2.c +3 -3
@@ -67,8 +67,8 @@ int omap3_core_dpll_m2_set_rate(struct clk_hw *hw, unsigned long rate,if (validrate != rate)return -EINVAL ; - sdrcrate =__clk_get_rate (sdrc_ick_p); - clkrate =__clk_get_rate (hw->clk); + sdrcrate =clk_get_rate (sdrc_ick_p); + clkrate =clk_hw_get_rate (hw);if (rate > clkrate) sdrcrate <<= ((rate / clkrate) >>1 );else
@@ -86,7 +86,7 @@ int omap3_core_dpll_m2_set_rate(struct clk_hw *hw, unsigned long rate,/* * XXX This only needs to be done when the CPU frequency changes */ - _mpurate =__clk_get_rate (arm_fck_p) /CYCLES_PER_MHZ ; + _mpurate =clk_get_rate (arm_fck_p) /CYCLES_PER_MHZ ; c = (_mpurate <<SDRC_MPURATE_SCALE ) >>SDRC_MPURATE_BASE_SHIFT ; c +=1 ;/* for safety */ c *=SDRC_MPURATE_LOOPS ;
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH 9/26 MIPS: alchemy: Convert to clk_hw based provider APIs
In reply to Stephen BoydWe're removing struct clk from the clk provider API, so switch this code to using the clk_hw based provider APIs.
--- arch/mips/alchemy/common/clock.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)
arch/mips/alchemy/common/clock.c +6 -6
@@ -394,7 +394,7 @@ static int alchemy_clk_fgcs_detr(struct clk_hw *hw,struct clk_rate_request *req, int scale, int maxdiv) { - struct clk *pc, *bpc, *free; + struct clk_hw *pc, *bpc, *free;long tdv, tpr, pr, nr, br, bpr, diff, lastdiff;int j;
@@ -408,7 +408,7 @@ static int alchemy_clk_fgcs_detr(struct clk_hw *hw,* the one that gets closest to but not over the requested rate. */ for (j =0 ; j <7 ; j++) { - pc =clk_get_parent_by_index (hw->clk, j); + pc =clk_hw_get_parent_by_index (hw, j);if (!pc)break ;
@@ -416,12 +416,12 @@ static int alchemy_clk_fgcs_detr(struct clk_hw *hw,* XXX: we would actually want clk_has_active_children() * but this is a good-enough approximation for now. */ -if (!__clk_is_prepared (pc)) { +if (!clk_hw_is_prepared (pc)) {if (!free) free = pc; } - pr =clk_get_rate (pc); + pr =clk_hw_get_rate (pc);if (pr < req->rate)continue ;
@@ -451,7 +451,7 @@ static int alchemy_clk_fgcs_detr(struct clk_hw *hw, tpr = req->rate * j;if (tpr <0 )break ; - pr =clk_round_rate (free, tpr); + pr =clk_hw_round_rate (free, tpr); tdv =alchemy_calc_div (req->rate, pr, scale, maxdiv,NULL );
@@ -474,7 +474,7 @@ static int alchemy_clk_fgcs_detr(struct clk_hw *hw,return br; req->best_parent_rate = bpr; - req->best_parent_hw =__clk_get_hw (bpc); + req->best_parent_hw = bpc; req->rate = br;return 0 ;
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH 10/26 clk: at91: Convert to clk_hw based provider APIs
In reply to Stephen BoydWe're removing struct clk from the clk provider API, so switch this code to using the clk_hw based provider APIs.
--- drivers/clk/at91/clk-peripheral.c | 6 +++--- drivers/clk/at91/clk-programmable.c | 8 ++++---- drivers/clk/at91/clk-usb.c | 12 ++++++------ 3 files changed, 13 insertions(+), 13 deletions(-)
drivers/clk/at91/clk-peripheral.c +3 -3
@@ -134,7 +134,7 @@ at91_clk_register_peripheral(struct at91_pmc *pmc, const char *name,static void clk_sam9x5_peripheral_autodiv (struct clk_sam9x5_peripheral *periph) { -struct clk *parent; +struct clk_hw *parent;unsigned long parent_rate;int shift =0 ;
@@ -142,8 +142,8 @@ static void clk_sam9x5_peripheral_autodiv(struct clk_sam9x5_peripheral *periph)return ;if (periph->range.max) { - parent =clk_get_parent_by_index (periph->hw.clk,0 ); - parent_rate =__clk_get_rate (parent); + parent =clk_hw_get_parent_by_index (&periph->hw,0 ); + parent_rate =clk_hw_get_rate (parent);if (!parent_rate)return ;
drivers/clk/at91/clk-programmable.c +4 -4
@@ -57,7 +57,7 @@ static unsigned long clk_programmable_recalc_rate(struct clk_hw *hw,static int clk_programmable_determine_rate (struct clk_hw *hw,struct clk_rate_request *req) { -struct clk *parent =NULL ; +struct clk_hw *parent;long best_rate = -EINVAL ;unsigned long parent_rate;unsigned long tmp_rate;
@@ -65,11 +65,11 @@ static int clk_programmable_determine_rate(struct clk_hw *hw,int i;for (i =0 ; i <clk_hw_get_num_parents (hw); i++) { - parent =clk_get_parent_by_index (hw->clk, i); + parent =clk_hw_get_parent_by_index (hw, i);if (!parent)continue ; - parent_rate =__clk_get_rate (parent); + parent_rate =clk_hw_get_rate (parent);for (shift =0 ; shift <PROG_PRES_MASK ; shift++) { tmp_rate = parent_rate >> shift;if (tmp_rate <= req->rate)
@@ -83,7 +83,7 @@ static int clk_programmable_determine_rate(struct clk_hw *hw, (req->rate - tmp_rate) < (req->rate - best_rate)) { best_rate = tmp_rate; req->best_parent_rate = parent_rate; - req->best_parent_hw =__clk_get_hw (parent); + req->best_parent_hw = parent; }if (!best_rate)
drivers/clk/at91/clk-usb.c +6 -6
@@ -59,7 +59,7 @@ static unsigned long at91sam9x5_clk_usb_recalc_rate(struct clk_hw *hw,static int at91sam9x5_clk_usb_determine_rate (struct clk_hw *hw,struct clk_rate_request *req) { -struct clk *parent =NULL ; +struct clk_hw *parent;long best_rate = -EINVAL ;unsigned long tmp_rate;int best_diff =-1 ;
@@ -69,7 +69,7 @@ static int at91sam9x5_clk_usb_determine_rate(struct clk_hw *hw,for (i =0 ; i <clk_hw_get_num_parents (hw); i++) {int div; - parent =clk_get_parent_by_index (hw->clk, i); + parent =clk_hw_get_parent_by_index (hw, i);if (!parent)continue ;
@@ -77,7 +77,7 @@ static int at91sam9x5_clk_usb_determine_rate(struct clk_hw *hw,unsigned long tmp_parent_rate; tmp_parent_rate = req->rate * div; - tmp_parent_rate =__clk_round_rate (parent, + tmp_parent_rate =clk_hw_round_rate (parent, tmp_parent_rate); tmp_rate =DIV_ROUND_CLOSEST (tmp_parent_rate, div);if (tmp_rate < req->rate)
@@ -89,7 +89,7 @@ static int at91sam9x5_clk_usb_determine_rate(struct clk_hw *hw, best_rate = tmp_rate; best_diff = tmp_diff; req->best_parent_rate = tmp_parent_rate; - req->best_parent_hw =__clk_get_hw (parent); + req->best_parent_hw = parent; }if (!best_diff || tmp_rate < req->rate)
@@ -273,7 +273,7 @@ static long at91rm9200_clk_usb_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) {struct at91rm9200_clk_usb *usb =to_at91rm9200_clk_usb (hw); -struct clk *parent =__clk_get_parent (hw->clk); +struct clk_hw *parent =clk_hw_get_parent (hw);unsigned long bestrate =0 ;int bestdiff =-1 ;unsigned long tmprate;
@@ -287,7 +287,7 @@ static long at91rm9200_clk_usb_round_rate(struct clk_hw *hw, unsigned long rate,continue ; tmp_parent_rate = rate * usb->divisors[i]; - tmp_parent_rate =__clk_round_rate (parent, tmp_parent_rate); + tmp_parent_rate =clk_hw_round_rate (parent, tmp_parent_rate); tmprate =DIV_ROUND_CLOSEST (tmp_parent_rate, usb->divisors[i]);if (tmprate < rate) tmpdiff = rate - tmprate;
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH 10/26] clk: at91: Convert to clk_hw based provider APIs
Quoted 4 lines · On Fri, 31 Jul 2015 10:03:50 -0700 Stephen Boyd <[email protected]> wrote:
We're removing struct clk from the clk provider API, so switch this code to using the
clk_hwbased provider APIs.Cc Boris Brezillon <[email protected]>
Quoted 125 lines
Signed-off-by Stephen Boyd <[email protected]>--- drivers/clk/at91/clk-peripheral.c | 6 +++--- drivers/clk/at91/clk-programmable.c | 8 ++++---- drivers/clk/at91/clk-usb.c | 12 ++++++------ 3 files changed, 13 insertions(+), 13 deletions(-)drivers/clk/at91/clk-peripheral.c +3
-3@@ -134,7 +134,7 @@ at91_clk_register_peripheral(struct at91_pmc *pmc, const char *name,static void clk_sam9x5_peripheral_autodiv (struct clk_sam9x5_peripheral *periph) { -struct clk *parent; +struct clk_hw *parent;unsigned long parent_rate;int shift =0 ;@@ -142,8 +142,8 @@ static void clk_sam9x5_peripheral_autodiv(struct clk_sam9x5_peripheral *periph)return ;if (periph->range.max) { - parent =clk_get_parent_by_index (periph->hw.clk,0 ); - parent_rate =__clk_get_rate (parent); + parent =clk_hw_get_parent_by_index (&periph->hw,0 ); + parent_rate =clk_hw_get_rate (parent);if (!parent_rate)return ;drivers/clk/at91/clk-programmable.c +4
-4@@ -57,7 +57,7 @@ static unsigned long clk_programmable_recalc_rate(struct clk_hw *hw,static int clk_programmable_determine_rate (struct clk_hw *hw,struct clk_rate_request *req) { -struct clk *parent =NULL ; +struct clk_hw *parent;long best_rate = -EINVAL ;unsigned long parent_rate;unsigned long tmp_rate;@@ -65,11 +65,11 @@ static int clk_programmable_determine_rate(struct clk_hw *hw,int i;for (i =0 ; i <clk_hw_get_num_parents (hw); i++) { - parent =clk_get_parent_by_index (hw->clk, i); + parent =clk_hw_get_parent_by_index (hw, i);if (!parent)continue ; - parent_rate =__clk_get_rate (parent); + parent_rate =clk_hw_get_rate (parent);for (shift =0 ; shift <PROG_PRES_MASK ; shift++) { tmp_rate = parent_rate >> shift;if (tmp_rate <= req->rate)@@ -83,7 +83,7 @@ static int clk_programmable_determine_rate(struct clk_hw *hw, (req->rate - tmp_rate) < (req->rate - best_rate)) { best_rate = tmp_rate; req->best_parent_rate = parent_rate; - req->best_parent_hw =__clk_get_hw (parent); + req->best_parent_hw = parent; }if (!best_rate)drivers/clk/at91/clk-usb.c +6
-6@@ -59,7 +59,7 @@ static unsigned long at91sam9x5_clk_usb_recalc_rate(struct clk_hw *hw,static int at91sam9x5_clk_usb_determine_rate (struct clk_hw *hw,struct clk_rate_request *req) { -struct clk *parent =NULL ; +struct clk_hw *parent;long best_rate = -EINVAL ;unsigned long tmp_rate;int best_diff =-1 ;@@ -69,7 +69,7 @@ static int at91sam9x5_clk_usb_determine_rate(struct clk_hw *hw,for (i =0 ; i <clk_hw_get_num_parents (hw); i++) {int div; - parent =clk_get_parent_by_index (hw->clk, i); + parent =clk_hw_get_parent_by_index (hw, i);if (!parent)continue ;@@ -77,7 +77,7 @@ static int at91sam9x5_clk_usb_determine_rate(struct clk_hw *hw,unsigned long tmp_parent_rate; tmp_parent_rate = req->rate * div; - tmp_parent_rate =__clk_round_rate (parent, + tmp_parent_rate =clk_hw_round_rate (parent, tmp_parent_rate); tmp_rate =DIV_ROUND_CLOSEST (tmp_parent_rate, div);if (tmp_rate < req->rate)@@ -89,7 +89,7 @@ static int at91sam9x5_clk_usb_determine_rate(struct clk_hw *hw, best_rate = tmp_rate; best_diff = tmp_diff; req->best_parent_rate = tmp_parent_rate; - req->best_parent_hw =__clk_get_hw (parent); + req->best_parent_hw = parent; }if (!best_diff || tmp_rate < req->rate)@@ -273,7 +273,7 @@ static long at91rm9200_clk_usb_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) {struct at91rm9200_clk_usb *usb =to_at91rm9200_clk_usb (hw); -struct clk *parent =__clk_get_parent (hw->clk); +struct clk_hw *parent =clk_hw_get_parent (hw);unsigned long bestrate =0 ;int bestdiff =-1 ;unsigned long tmprate;@@ -287,7 +287,7 @@ static long at91rm9200_clk_usb_round_rate(struct clk_hw *hw, unsigned long rate,continue ; tmp_parent_rate = rate * usb->divisors[i]; - tmp_parent_rate =__clk_round_rate (parent, tmp_parent_rate); + tmp_parent_rate =clk_hw_round_rate (parent, tmp_parent_rate); tmprate =DIV_ROUND_CLOSEST (tmp_parent_rate, usb->divisors[i]);if (tmprate < rate) tmpdiff = rate - tmprate;
Signature · 3 lines
Boris Brezillon, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com
PATCH 11/26 clk: bcm: Convert to clk_hw based provider APIs
In reply to Stephen BoydWe're removing struct clk from the clk provider API, so switch this code to using the clk_hw based provider APIs.
--- drivers/clk/bcm/clk-kona.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-)
drivers/clk/bcm/clk-kona.c +10 -10
@@ -1011,7 +1011,7 @@ static long kona_peri_clk_round_rate(struct clk_hw *hw, unsigned long rate,struct bcm_clk_div *div = &bcm_clk->u.peri->div;if (!divider_exists (div)) -return __clk_get_rate (hw->clk); +return clk_hw_get_rate (hw);/* Quietly avoid a zero rate */ return round_rate(bcm_clk->ccu, div, &bcm_clk->u.peri->pre_div,
@@ -1022,8 +1022,7 @@ static int kona_peri_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) {struct kona_clk *bcm_clk =to_kona_clk (hw); -struct clk *clk = hw->clk; -struct clk *current_parent; +struct clk_hw *current_parent;unsigned long parent_rate;unsigned long best_delta;unsigned long best_rate;
@@ -1048,14 +1047,14 @@ static int kona_peri_clk_determine_rate(struct clk_hw *hw, }/* Unless we can do better, stick with current parent */ - current_parent =clk_get_parent (clk); - parent_rate =__clk_get_rate (current_parent); + current_parent =clk_hw_get_parent (hw); + parent_rate =clk_hw_get_rate (current_parent); best_rate =kona_peri_clk_round_rate (hw, req->rate, &parent_rate); best_delta =abs (best_rate - req->rate);/* Check whether any other parent clock can produce a better result */ for (which =0 ; which < parent_count; which++) { -struct clk *parent =clk_get_parent_by_index (clk, which); +struct clk_hw *parent =clk_hw_get_parent_by_index (hw, which);unsigned long delta;unsigned long other_rate;
@@ -1064,14 +1063,14 @@ static int kona_peri_clk_determine_rate(struct clk_hw *hw,continue ;/* We don't support CLK_SET_RATE_PARENT */ - parent_rate =__clk_get_rate (parent); + parent_rate =clk_hw_get_rate (parent); other_rate =kona_peri_clk_round_rate (hw, req->rate, &parent_rate); delta =abs (other_rate - req->rate);if (delta < best_delta) { best_delta = delta; best_rate = other_rate; - req->best_parent_hw =__clk_get_hw (parent); + req->best_parent_hw = parent; req->best_parent_rate = parent_rate; } }
@@ -1139,7 +1138,7 @@ static int kona_peri_clk_set_rate(struct clk_hw *hw, unsigned long rate,if (parent_rate > (unsigned long )LONG_MAX )return -EINVAL ; -if (rate ==__clk_get_rate (hw->clk)) +if (rate ==clk_hw_get_rate (hw))return 0 ;if (!divider_exists (div))
@@ -1258,6 +1257,7 @@ bool __init kona_ccu_init(struct ccu_data *ccu)unsigned long flags;unsigned int which;struct clk **clks = ccu->clk_data.clks; +struct kona_clk *kona_clks = ccu->kona_clks;bool success = true; flags =ccu_lock (ccu);
@@ -1268,7 +1268,7 @@ bool __init kona_ccu_init(struct ccu_data *ccu)if (!clks[which])continue ; - bcm_clk =to_kona_clk (__clk_get_hw (clks[which])); + bcm_clk = &kona_clks[which]; success &=__kona_clk_init (bcm_clk); }
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH 11/26] clk: bcm: Convert to clk_hw based provider APIs
Quoted 5 lines · Stephen Boyd
We're removing struct clk from the clk provider API, so switch this code to using the
clk_hwbased provider APIs.Cc Alex Elder <[email protected]>Signed-off-by Stephen Boyd <[email protected]>
Looks good to me.
Quoted 89 lines
--- drivers/clk/bcm/clk-kona.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-)drivers/clk/bcm/clk-kona.c +10
-10@@ -1011,7 +1011,7 @@ static long kona_peri_clk_round_rate(struct clk_hw *hw, unsigned long rate,struct bcm_clk_div *div = &bcm_clk->u.peri->div;if (!divider_exists (div)) -return __clk_get_rate (hw->clk); +return clk_hw_get_rate (hw);/* Quietly avoid a zero rate */ return round_rate(bcm_clk->ccu, div, &bcm_clk->u.peri->pre_div,@@ -1022,8 +1022,7 @@ static int kona_peri_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) {struct kona_clk *bcm_clk =to_kona_clk (hw); -struct clk *clk = hw->clk; -struct clk *current_parent; +struct clk_hw *current_parent;unsigned long parent_rate;unsigned long best_delta;unsigned long best_rate;@@ -1048,14 +1047,14 @@ static int kona_peri_clk_determine_rate(struct clk_hw *hw, }/* Unless we can do better, stick with current parent */ - current_parent =clk_get_parent (clk); - parent_rate =__clk_get_rate (current_parent); + current_parent =clk_hw_get_parent (hw); + parent_rate =clk_hw_get_rate (current_parent); best_rate =kona_peri_clk_round_rate (hw, req->rate, &parent_rate); best_delta =abs (best_rate - req->rate);/* Check whether any other parent clock can produce a better result */ for (which =0 ; which < parent_count; which++) { -struct clk *parent =clk_get_parent_by_index (clk, which); +struct clk_hw *parent =clk_hw_get_parent_by_index (hw, which);unsigned long delta;unsigned long other_rate;@@ -1064,14 +1063,14 @@ static int kona_peri_clk_determine_rate(struct clk_hw *hw,continue ;/* We don't support CLK_SET_RATE_PARENT */ - parent_rate =__clk_get_rate (parent); + parent_rate =clk_hw_get_rate (parent); other_rate =kona_peri_clk_round_rate (hw, req->rate, &parent_rate); delta =abs (other_rate - req->rate);if (delta < best_delta) { best_delta = delta; best_rate = other_rate; - req->best_parent_hw =__clk_get_hw (parent); + req->best_parent_hw = parent; req->best_parent_rate = parent_rate; } }@@ -1139,7 +1138,7 @@ static int kona_peri_clk_set_rate(struct clk_hw *hw, unsigned long rate,if (parent_rate > (unsigned long )LONG_MAX )return -EINVAL ; -if (rate ==__clk_get_rate (hw->clk)) +if (rate ==clk_hw_get_rate (hw))return 0 ;if (!divider_exists (div))@@ -1258,6 +1257,7 @@ bool __init kona_ccu_init(struct ccu_data *ccu)unsigned long flags;unsigned int which;struct clk **clks = ccu->clk_data.clks; +struct kona_clk *kona_clks = ccu->kona_clks;bool success = true; flags =ccu_lock (ccu);@@ -1268,7 +1268,7 @@ bool __init kona_ccu_init(struct ccu_data *ccu)if (!clks[which])continue ; - bcm_clk =to_kona_clk (__clk_get_hw (clks[which])); + bcm_clk = &kona_clks[which]; success &=__kona_clk_init (bcm_clk); }
PATCH 12/26 clk: Convert basic types to clk_hw based provider APIs
In reply to Stephen BoydWe're removing struct clk from the clk provider API, so switch this code to using the clk_hw based provider APIs.
--- drivers/clk/clk-composite.c | 14 +++++++------- drivers/clk/clk-divider.c | 6 +++--- drivers/clk/clk-fixed-factor.c | 3 +-- 3 files changed, 11 insertions(+), 12 deletions(-)
drivers/clk/clk-composite.c +7 -7
@@ -63,7 +63,7 @@ static int clk_composite_determine_rate(struct clk_hw *hw,const struct clk_ops *mux_ops = composite->mux_ops;struct clk_hw *rate_hw = composite->rate_hw;struct clk_hw *mux_hw = composite->mux_hw; -struct clk *parent; +struct clk_hw *parent;unsigned long parent_rate;long tmp_rate, best_rate =0 ;unsigned long rate_diff;
@@ -79,9 +79,9 @@ static int clk_composite_determine_rate(struct clk_hw *hw, req->best_parent_hw =NULL ;if (clk_hw_get_flags (hw) &CLK_SET_RATE_NO_REPARENT ) { - parent =clk_get_parent (mux_hw->clk); - req->best_parent_hw =__clk_get_hw (parent); - req->best_parent_rate =__clk_get_rate (parent); + parent =clk_hw_get_parent (mux_hw); + req->best_parent_hw = parent; + req->best_parent_rate =clk_hw_get_rate (parent); rate = rate_ops->round_rate (rate_hw, req->rate, &req->best_parent_rate);
@@ -93,11 +93,11 @@ static int clk_composite_determine_rate(struct clk_hw *hw, }for (i =0 ; i <clk_hw_get_num_parents (mux_hw); i++) { - parent =clk_get_parent_by_index (mux_hw->clk, i); + parent =clk_hw_get_parent_by_index (mux_hw, i);if (!parent)continue ; - parent_rate =__clk_get_rate (parent); + parent_rate =clk_hw_get_rate (parent); tmp_rate = rate_ops->round_rate (rate_hw, req->rate, &parent_rate);
@@ -108,7 +108,7 @@ static int clk_composite_determine_rate(struct clk_hw *hw,if (!rate_diff || !req->best_parent_hw || best_rate_diff > rate_diff) { - req->best_parent_hw =__clk_get_hw (parent); + req->best_parent_hw = parent; req->best_parent_rate = parent_rate; best_rate_diff = rate_diff; best_rate = tmp_rate;
drivers/clk/clk-divider.c +3 -3
@@ -128,7 +128,7 @@ unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,if (!div) {WARN (!(flags &CLK_DIVIDER_ALLOW_ZERO ),"%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n" , -__clk_get_name (hw->clk)); +clk_hw_get_name (hw));return parent_rate; }
@@ -316,7 +316,7 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate, *best_parent_rate = parent_rate_saved;return i; } - parent_rate =__clk_round_rate (__clk_get_parent (hw->clk), + parent_rate =clk_hw_round_rate (clk_hw_get_parent (hw), rate * i); now =DIV_ROUND_UP (parent_rate, i);if (_is_best_div (rate, now, best, flags)) {
@@ -328,7 +328,7 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,if (!bestdiv) { bestdiv =_get_maxdiv (table, width, flags); - *best_parent_rate =__clk_round_rate (__clk_get_parent (hw->clk),1 ); + *best_parent_rate =clk_hw_round_rate (clk_hw_get_parent (hw),1 ); }return bestdiv;
drivers/clk/clk-fixed-factor.c +1 -2
@@ -45,8 +45,7 @@ static long clk_factor_round_rate(struct clk_hw *hw, unsigned long rate,unsigned long best_parent; best_parent = (rate / fix->mult) * fix->div; - *prate =__clk_round_rate (__clk_get_parent (hw->clk), - best_parent); + *prate =clk_hw_round_rate (clk_hw_get_parent (hw), best_parent); }return (*prate / fix->div) * fix->mult;
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH 13/26 clk: mmp: Convert to clk_hw based provider APIs
In reply to Stephen BoydWe're removing struct clk from the clk provider API, so switch this code to using the clk_hw based provider APIs.
--- drivers/clk/mmp/clk-gate.c | 3 +-- drivers/clk/mmp/clk-mix.c | 35 ++++++++++++++++------------------- 2 files changed, 17 insertions(+), 21 deletions(-)
drivers/clk/mmp/clk-gate.c +1 -2
@@ -27,7 +27,6 @@static int mmp_clk_gate_enable (struct clk_hw *hw) {struct mmp_clk_gate *gate =to_clk_mmp_gate (hw); -struct clk *clk = hw->clk;unsigned long flags =0 ;unsigned long rate;u32 tmp;
@@ -44,7 +43,7 @@ static int mmp_clk_gate_enable(struct clk_hw *hw)spin_unlock_irqrestore (gate->lock, flags);if (gate->flags &MMP_CLK_GATE_NEED_DELAY ) { - rate =__clk_get_rate (clk); + rate =clk_hw_get_rate (hw);/* Need delay 2 cycles. */ udelay (2000000 /rate); }
drivers/clk/mmp/clk-mix.c +16 -19
@@ -113,15 +113,15 @@ static void _filter_clk_table(struct mmp_clk_mix *mix, {int i;struct mmp_clk_mix_clk_table *item; -struct clk *parent, *clk; +struct clk_hw *parent, *hw;unsigned long parent_rate; - clk = mix->hw.clk; + hw = &mix->hwfor (i =0 ; i < table_size; i++) { item = &table[i]; - parent =clk_get_parent_by_index (clk, item->parent_index); - parent_rate =__clk_get_rate (parent); + parent =clk_hw_get_parent_by_index (hw, item->parent_index); + parent_rate =clk_hw_get_rate (parent);if (parent_rate % item->rate) { item->valid =0 ; }else {
@@ -181,7 +181,7 @@ static int _set_rate(struct mmp_clk_mix *mix, u32 mux_val, u32 div_val,if (timeout ==0 ) {pr_err ("%s:%s cannot do frequency change\n" , - __func__,__clk_get_name (mix->hw.clk)); + __func__,clk_hw_get_name (&mix->hw)); ret = -EBUSY ; goto error; }
@@ -206,16 +206,14 @@ static int mmp_clk_mix_determine_rate(struct clk_hw *hw, {struct mmp_clk_mix *mix =to_clk_mix (hw);struct mmp_clk_mix_clk_table *item; -struct clk *parent, *parent_best, *mix_clk; +struct clk_hw *parent, *parent_best;unsigned long parent_rate, mix_rate, mix_rate_best, parent_rate_best;unsigned long gap, gap_best;u32 div_val_max;unsigned int div;int i, j; - mix_clk = hw->clk; - parent =NULL ; mix_rate_best =0 ; parent_rate_best =0 ; gap_best =ULONG_MAX ;
@@ -226,9 +224,9 @@ static int mmp_clk_mix_determine_rate(struct clk_hw *hw, item = &mix->table[i];if (item->valid ==0 )continue ; - parent =clk_get_parent_by_index (mix_clk, + parent =clk_hw_get_parent_by_index (hw, item->parent_index); - parent_rate =__clk_get_rate (parent); + parent_rate =clk_hw_get_rate (parent); mix_rate = parent_rate / item->divisor; gap =abs (mix_rate - req->rate);if (parent_best ==NULL || gap < gap_best) {
@@ -242,8 +240,8 @@ static int mmp_clk_mix_determine_rate(struct clk_hw *hw, } }else {for (i =0 ; i <clk_hw_get_num_parents (hw); i++) { - parent =clk_get_parent_by_index (mix_clk, i); - parent_rate =__clk_get_rate (parent); + parent =clk_hw_get_parent_by_index (hw, i); + parent_rate =clk_hw_get_rate (parent); div_val_max =_get_maxdiv (mix);for (j =0 ; j < div_val_max; j++) { div =_get_div (mix, j);
@@ -266,7 +264,7 @@ found:return -EINVAL ; req->best_parent_rate = parent_rate_best; - req->best_parent_hw =__clk_get_hw (parent_best); + req->best_parent_hw = parent_best; req->rate = mix_rate_best;return 0 ;
@@ -382,20 +380,19 @@ static int mmp_clk_set_rate(struct clk_hw *hw, unsigned long rate,struct mmp_clk_mix_clk_table *item;unsigned long parent_rate;unsigned int best_divisor; -struct clk *mix_clk, *parent; +struct clk_hw *parent;int i; best_divisor = best_parent_rate / rate; - mix_clk = hw->clk;if (mix->table) {for (i =0 ; i < mix->table_size; i++) { item = &mix->table[i];if (item->valid ==0 )continue ; - parent =clk_get_parent_by_index (mix_clk, + parent =clk_hw_get_parent_by_index (hw, item->parent_index); - parent_rate =__clk_get_rate (parent); + parent_rate =clk_hw_get_rate (parent);if (parent_rate == best_parent_rate && item->divisor == best_divisor)break ;
@@ -409,8 +406,8 @@ static int mmp_clk_set_rate(struct clk_hw *hw, unsigned long rate,return -EINVAL ; }else {for (i =0 ; i <clk_hw_get_num_parents (hw); i++) { - parent =clk_get_parent_by_index (mix_clk, i); - parent_rate =__clk_get_rate (parent); + parent =clk_hw_get_parent_by_index (hw, i); + parent_rate =clk_hw_get_rate (parent);if (parent_rate == best_parent_rate)break ; }
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH 14/26 clk: mvebu: Convert to clk_hw based provider APIs
In reply to Stephen BoydWe're removing struct clk from the clk provider API, so switch this code to using the clk_hw based provider APIs. This also removes a clk_get() in this driver that can just as easily use of_clk_get_parent_name() instead.
--- drivers/clk/mvebu/clk-cpu.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-)
drivers/clk/mvebu/clk-cpu.c +2 -4
@@ -121,7 +121,7 @@ static int clk_cpu_on_set_rate(struct clk_hw *hwclk, unsigned long rate,if (!cpuclk->pmu_dfs)return -ENODEV ; - cur_rate =__clk_get_rate (hwclk->clk); + cur_rate =clk_hw_get_rate (hwclk); reg =readl (cpuclk->reg_base +SYS_CTRL_CLK_DIVIDER_CTRL2_OFFSET ); fabric_div = (reg >> SYS_CTRL_CLK_DIVIDER_CTRL2_NBCLK_RATIO_SHIFT) &
@@ -197,7 +197,6 @@ static void __init of_cpu_clk_setup(struct device_node *node)for_each_node_by_type (dn,"cpu" ) {struct clk_init_data init;struct clk *clk; -struct clk *parent_clk;char *clk_name =kzalloc (5 ,GFP_KERNEL );int cpu, err;
@@ -209,9 +208,8 @@ static void __init of_cpu_clk_setup(struct device_node *node) goto bail_out;sprintf (clk_name,"cpu%d" , cpu); - parent_clk =of_clk_get (node,0 ); - cpuclk[cpu].parent_name =__clk_get_name (parent_clk); + cpuclk[cpu].parent_name =of_clk_get_parent_name (node,0 ); cpuclk[cpu].clk_name = clk_name; cpuclk[cpu].cpu = cpu; cpuclk[cpu].reg_base = clock_complex_base;
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH 14/26] clk: mvebu: Convert to clk_hw based provider APIs
Stephen, Mike,
Quoted 34 lines · Stephen Boyd
We're removing struct clk from the clk provider API, so switch this code to using the
clk_hwbased provider APIs. This also removes aclk_get()in this driver that can just as easily useof_clk_get_parent_name()instead.Cc Gregory CLEMENT <[email protected]>Cc Thomas Petazzoni <[email protected]>Signed-off-by Stephen Boyd <[email protected]>--- drivers/clk/mvebu/clk-cpu.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-)drivers/clk/mvebu/clk-cpu.c +1
-2@@ -121,7 +121,7 @@ static int clk_cpu_on_set_rate(struct clk_hw *hwclk, unsigned long rate,if (!cpuclk->pmu_dfs)return -ENODEV ; - cur_rate =__clk_get_rate (hwclk->clk); + cur_rate =clk_hw_get_rate (hwclk); reg =readl (cpuclk->reg_base +SYS_CTRL_CLK_DIVIDER_CTRL2_OFFSET ); fabric_div = (reg >> SYS_CTRL_CLK_DIVIDER_CTRL2_NBCLK_RATIO_SHIFT) &@@ -197,7 +197,6 @@ static void __init of_cpu_clk_setup(struct device_node *node)for_each_node_by_type (dn,"cpu" ) {struct clk_init_data init;struct clk *clk; -struct clk *parent_clk;char *clk_name =kzalloc (5 ,GFP_KERNEL );int cpu, err;
drivers/clk/mvebu/clk-cpu.c static void __init of_cpu_clk_setup(struct device_node *node) · line 215
Quoted 10 lines
drivers/clk/mvebu/clk-cpu.c +1
-2@@ -209,9 +208,8 @@ static void __init of_cpu_clk_setup(struct device_node *node) goto bail_out;sprintf (clk_name,"cpu%d" , cpu); - parent_clk =of_clk_get (node,0 ); - cpuclk[cpu].parent_name =__clk_get_name (parent_clk); + cpuclk[cpu].parent_name =of_clk_get_parent_name (node,0 ); cpuclk[cpu].clk_name = clk_name; cpuclk[cpu].cpu = cpu; cpuclk[cpu].reg_base = clock_complex_base;
Sorry to chime in only right now, but this patch causes a regression on Armada XP: the cpu clocks are no longer seen as child of their parent and therefore their rate is always 0. This breaks cpufreq on this platform.
For the record, our DT looks like this:
coreclk: mvebu-sar@18230 {
compatible = "marvell,armada-xp-core-clock";
reg = <0x18230 0x08>;
#clock-cells = <1>;
};
cpuclk: clock-complex@18700 {
#clock-cells = <1>;
compatible = "marvell,armada-xp-cpu-clock";
reg = <0x18700 0x24>, <0x1c054 0x10>;
clocks = <&coreclk 1>;
};The driver for the cpuclk registers n clocks, one for each CPU, where each clock has as its parent the second "core clock", i.e <&coreclk 1>.
In the code before your patch, we were doing an of_clk_get(), which was doing a complete "resolution" of the parent clock, and so cpuclk[cpu].parent_name is "cpuclk". This allows the clk framework to properly find "cpuclk" as the parent for the cpu[0-3] clocks, and we get the appropriate behavior:
cpuclk 4 4 1333000000 0 0
cpu3 1 1 1333000000 0 0
cpu2 1 1 1333000000 0 0
cpu1 1 1 1333000000 0 0
cpu0 3 3 1333000000 0 0
dramclk 0 0 666500000 0 0
hclk 0 0 333250000 0 0
nbclk 0 0 666500000 0 0 With your patch, since we don't use clock-output-names in the Device Tree, the of_clk_get_parent_name() helper function returns simply the name of the Device Tree node of the parent, in our case just "mvebu-sar". Which obviously doesn't match any clock name, with the consequence that cpu[0-3] are no longer parented to cpuclk, and therefore their rate is 0 because they don't have a parent:
cpuclk 0 0 1333000000 0 0
dramclk 0 0 666500000 0 0
hclk 0 0 333250000 0 0
nbclk 0 0 666500000 0 0
cpu3 1 1 0 0 0
cpu2 1 1 0 0 0
cpu1 1 1 0 0 0
cpu0 3 3 0 0 0 Stephen, what do you suggest to fix this issue?
The easiest solution is to add a clock-output-names property to the coreclk node. This way, of_clk_get_parent_name() will properly resolve the clock name to its correct name (i.e, "cpuclk" in our case) and everything works fine (I've tested). The drawback of this solution is that it breaks backward compatibility with old DTs: a 4.2 DT for Armada XP would no longer work with a >= 4.3 kernel.
Do you have some other suggestions to make ?
Thanks!
Thomas
Signature · 3 lines
Thomas Petazzoni, CTO, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
Re: [PATCH 14/26] clk: mvebu: Convert to clk_hw based provider APIs
Quoted 18 lines · Thomas Petazzoni
Review static void __init of_cpu_clk_setup(struct device_node *node) · line 215
Quoted 11 lines · Stephen Boyd
(quoted diff) +1
-2@@ -209,9 +208,8 @@ static void __init of_cpu_clk_setup(struct device_node *node) goto bail_out; sprintf(clk_name, "cpu%d", cpu); - parent_clk = of_clk_get(node, 0); - cpuclk[cpu].parent_name = __clk_get_name(parent_clk); + cpuclk[cpu].parent_name = of_clk_get_parent_name(node, 0); cpuclk[cpu].clk_name = clk_name; cpuclk[cpu].cpu = cpu; cpuclk[cpu].reg_base = clock_complex_base;Sorry to chime in only right now, but this patch causes a regression on Armada XP: the cpu clocks are no longer seen as child of their parent and therefore their rate is always 0. This breaks cpufreq on this platform.
[...]
Quoted 2 lines
Stephen, what do you suggest to fix this issue?
Simplest fix is to revert this hunk. Longer term, we should look into making of_clk_get_parent_name() use whatever string has been used when registering the clock, or completely change how we do parent child linkages so that strings aren't necessary.
Quoted 10 lines
The easiest solution is to add a clock-output-names property to the coreclk node. This way,
of_clk_get_parent_name()will properly resolve the clock name to its correct name (i.e, "cpuclk" in our case) and everything works fine (I've tested). The drawback of this solution is that it breaks backward compatibility with old DTs: a 4.2 DT for Armada XP would no longer work with a >= 4.3 kernel.Do you have some other suggestions to make ?
How about this patch?
---8<----
drivers/clk/mvebu/clk-cpu.c +3 -1
@@ -197,6 +197,7 @@ static void __init of_cpu_clk_setup(struct device_node *node)for_each_node_by_type (dn,"cpu" ) {struct clk_init_data init;struct clk *clk; +struct clk *parent_clk;char *clk_name =kzalloc (5 ,GFP_KERNEL );int cpu, err;
@@ -208,8 +209,9 @@ static void __init of_cpu_clk_setup(struct device_node *node) goto bail_out;sprintf (clk_name,"cpu%d" , cpu); + parent_clk =of_clk_get (node,0 ); - cpuclk[cpu].parent_name =of_clk_get_parent_name (node,0 ); + cpuclk[cpu].parent_name =__clk_get_name (parent_clk); cpuclk[cpu].clk_name = clk_name; cpuclk[cpu].cpu = cpu; cpuclk[cpu].reg_base = clock_complex_base;
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH 14/26] clk: mvebu: Convert to clk_hw based provider APIs
Hello,
Thanks for your feedback!
Quoted 3 lines · Stephen Boyd
Quoted 1 line
Stephen, what do you suggest to fix this issue?
Simplest fix is to revert this hunk.
Indeed, this is the simplest fix. But it's going backward with what you were trying to do originally, so it isn't really nice either.
Quoted 2 lines
Longer term, we should look into making
of_clk_get_parent_name()use whatever string has been used when registering the clock,
I am not sure how of_clk_get_parent_name() can know the name of the clock without clock-output-names in the DT. Without clock-output-names, the only way to know the name of the parent clock is to actually ask the driver of the parent clock, no?
Quoted 2 lines
or completely change how we do parent child linkages so that strings aren't necessary.
Keep the reference to the DT node + "arguments". Not super simple either.
Quoted 11 lines
Quoted 9 lines
The easiest solution is to add a clock-output-names property to the coreclk node. This way,
of_clk_get_parent_name()will properly resolve the clock name to its correct name (i.e, "cpuclk" in our case) and everything works fine (I've tested). The drawback of this solution is that it breaks backward compatibility with old DTs: a 4.2 DT for Armada XP would no longer work with a >= 4.3 kernel.Do you have some other suggestions to make ?
How about this patch?
I'll give it a try tomorrow, but since it's essentially a revert of your patch, I believe it should work.
Thanks!
Thomas
Signature · 3 lines
Thomas Petazzoni, CTO, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
Re: [PATCH 14/26] clk: mvebu: Convert to clk_hw based provider APIs
Quoted 9 lines · Thomas Petazzoni
Quoted 3 lines · Stephen Boyd
Quoted 1 line
Stephen, what do you suggest to fix this issue?
Simplest fix is to revert this hunk.
Indeed, this is the simplest fix. But it's going backward with what you were trying to do originally, so it isn't really nice either.
Quoted 7 lines
Quoted 2 lines
Longer term, we should look into making
of_clk_get_parent_name()use whatever string has been used when registering the clock,I am not sure how
of_clk_get_parent_name()can know the name of the clock without clock-output-names in the DT. Without clock-output-names, the only way to know the name of the parent clock is to actually ask the driver of the parent clock, no?
Yes that's the plan. We would try to resolve the name with of_clk_get() and __clk_get_name() if there isn't a clock-output-names property. If #clock-cells > 1 and of_clk_get() fails, we would return NULL, otherwise for #clock-cells == 0 we could fallback on the node name as a last resort. The change here is that we don't use the node name for providers with #clock-cells > 1 because that doesn't make any sense. We'll also try a clk_get() in the case with #clock-cells = 0 and no clock-output-names.
Eventually once we add the ability for OF clk providers to register clk_hw pointers instead of clk pointers we'll be able to "simplify" the of_clk_get() + __clk_get_name() path with a provider clk_hw lookup and clk_hw_get_name() combination, which should be faster and avoid any allocations.
Here's that untested patch, which we can throw into clk-next for v4.4
-----8<----
drivers/clk/clk.c +20 -2
@@ -3055,6 +3055,7 @@ const char *of_clk_get_parent_name(struct device_node *np, int index)u32 pv;int rc;int count; +struct clk *clk;if (index <0 )return NULL ;
@@ -3080,8 +3081,25 @@ const char *of_clk_get_parent_name(struct device_node *np, int index)if (of_property_read_string_index (clkspec.np,"clock-output-names" , index, - &clk_name) <0 ) - clk_name = clkspec.np->name; + &clk_name) <0 ) { +/* +* Best effort to get the name if the clock has been +* registered with the framework. If the clock isn't +* registered, we return the node name as the name of +* the clock as long as #clock-cells = 0. +*/ + clk =of_clk_get (np, index); +if (IS_ERR (clk)) { +if (clkspec.args_count ==0 ) + clk_name = clkspec.np->name; +else + clk_name =NULL ; + }else { + clk_name =__clk_get_name (clk); +clk_put (clk); + } + } +of_node_put (clkspec.np);return clk_name;
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH 14/26] clk: mvebu: Convert to clk_hw based provider APIs
Stephen,
Quoted 34 lines · Stephen Boyd
Here's that untested patch, which we can throw into clk-next for v4.4
-----8<----
drivers/clk/clk.c +13
-2@@ -3055,6 +3055,7 @@ const char *of_clk_get_parent_name(struct device_node *np, int index)u32 pv;int rc;int count; +struct clk *clk;if (index <0 )return NULL ;@@ -3080,8 +3081,25 @@ const char *of_clk_get_parent_name(struct device_node *np, int index)if (of_property_read_string_index (clkspec.np,"clock-output-names" , index, - &clk_name) <0 ) - clk_name = clkspec.np->name; + &clk_name) <0 ) { +/* +* Best effort to get the name if the clock has been +* registered with the framework. If the clock isn't +* registered, we return the node name as the name of +* the clock as long as #clock-cells = 0. +*/ + clk =of_clk_get (np, index); +if (IS_ERR (clk)) { +if (clkspec.args_count ==0 ) + clk_name = clkspec.np->name; +else
drivers/clk/clk.c const char *of_clk_get_parent_name(struct device_node *np, int index) · line 3105
Quoted 10 lines
drivers/clk/clk.c +7
-0+ clk_name =NULL ; + }else { + clk_name =__clk_get_name (clk); +clk_put (clk); + } + } +of_node_put (clkspec.np);return clk_name;
It almost worked, but not completely. The issue is that by the time you call of_clk_get(np, index), index is no longer equal to the value passed as argument to of_clk_get_parent_name(), it has been modified to indicate the index of the *parent* clock.
So, after changing your patch to:
drivers/clk/clk.c +24 -5
@@ -3052,9 +3052,11 @@ const char *of_clk_get_parent_name(struct device_node *np, int index)struct property *prop;const char *clk_name;const __be32 *vp; +int parent_index;u32 pv;int rc;int count; +struct clk *clk;if (index <0 )return NULL ;
@@ -3064,14 +3066,14 @@ const char *of_clk_get_parent_name(struct device_node *np, int index)if (rc)return NULL ; - index = clkspec.args_count ? clkspec.args[0 ] :0 ; + parent_index = clkspec.args_count ? clkspec.args[0 ] :0 ; count =0 ;/* if there is an indices property, use it to transfer the index * specified into an array offset for the clock-output-names property. */ of_property_for_each_u32 (clkspec.np,"clock-indices" , prop, vp, pv) { -if (index == pv) { +if (parent_index == pv) { index = count;break ; }
@@ -3079,9 +3081,26 @@ const char *of_clk_get_parent_name(struct device_node *np, int index) }if (of_property_read_string_index (clkspec.np,"clock-output-names" , - index, - &clk_name) <0 ) - clk_name = clkspec.np->name; + parent_index, + &clk_name) <0 ) { +/* +* Best effort to get the name if the clock has been +* registered with the framework. If the clock isn't +* registered, we return the node name as the name of +* the clock as long as #clock-cells = 0. +*/ + clk =of_clk_get (np, index); +if (IS_ERR (clk)) { +if (clkspec.args_count ==0 ) + clk_name = clkspec.np->name; +else + clk_name =NULL ; + }else { + clk_name =__clk_get_name (clk); +clk_put (clk); + } + } +of_node_put (clkspec.np);return clk_name;
It does work properly for me, on top of 4.3-rc5, without any change to my Device Tree files.
So, what is the plan now ?
- Have the minimal fix in drivers/clk/mvebu/clk-cpu.c for 4.3.
- Have the patch improving the of_clk_get_parent_name() logic merged in 4.4 + a revert of the fix done for 4.3 in clk-cpu.c. Unless maybe you don't want to clutter the core of the clock framework to handle this specific case?
- Add the clock-output-names to the Marvell EBU Device Tree files, so that in a couple of kernel releases we can remove the hacks and rely on the generic logic of of_clk_get_parent_name().
Thanks,
Thomas
Signature · 3 lines
Thomas Petazzoni, CTO, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
Re: [PATCH 14/26] clk: mvebu: Convert to clk_hw based provider APIs
Quoted 13 lines · Thomas Petazzoni
Stephen,
Quoted 2 lines · Stephen Boyd
Here's that untested patch, which we can throw into clk-next for v4.4
It almost worked, but not completely. The issue is that by the time you call
of_clk_get(np, index), index is no longer equal to the value passed as argument toof_clk_get_parent_name(), it has been modified to indicate the index of the *parent* clock.So, after changing your patch to:
[...]
Quoted 2 lines
It does work properly for me, on top of 4.3-rc5, without any change to my Device Tree files.
Good catch! Except we don't need to do all that complicated stuff, right? We can use of_clk_get_from_provider() instead.
---8<----
drivers/clk/clk.c +1 -1
@@ -3088,7 +3088,7 @@ const char *of_clk_get_parent_name(struct device_node *np, int index)* registered, we return the node name as the name of * the clock as long as #clock-cells = 0. */ - clk =of_clk_get (np, index); + clk =of_clk_get_from_provider (clkspec);if (IS_ERR (clk)) {if (clkspec.args_count ==0 ) clk_name = clkspec.np->name;
Quoted 4 lines
So, what is the plan now ?
- Have the minimal fix in
drivers/clk/mvebu/clk-cpu.cfor 4.3.
Yep.
Quoted 5 lines
- Have the patch improving the
of_clk_get_parent_name()logic merged in 4.4 + a revert of the fix done for 4.3 inclk-cpu.c. Unless maybe you don't want to clutter the core of the clock framework to handle this specific case?
Assuming that the patch doesn't cause problems for other platforms, then I think we'll go with this approach.
Quoted 5 lines
- Add the clock-output-names to the Marvell EBU Device Tree files, so that in a couple of kernel releases we can remove the hacks and rely on the generic logic of
of_clk_get_parent_name().
Naw, let's not change any DT files for this.
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH 14/26] clk: mvebu: Convert to clk_hw based provider APIs
Stephen,
Quoted 9 lines · Stephen Boyd
Good catch! Except we don't need to do all that complicated stuff, right? We can use
of_clk_get_from_provider()instead.---8<----
drivers/clk/clk.c +0
-0
drivers/clk/clk.c const char *of_clk_get_parent_name(struct device_node *np, int index) · line 3094
Quoted 8 lines
drivers/clk/clk.c +1
-1@@ -3088,7 +3088,7 @@ const char *of_clk_get_parent_name(struct device_node *np, int index)* registered, we return the node name as the name of * the clock as long as #clock-cells = 0. */ - clk =of_clk_get (np, index); + clk =of_clk_get_from_provider (clkspec);if (IS_ERR (clk)) {if (clkspec.args_count ==0 ) clk_name = clkspec.np->name;
I'll re-test this solution tomorrow, just to make sure.
Quoted 5 lines
Quoted 3 lines
So, what is the plan now ?
- Have the minimal fix in
drivers/clk/mvebu/clk-cpu.cfor 4.3.Yep.
I see in your other e-mail that you already applied the fix, so good.
Quoted 7 lines
Quoted 4 lines
- Have the patch improving the
of_clk_get_parent_name()logic merged in 4.4 + a revert of the fix done for 4.3 inclk-cpu.c. Unless maybe you don't want to clutter the core of the clock framework to handle this specific case?Assuming that the patch doesn't cause problems for other platforms, then I think we'll go with this approach.
Ok. Can you send the patch "properly" so that I can give a formal Tested-by ?
Quoted 6 lines
Quoted 4 lines
- Add the clock-output-names to the Marvell EBU Device Tree files, so that in a couple of kernel releases we can remove the hacks and rely on the generic logic of
of_clk_get_parent_name().Naw, let's not change any DT files for this.
ACK.
Thanks for your help!
Thomas
Signature · 3 lines
Thomas Petazzoni, CTO, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
PATCH 1/1 clk: Make of_clk_get_parent_name() robust with #clock-cells = 1
If a clock provider has #clock-cells = 1 and we call of_clk_get_parent_name() on it we may end up returning the name of the provider node if the provider doesn't have a clock-output-names property. This doesn't make sense, especially when you consider that calling of_clk_get_parent_name() on such a node with different indices will return the same name each time.
Let's try getting the clock from the framework via of_clk_get() instead, and only fallback to the node name if we have a provider with #clock-cells = 0. This way, we can't hand out the same name for different clocks when we don't actually know their names.
--- drivers/clk/clk.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-)
drivers/clk/clk.c +20 -2
@@ -3055,6 +3055,7 @@ const char *of_clk_get_parent_name(struct device_node *np, int index)u32 pv;int rc;int count; +struct clk *clk;if (index <0 )return NULL ;
@@ -3080,8 +3081,25 @@ const char *of_clk_get_parent_name(struct device_node *np, int index)if (of_property_read_string_index (clkspec.np,"clock-output-names" , index, - &clk_name) <0 ) - clk_name = clkspec.np->name; + &clk_name) <0 ) { +/* +* Best effort to get the name if the clock has been +* registered with the framework. If the clock isn't +* registered, we return the node name as the name of +* the clock as long as #clock-cells = 0. +*/ + clk =of_clk_get_from_provider (&clkspec); +if (IS_ERR (clk)) { +if (clkspec.args_count ==0 ) + clk_name = clkspec.np->name; +else + clk_name =NULL ; + }else { + clk_name =__clk_get_name (clk); +clk_put (clk); + } + } +of_node_put (clkspec.np);return clk_name;
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH] clk: Make of_clk_get_parent_name() robust with #clock-cells = 1
Cc'ing Geert.
Quoting Stephen Boyd (2015-10-15 16:19:38)
Quoted 8 lines
If a clock provider has #clock-cells =3D 1 and we call
of_clk_get_parent_name()on it we may end up returning the name of the provider node if the provider doesn't have a clock-output-names property. This doesn't make sense, especially when you consider that callingof_clk_get_parent_name()on such a node with different indices will return the same name each time. =
Quoted 7 lines
Let's try getting the clock from the framework via
of_clk_get()instead, and only fallback to the node name if we have a provider with #clock-cells =3D 0. This way, we can't hand out the same name for different clocks when we don't actually know their names. =Signed-off-by Stephen Boyd <[email protected]>
Geert,
Does this approach fix the issues you had removing clock-output-names from your clock provider DTS?
Regards,
Mike
drivers/clk/clk.c const char *of_clk_get_parent_name(struct device_no=
Quoted 10 lines
--- drivers/clk/clk.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-)=
drivers/clk/clk.c +0
-0@@ -3055,6 +3055,7 @@ const char *of_clk_get_parent_name(struct device_no=
de *np, int index)
drivers/clk/clk.c const char *of_clk_get_parent_name(struct device_n=
Quoted 9 lines
drivers/clk/clk.c +1
-0u32 pv;int rc;int count; +struct clk *clk; =if (index <0 )return NULL;drivers/clk/clk.c +0
-0@@ -3080,8 +3081,25 @@ const char *of_clk_get_parent_name(struct device_n=
ode *np, int index)
drivers/clk/clk.c const char *of_clk_get_parent_name(struct device_n= · line 3083
Quoted 3 lines
drivers/clk/clk.c +0
-0= if (of_property_read_string_index(clkspec.np, "clock-output-names=
",
Quoted 31 lines
drivers/clk/clk.c +19
-2index, - &clk_name) < 0) - clk_name =3D clkspec.np->name; + &clk_name) < 0) { +/* +* Best effort to get the name if the clock has been +* registered with the framework. If the clock isn't +* registered, we return the node name as the name of +* the clock as long as #clock-cells =3D 0. +*/ + clk =3D of_clk_get_from_provider(&clkspec); +if (IS_ERR (clk)) { + if (clkspec.args_count =3D=3D 0) + clk_name =3D clkspec.np->name; +else + clk_name =3D NULL; + }else { + clk_name =3D __clk_get_name(clk); +clk_put (clk); + } + } + =of_node_put(clkspec.np); return clk_name;-- =
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
=20
Re: [PATCH] clk: Make of_clk_get_parent_name() robust with #clock-cells = 1
Hi Mike,
Quoted 13 lines · Michael Turquette
Quoting Stephen Boyd (2015-10-15 16:19:38)
Quoted 12 lines
If a clock provider has #clock-cells = 1 and we call
of_clk_get_parent_name()on it we may end up returning the name of the provider node if the provider doesn't have a clock-output-names property. This doesn't make sense, especially when you consider that callingof_clk_get_parent_name()on such a node with different indices will return the same name each time.Let's try getting the clock from the framework via
of_clk_get()instead, and only fallback to the node name if we have a provider with #clock-cells = 0. This way, we can't hand out the same name for different clocks when we don't actually know their names.
Quoted 6 lines
Quoted 1 line
Signed-off-by Stephen Boyd <[email protected]>Geert,
Does this approach fix the issues you had removing clock-output-names from your clock provider DTS?
I already saw this patch in clk-next, and I think it would fix that issue. However, we're no longer seeing the issue, as we no longer have fixed-factor-clocks in DT.
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH] clk: Make of_clk_get_parent_name() robust with #clock-cells = 1
In reply to Stephen BoydStephen,
Quoted 12 lines · Stephen Boyd
If a clock provider has #clock-cells = 1 and we call
of_clk_get_parent_name()on it we may end up returning the name of the provider node if the provider doesn't have a clock-output-names property. This doesn't make sense, especially when you consider that callingof_clk_get_parent_name()on such a node with different indices will return the same name each time.Let's try getting the clock from the framework via
of_clk_get()instead, and only fallback to the node name if we have a provider with #clock-cells = 0. This way, we can't hand out the same name for different clocks when we don't actually know their names.
Quoted 4 lines
Signed-off-by Stephen Boyd <[email protected]>--- drivers/clk/clk.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-)
I tested on top of 4.3-rc5 and the Armada XP per-CPU clocks are now properly parented with their common parent "cpuclk".
Thanks!
Thomas
Signature · 3 lines
Thomas Petazzoni, CTO, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
Re: [PATCH 14/26] clk: mvebu: Convert to clk_hw based provider APIs
In reply to Stephen BoydStephen,
Quoted 16 lines · Stephen Boyd
How about this patch?
---8<----
drivers/clk/mvebu/clk-cpu.c +1
-0@@ -197,6 +197,7 @@ static void __init of_cpu_clk_setup(struct device_node *node)for_each_node_by_type (dn,"cpu" ) {struct clk_init_data init;struct clk *clk; +struct clk *parent_clk;char *clk_name =kzalloc (5 ,GFP_KERNEL );int cpu, err;
drivers/clk/mvebu/clk-cpu.c static void __init of_cpu_clk_setup(struct device_node *node) · line 217
Quoted 10 lines
drivers/clk/mvebu/clk-cpu.c +2
-1@@ -208,8 +209,9 @@ static void __init of_cpu_clk_setup(struct device_node *node) goto bail_out;sprintf (clk_name,"cpu%d" , cpu); + parent_clk =of_clk_get (node,0 ); - cpuclk[cpu].parent_name =of_clk_get_parent_name (node,0 ); + cpuclk[cpu].parent_name =__clk_get_name (parent_clk); cpuclk[cpu].clk_name = clk_name; cpuclk[cpu].cpu = cpu; cpuclk[cpu].reg_base = clock_complex_base;
Applied on top of 4.3-rc5, this patch fixes the problem for me, without any change to the Device Tree files.
It's probably the easiest option for 4.3. Do you want me to submit a patch, or will you apply it directly to your clk tree?
Thanks!
Thomas
Signature · 3 lines
Thomas Petazzoni, CTO, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
Re: [PATCH 14/26] clk: mvebu: Convert to clk_hw based provider APIs
Quoted 6 lines · Thomas Petazzoni
Applied on top of 4.3-rc5, this patch fixes the problem for me, without any change to the Device Tree files.
It's probably the easiest option for 4.3. Do you want me to submit a patch, or will you apply it directly to your clk tree?
I've already applied it to clk-fixes, I'll send it off tomorrow or the next day.
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH 15/26 clk: stm32f4: Convert to clk_hw based provider APIs
In reply to Stephen BoydWe're removing struct clk from the clk provider API, so switch this code to using the clk_hw based provider APIs.
--- drivers/clk/clk-stm32f4.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
drivers/clk/clk-stm32f4.c +1 -2
@@ -178,8 +178,7 @@ static long clk_apb_mul_round_rate(struct clk_hw *hw, unsigned long rate,if (clk_hw_get_flags (hw) &CLK_SET_RATE_PARENT ) {unsigned long best_parent = rate / mult; - *prate = -__clk_round_rate (__clk_get_parent (hw->clk), best_parent); + *prate =clk_hw_round_rate (clk_hw_get_parent (hw), best_parent); }return *prate * mult;
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH 16/26 clk: qcom: Convert to clk_hw based provider APIs
In reply to Stephen BoydWe're removing struct clk from the clk provider API, so switch this code to using the clk_hw based provider APIs.
--- drivers/clk/qcom/clk-pll.c | 8 ++------ drivers/clk/qcom/clk-rcg.c | 17 ++++++++--------- drivers/clk/qcom/clk-rcg2.c | 29 +++++++++++++---------------- drivers/clk/qcom/mmcc-msm8960.c | 10 ++++++---- 4 files changed, 29 insertions(+), 35 deletions(-)
drivers/clk/qcom/clk-pll.c +2 -6
@@ -138,13 +138,9 @@ struct pll_freq_tbl *find_freq(const struct pll_freq_tbl *f, unsigned long rate)static int clk_pll_determine_rate (struct clk_hw *hw,struct clk_rate_request *req) { -struct clk *parent =__clk_get_parent (hw->clk);struct clk_pll *pll =to_clk_pll (hw);const struct pll_freq_tbl *f; - req->best_parent_hw =__clk_get_hw (parent); - req->best_parent_rate =__clk_get_rate (parent); - f =find_freq (pll->freq_tbl, req->rate);if (!f) req->rate =clk_pll_recalc_rate (hw, req->best_parent_rate);
@@ -198,7 +194,7 @@ static int wait_for_pll(struct clk_pll *pll)u32 val;int count;int ret; -const char *name =__clk_get_name (pll->clkr.hw.clk); +const char *name =clk_hw_get_name (&pll->clkr.hw);/* Wait for pll to enable. */ for (count =200 ; count >0 ; count--) {
@@ -217,7 +213,7 @@ static int wait_for_pll(struct clk_pll *pll)static int clk_pll_vote_enable (struct clk_hw *hw) {int ret; -struct clk_pll *p =to_clk_pll (__clk_get_hw (__clk_get_parent (hw->clk))); +struct clk_pll *p =to_clk_pll (clk_hw_get_parent (hw)); ret =clk_enable_regmap (hw);if (ret)
drivers/clk/qcom/clk-rcg.c +8 -9
@@ -59,7 +59,7 @@ static u8 clk_rcg_get_parent(struct clk_hw *hw) err:pr_debug ("%s: Clock %s has invalid parent, using default.\n" , - __func__,__clk_get_name (hw->clk)); + __func__,clk_hw_get_name (hw));return 0 ; }
@@ -95,7 +95,7 @@ static u8 clk_dyn_rcg_get_parent(struct clk_hw *hw) err:pr_debug ("%s: Clock %s has invalid parent, using default.\n" , - __func__,__clk_get_name (hw->clk)); + __func__,clk_hw_get_name (hw));return 0 ; }
@@ -409,7 +409,7 @@ static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f, const struct parent_map *parent_map) {unsigned long clk_flags, rate = req->rate; -struct clk *p; +struct clk_hw *p;int index; f =qcom_find_freq (f, rate);
@@ -421,7 +421,7 @@ static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f,return index; clk_flags =clk_hw_get_flags (hw); - p =clk_get_parent_by_index (hw->clk, index); + p =clk_hw_get_parent_by_index (hw, index);if (clk_flags &CLK_SET_RATE_PARENT ) { rate = rate * f->pre_div;if (f->n) {
@@ -431,9 +431,9 @@ static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f, rate = tmp; } }else { - rate =__clk_get_rate (p); + rate =clk_hw_get_rate (p); } - req->best_parent_hw =__clk_get_hw (p); + req->best_parent_hw = p; req->best_parent_rate = rate; req->rate = f->freq;
@@ -472,9 +472,8 @@ static int clk_rcg_bypass_determine_rate(struct clk_hw *hw,struct clk *p;int index =qcom_find_src_index (hw, rcg->s.parent_map, f->src); - p =clk_get_parent_by_index (hw->clk, index); - req->best_parent_hw =__clk_get_hw (p); - req->best_parent_rate =__clk_round_rate (p, req->rate); + req->best_parent_hw = p =clk_hw_get_parent_by_index (hw, index); + req->best_parent_rate =clk_hw_round_rate (p, req->rate); req->rate = req->best_parent_rate;return 0 ;
drivers/clk/qcom/clk-rcg2.c +13 -16
@@ -80,7 +80,7 @@ static u8 clk_rcg2_get_parent(struct clk_hw *hw) err:pr_debug ("%s: Clock %s has invalid parent, using default.\n" , - __func__,__clk_get_name (hw->clk)); + __func__,clk_hw_get_name (hw));return 0 ; }
@@ -89,7 +89,7 @@ static int update_config(struct clk_rcg2 *rcg)int count, ret;u32 cmd;struct clk_hw *hw = &rcg->clkr.hw; -const char *name =__clk_get_name (hw->clk); +const char *name =clk_hw_get_name (hw); ret =regmap_update_bits (rcg->clkr.regmap, rcg->cmd_rcgr +CMD_REG ,CMD_UPDATE ,CMD_UPDATE );
@@ -180,7 +180,7 @@ static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f, struct clk_rate_request *req) { unsigned long clk_flags, rate = req->rate; -struct clk *p; +struct clk_hw *p;struct clk_rcg2 *rcg =to_clk_rcg2 (hw);int index;
@@ -193,7 +193,7 @@ static int _freq_tbl_determine_rate(struct clk_hw *hw,return index; clk_flags =clk_hw_get_flags (hw); - p =clk_get_parent_by_index (hw->clk, index); + p =clk_hw_get_parent_by_index (hw, index);if (clk_flags &CLK_SET_RATE_PARENT ) {if (f->pre_div) { rate /=2 ;
@@ -207,9 +207,9 @@ static int _freq_tbl_determine_rate(struct clk_hw *hw, rate = tmp; } }else { - rate =__clk_get_rate (p); + rate =clk_hw_get_rate (p); } - req->best_parent_hw =__clk_get_hw (p); + req->best_parent_hw = p; req->best_parent_rate = rate; req->rate = f->freq;
@@ -384,11 +384,10 @@ static int clk_edp_pixel_determine_rate(struct clk_hw *hw,u32 mask =BIT (rcg->hid_width) -1 ;u32 hid_div;int index =qcom_find_src_index (hw, rcg->parent_map, f->src); -struct clk *p =clk_get_parent_by_index (hw->clk, index);/* Force the correct parent */ - req->best_parent_hw =__clk_get_hw (p); - req->best_parent_rate =__clk_get_rate (p); + req->best_parent_hw =clk_hw_get_parent_by_index (hw, index); + req->best_parent_rate =clk_hw_get_rate (req->best_parent_hw);if (req->best_parent_rate ==810000000 ) frac = frac_table_810m;
@@ -436,14 +435,13 @@ static int clk_byte_determine_rate(struct clk_hw *hw,int index =qcom_find_src_index (hw, rcg->parent_map, f->src);unsigned long parent_rate, div;u32 mask =BIT (rcg->hid_width) -1 ; -struct clk *p; +struct clk_hw *p;if (req->rate ==0 )return -EINVAL ; - p =clk_get_parent_by_index (hw->clk, index); - req->best_parent_hw =__clk_get_hw (p); - req->best_parent_rate = parent_rate =__clk_round_rate (p, req->rate); + req->best_parent_hw = p =clk_hw_get_parent_by_index (hw, index); + req->best_parent_rate = parent_rate =clk_hw_round_rate (p, req->rate); div =DIV_ROUND_UP ((2 * parent_rate), req->rate) -1 ; div =min_t (u32, div, mask);
@@ -504,14 +502,13 @@ static int clk_pixel_determine_rate(struct clk_hw *hw,const struct freq_tbl *f = rcg->freq_tbl;const struct frac_entry *frac = frac_table_pixel;int index =qcom_find_src_index (hw, rcg->parent_map, f->src); -struct clk *parent =clk_get_parent_by_index (hw->clk, index); - req->best_parent_hw =__clk_get_hw (parent); + req->best_parent_hw =clk_hw_get_parent_by_index (hw, index);for (; frac->num; frac++) { request = (req->rate * frac->den) / frac->num; - src_rate =__clk_round_rate (parent, request); + src_rate =clk_hw_round_rate (req->best_parent_hw, request);if ((src_rate < (request - delta)) || (src_rate > (request + delta)))continue ;
drivers/clk/qcom/mmcc-msm8960.c +6 -4
@@ -509,7 +509,6 @@ static int pix_rdi_set_parent(struct clk_hw *hw, u8 index)int ret =0 ;u32 val;struct clk_pix_rdi *rdi =to_clk_pix_rdi (hw); -struct clk *clk = hw->clk;int num_parents =clk_hw_get_num_parents (hw);/*
@@ -521,7 +520,8 @@ static int pix_rdi_set_parent(struct clk_hw *hw, u8 index)* needs to be on at what time. */ for (i =0 ; i < num_parents; i++) { - ret =clk_prepare_enable (clk_get_parent_by_index (clk, i)); +struct clk_hw *p =clk_hw_get_parent_by_index (hw, i); + ret =clk_prepare_enable (p->clk);if (ret) goto err; }
@@ -549,8 +549,10 @@ static int pix_rdi_set_parent(struct clk_hw *hw, u8 index)udelay (1 ); err: -for (i--; i >=0 ; i--) -clk_disable_unprepare (clk_get_parent_by_index (clk, i)); +for (i--; i >=0 ; i--) { +struct clk_hw *p =clk_hw_get_parent_by_index (hw, i); +clk_disable_unprepare (p->clk); + }return ret; }
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH 17/26 clk: rockchip: Convert to clk_hw based provider APIs
In reply to Stephen BoydWe're removing struct clk from the clk provider API, so switch this code to using the clk_hw based provider APIs.
--- drivers/clk/rockchip/clk-pll.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-)
drivers/clk/rockchip/clk-pll.c +9 -9
@@ -136,7 +136,7 @@ static unsigned long rockchip_rk3066_pll_recalc_rate(struct clk_hw *hw, pllcon =readl_relaxed (pll->reg_base +RK3066_PLLCON (3 ));if (pllcon &RK3066_PLLCON3_BYPASS ) {pr_debug ("%s: pll %s is bypassed\n" , __func__, -__clk_get_name (hw->clk)); +clk_hw_get_name (hw));return prate; }
@@ -174,13 +174,13 @@ static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate, }pr_debug ("%s: changing %s from %lu to %lu with a parent rate of %lu\n" , - __func__,__clk_get_name (hw->clk), old_rate, drate, prate); + __func__,clk_hw_get_name (hw), old_rate, drate, prate);/* Get required rate settings from table */ rate =rockchip_get_pll_settings (pll, drate);if (!rate) {pr_err ("%s: Invalid rate : %lu for pll clk %s\n" , __func__, - drate,__clk_get_name (hw->clk)); + drate,clk_hw_get_name (hw));return -EINVAL ; }
@@ -268,7 +268,7 @@ static void rockchip_rk3066_pll_init(struct clk_hw *hw)if (!(pll->flags &ROCKCHIP_PLL_SYNC_RATE ))return ; - drate =__clk_get_rate (hw->clk); + drate =clk_hw_get_rate (hw); rate =rockchip_get_pll_settings (pll, drate);/* when no rate setting for the current rate, rely on clk_set_rate */
@@ -286,22 +286,22 @@ static void rockchip_rk3066_pll_init(struct clk_hw *hw) nb = ((pllcon >>RK3066_PLLCON2_NB_SHIFT ) &RK3066_PLLCON2_NB_MASK ) +1 ;pr_debug ("%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), nb(%d:%d)\n" , - __func__,__clk_get_name (hw->clk), drate, rate->nr, nr, + __func__,clk_hw_get_name (hw), drate, rate->nr, nr, rate->no, no, rate->nf, nf, rate->nb, nb);if (rate->nr != nr || rate->no != no || rate->nf != nf || rate->nb != nb) { -struct clk *parent =__clk_get_parent (hw->clk); +struct clk_hw *parent =clk_hw_get_parent (hw);unsigned long prate;if (!parent) {pr_warn ("%s: parent of %s not available\n" , - __func__,__clk_get_name (hw->clk)); + __func__,clk_hw_get_parent (hw));return ; }pr_debug ("%s: pll %s: rate params do not match rate table, adjusting\n" , - __func__,__clk_get_name (hw->clk)); - prate =__clk_get_rate (parent); + __func__,clk_hw_get_name (hw)); + prate =clk_hw_get_rate (parent);rockchip_rk3066_pll_set_rate (hw, drate, prate); } }
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH 17/26] clk: rockchip: Convert to clk_hw based provider APIs
Am Freitag, 31. Juli 2015, 10:03:57 schrieb Stephen Boyd:
Quoted 5 lines
We're removing struct clk from the clk provider API, so switch this code to using the
clk_hwbased provider APIs.Cc Heiko Stuebner <[email protected]>Signed-off-by Stephen Boyd <[email protected]>
Looks correct to me and there are no functional changes in here anyway
Heiko
Re: [PATCH 17/26] clk: rockchip: Convert to clk_hw based provider APIs
Quoted 9 lines · Heiko Stübner
Am Freitag, 31. Juli 2015, 10:03:57 schrieb Stephen Boyd:
Quoted 5 lines
We're removing struct clk from the clk provider API, so switch this code to using the
clk_hwbased provider APIs.Cc Heiko Stuebner <[email protected]>Signed-off-by Stephen Boyd <[email protected]>Looks correct to me and there are no functional changes in here anyway
Reviewed-by Heiko Stuebner <[email protected]>
Thanks. There was one bug, but I fixed it ;-)
---8<---
drivers/clk/rockchip/clk-pll.c +1 -1
@@ -295,7 +295,7 @@ static void rockchip_rk3066_pll_init(struct clk_hw *hw)if (!parent) {pr_warn ("%s: parent of %s not available\n" , - __func__,clk_hw_get_parent (hw)); + __func__,clk_hw_get_name (hw));return ; }
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH 18/26 clk: samsung: Convert to clk_hw based provider APIs
In reply to Stephen BoydWe're removing struct clk from the clk provider API, so switch this code to using the clk_hw based provider APIs.
--- drivers/clk/samsung/clk-cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/clk/samsung/clk-cpu.c +2 -2
@@ -100,8 +100,8 @@ static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos,static long exynos_cpuclk_round_rate (struct clk_hw *hw,unsigned long drate,unsigned long *prate) { -struct clk *parent =__clk_get_parent (hw->clk); - *prate =__clk_round_rate (parent, drate); +struct clk_hw *parent =clk_hw_get_parent (hw); + *prate =clk_hw_round_rate (parent, drate);return *prate; }
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH 18/26] clk: samsung: Convert to clk_hw based provider APIs
Quoted 8 lines · Stephen Boyd
We're removing struct clk from the clk provider API, so switch this code to using the
clk_hwbased provider APIs.Cc Chanwoo Choi <[email protected]>Cc Sylwester Nawrocki <[email protected]>Cc Krzysztof Kozlowski <[email protected]>Cc Kukjin Kim <[email protected]>Signed-off-by Stephen Boyd <[email protected]>
Quoted 18 lines
--- drivers/clk/samsung/clk-cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)drivers/clk/samsung/clk-cpu.c +2
-2@@ -100,8 +100,8 @@ static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos,static long exynos_cpuclk_round_rate (struct clk_hw *hw,unsigned long drate,unsigned long *prate) { -struct clk *parent =__clk_get_parent (hw->clk); - *prate =__clk_round_rate (parent, drate); +struct clk_hw *parent =clk_hw_get_parent (hw); + *prate =clk_hw_round_rate (parent, drate);return *prate; }
PATCH 19/26 clk: sirf: Convert to clk_hw based provider APIs
In reply to Stephen BoydWe're removing struct clk from the clk provider API, so switch this code to using the clk_hw based provider APIs.
--- drivers/clk/sirf/clk-common.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)
drivers/clk/sirf/clk-common.c +6 -6
@@ -167,10 +167,10 @@ static long cpu_clk_round_rate(struct clk_hw *hw, unsigned long rate,* SiRF SoC has not cpu clock control, * So bypass to it's parent pll. */ -struct clk *parent_clk =clk_get_parent (hw->clk); -struct clk *pll_parent_clk =clk_get_parent (parent_clk); -unsigned long pll_parent_rate =clk_get_rate (pll_parent_clk); -return pll_clk_round_rate (__clk_get_hw (parent_clk), rate, &pll_parent_rate); +struct clk_hw *parent_clk =clk_hw_get_parent (hw); +struct clk_hw *pll_parent_clk =clk_hw_get_parent (parent_clk); +unsigned long pll_parent_rate =clk_hw_get_rate (pll_parent_clk); +return pll_clk_round_rate (parent_clk, rate, &pll_parent_rate); } static unsigned long cpu_clk_recalc_rate(struct clk_hw *hw,
@@ -180,8 +180,8 @@ static unsigned long cpu_clk_recalc_rate(struct clk_hw *hw,* SiRF SoC has not cpu clock control, * So return the parent pll rate. */ -struct clk *parent_clk =clk_get_parent (hw->clk); -return __clk_get_rate (parent_clk); +struct clk_hw *parent_clk =clk_hw_get_parent (hw); +return clk_hw_get_rate (parent_clk); }static struct clk_ops std_pll_ops = {
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH 20/26 clk: spear: Convert to clk_hw based provider APIs
In reply to Stephen BoydWe're removing struct clk from the clk provider API, so switch this code to using the clk_hw based provider APIs.
--- drivers/clk/spear/clk-vco-pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/clk/spear/clk-vco-pll.c +1 -1
@@ -87,7 +87,7 @@ static long clk_pll_round_rate_index(struct clk_hw *hw, unsigned long drate,struct clk_pll *pll =to_clk_pll (hw);unsigned long prev_rate, vco_prev_rate, rate =0 ;unsigned long vco_parent_rate = -__clk_get_rate (__clk_get_parent (__clk_get_parent (hw->clk))); +clk_hw_get_rate (clk_hw_get_parent (clk_hw_get_parent (hw)));if (!prate) {pr_err ("%s: prate is must for pll clk\n" , __func__);
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH 20/26] clk: spear: Convert to clk_hw based provider APIs
Quoted 14 lines · Stephen Boyd
We're removing struct clk from the clk provider API, so switch this code to using the
clk_hwbased provider APIs.Cc Viresh Kumar <[email protected]>Signed-off-by Stephen Boyd <[email protected]>--- drivers/clk/spear/clk-vco-pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)drivers/clk/spear/clk-vco-pll.c +0
-0
drivers/clk/spear/clk-vco-pll.c static long clk_pll_round_rate_index(struct clk_hw *hw, unsigned long drate, · line 90
Quoted 5 lines
drivers/clk/spear/clk-vco-pll.c +1
-1@@ -87,7 +87,7 @@ static long clk_pll_round_rate_index(struct clk_hw *hw, unsigned long drate,struct clk_pll *pll =to_clk_pll (hw);unsigned long prev_rate, vco_prev_rate, rate =0 ;unsigned long vco_parent_rate = -__clk_get_rate (__clk_get_parent (__clk_get_parent (hw->clk))); +clk_hw_get_rate (clk_hw_get_parent (clk_hw_get_parent (hw)));
Signature · 1 line
viresh
PATCH 21/26 clk: sunxi: Convert to clk_hw based provider APIs
In reply to Stephen BoydWe're removing struct clk from the clk provider API, so switch this code to using the clk_hw based provider APIs.
--- drivers/clk/sunxi/clk-factors.c | 10 +++++----- drivers/clk/sunxi/clk-sun6i-ar100.c | 8 ++++---- drivers/clk/sunxi/clk-sunxi.c | 10 +++++----- 3 files changed, 14 insertions(+), 14 deletions(-)
drivers/clk/sunxi/clk-factors.c +5 -5
@@ -82,20 +82,20 @@ static long clk_factors_round_rate(struct clk_hw *hw, unsigned long rate,static int clk_factors_determine_rate (struct clk_hw *hw,struct clk_rate_request *req) { -struct clk *clk = hw->clk, *parent, *best_parent =NULL ; +struct clk_hw *parent, *best_parent =NULL ;int i, num_parents;unsigned long parent_rate, best =0 , child_rate, best_child_rate =0 ;/* find the parent that can help provide the fastest rate <= rate */ num_parents =clk_hw_get_num_parents (hw);for (i =0 ; i < num_parents; i++) { - parent =clk_get_parent_by_index (clk, i); + parent =clk_hw_get_parent_by_index (hw, i);if (!parent)continue ;if (clk_hw_get_flags (hw) &CLK_SET_RATE_PARENT ) - parent_rate =__clk_round_rate (parent, req->rate); + parent_rate =clk_hw_round_rate (parent, req->rate);else - parent_rate =__clk_get_rate (parent); + parent_rate =clk_hw_get_rate (parent); child_rate =clk_factors_round_rate (hw, req->rate, &parent_rate);
@@ -110,7 +110,7 @@ static int clk_factors_determine_rate(struct clk_hw *hw,if (!best_parent)return -EINVAL ; - req->best_parent_hw =__clk_get_hw (best_parent); + req->best_parent_hw = best_parent; req->best_parent_rate = best; req->rate = best_child_rate;
drivers/clk/sunxi/clk-sun6i-ar100.c +4 -4
@@ -56,12 +56,12 @@ static int ar100_determine_rate(struct clk_hw *hw,for (i =0 ; i < nparents; i++) {unsigned long parent_rate;unsigned long tmp_rate; -struct clk *parent; +struct clk_hw *parent;unsigned long div;int shift; - parent =clk_get_parent_by_index (hw->clk, i); - parent_rate =__clk_get_rate (parent); + parent =clk_hw_get_parent_by_index (hw, i); + parent_rate =clk_hw_get_rate (parent); div =DIV_ROUND_UP (parent_rate, req->rate);/*
@@ -99,7 +99,7 @@ static int ar100_determine_rate(struct clk_hw *hw, tmp_rate = (parent_rate >> shift) / div;if (!req->best_parent_hw || tmp_rate > best_rate) { - req->best_parent_hw =__clk_get_hw (parent); + req->best_parent_hw = parent; req->best_parent_rate = parent_rate; best_rate = tmp_rate; }
drivers/clk/sunxi/clk-sunxi.c +5 -5
@@ -123,20 +123,20 @@ static long sun6i_ahb1_clk_round(unsigned long rate, u8 *divp, u8 *pre_divp,static int sun6i_ahb1_clk_determine_rate (struct clk_hw *hw,struct clk_rate_request *req) { -struct clk *clk = hw->clk, *parent, *best_parent =NULL ; +struct clk_hw *parent, *best_parent =NULL ;int i, num_parents;unsigned long parent_rate, best =0 , child_rate, best_child_rate =0 ;/* find the parent that can help provide the fastest rate <= rate */ num_parents =clk_hw_get_num_parents (hw);for (i =0 ; i < num_parents; i++) { - parent =clk_get_parent_by_index (clk, i); + parent =clk_hw_get_parent_by_index (hw, i);if (!parent)continue ;if (clk_hw_get_flags (hw) &CLK_SET_RATE_PARENT ) - parent_rate =__clk_round_rate (parent, req->rate); + parent_rate =clk_hw_round_rate (parent, req->rate);else - parent_rate =__clk_get_rate (parent); + parent_rate =clk_hw_get_rate (parent); child_rate =sun6i_ahb1_clk_round (req->rate,NULL ,NULL , i, parent_rate);
@@ -151,7 +151,7 @@ static int sun6i_ahb1_clk_determine_rate(struct clk_hw *hw,if (!best_parent)return -EINVAL ; - req->best_parent_hw =__clk_get_hw (best_parent); + req->best_parent_hw = best_parent; req->best_parent_rate = best; req->rate = best_child_rate;
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH 22/26 clk: tegra: Convert to clk_hw based provider APIs
In reply to Stephen BoydWe're removing struct clk from the clk provider API, so switch this code to using the clk_hw based provider APIs.
--- drivers/clk/tegra/clk-emc.c | 10 +++++----- drivers/clk/tegra/clk-pll.c | 10 +++++----- 2 files changed, 10 insertions(+), 10 deletions(-)
drivers/clk/tegra/clk-emc.c +5 -5
@@ -103,7 +103,7 @@ static unsigned long emc_recalc_rate(struct clk_hw *hw,* CCF wrongly assumes that the parent won't change during set_rate, * so get the parent rate explicitly. */ - parent_rate =__clk_get_rate (__clk_get_parent (hw->clk)); + parent_rate =clk_hw_get_rate (clk_hw_get_parent (hw)); val =readl (tegra->clk_regs +CLK_SOURCE_EMC ); div = val &CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK ;
@@ -151,7 +151,7 @@ static int emc_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)return 0 ; } - req->rate =__clk_get_rate (hw->clk); + req->rate =clk_hw_get_rate (hw);return 0 ; }
@@ -314,7 +314,7 @@ static int emc_set_rate(struct clk_hw *hw, unsigned long rate, tegra = container_of(hw, struct tegra_clk_emc, hw); -if (__clk_get_rate (hw->clk) == rate) +if (clk_hw_get_rate (hw) == rate)return 0 ;/*
@@ -527,8 +527,8 @@ struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np,if (IS_ERR (clk))return clk; - tegra->prev_parent =clk_get_parent_by_index ( - tegra->hw.clk,emc_get_parent (&tegra->hw)); + tegra->prev_parent =clk_hw_get_parent_by_index ( + &tegra->hw,emc_get_parent (&tegra->hw))->clk; tegra->changing_timing = false;/* Allow debugging tools to see the EMC clock */
drivers/clk/tegra/clk-pll.c +5 -5
@@ -634,7 +634,7 @@ static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,/* PLLM is used for memory; we do not change rate */ if (pll->params->flags &TEGRA_PLLM ) -return __clk_get_rate (hw->clk); +return clk_hw_get_rate (hw);if (_get_table_rate (hw, &cfg, rate, *prate) &&_calc_rate (hw, &cfg, rate, *prate))
@@ -1577,7 +1577,7 @@ struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,if (!pll_params->pdiv_tohw)return ERR_PTR (-EINVAL ); - parent_rate =__clk_get_rate (parent); + parent_rate =clk_get_rate (parent); pll_params->vco_min =_clip_vco_min (pll_params->vco_min, parent_rate);
@@ -1674,7 +1674,7 @@ struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,return ERR_PTR (-EINVAL ); } - parent_rate =__clk_get_rate (parent); + parent_rate =clk_get_rate (parent); pll_params->vco_min =_clip_vco_min (pll_params->vco_min, parent_rate);
@@ -1715,7 +1715,7 @@ struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,return ERR_PTR (-EINVAL ); } - parent_rate =__clk_get_rate (parent); + parent_rate =clk_get_rate (parent); pll_params->vco_min =_clip_vco_min (pll_params->vco_min, parent_rate);
@@ -1848,7 +1848,7 @@ struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, val &= ~PLLSS_REF_SRC_SEL_MASK ;pll_writel_base (val, pll); - parent_rate =__clk_get_rate (parent); + parent_rate =clk_get_rate (parent); pll_params->vco_min =_clip_vco_min (pll_params->vco_min, parent_rate);
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH 23/26 clk: tegra: Convert to clk_hw based provider APIs
In reply to Stephen BoydWe're removing struct clk from the clk provider API, so switch this code to using the clk_hw based provider APIs.
--- drivers/clk/ti/autoidle.c | 8 ++++---- drivers/clk/ti/clkt_dpll.c | 11 ++++++----- drivers/clk/ti/clock.h | 2 +- drivers/clk/ti/divider.c | 6 +++--- drivers/clk/ti/dpll3xxx.c | 31 ++++++++++++++----------------- drivers/clk/ti/dpll44xx.c | 4 ++-- drivers/clk/ti/gate.c | 6 +++--- 7 files changed, 33 insertions(+), 35 deletions(-)
drivers/clk/ti/autoidle.c +4 -4
@@ -169,21 +169,21 @@ int __init of_ti_clk_autoidle_setup(struct device_node *node)/** * omap2_init_clk_hw_omap_clocks - initialize an OMAP clock -* @clk: struct clk * to initialize +* @hw: struct clk_hw * to initialize * * Add an OMAP clock @clk to the internal list of OMAP clocks. Used * temporarily for autoidle handling, until this support can be * integrated into the common clock framework code in some way. No * return value. */ -void omap2_init_clk_hw_omap_clocks (struct clk *clk) +void omap2_init_clk_hw_omap_clocks (struct clk_hw *hw) {struct clk_hw_omap *c; -if (__clk_get_flags (clk) &CLK_IS_BASIC ) +if (clk_hw_get_flags (hw) &CLK_IS_BASIC )return ; - c =to_clk_hw_omap (__clk_get_hw (clk)); + c =to_clk_hw_omap (hw);list_add (&c->node, &clk_hw_omap_clocks); }
drivers/clk/ti/clkt_dpll.c +6 -5
@@ -16,6 +16,7 @@#include <linux/kernel.h> #include <linux/errno.h> +#include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/io.h> #include <linux/clk/ti.h>
@@ -75,7 +76,7 @@ static int _dpll_test_fint(struct clk_hw_omap *clk, unsigned int n) dd = clk->dpll_data;/* DPLL divider must result in a valid jitter correction val */ - fint =__clk_get_rate (__clk_get_parent (clk->hw.clk)) / n; + fint =clk_hw_get_rate (clk_hw_get_parent (&clk->hw)) / n;if (dd->flags &DPLL_J_TYPE ) { fint_min =OMAP3PLUS_DPLL_FINT_JTYPE_MIN ;
@@ -253,7 +254,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) v >>=__ffs (dd->enable_mask);if (_omap2_dpll_is_in_bypass (v)) -return __clk_get_rate (dd->clk_bypass); +return clk_get_rate (dd->clk_bypass); v = ti_clk_ll_ops->clk_readl (dd->mult_div1_reg); dpll_mult = v & dd->mult_mask;
@@ -261,7 +262,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) dpll_div = v & dd->div1_mask; dpll_div >>=__ffs (dd->div1_mask); - dpll_clk = (long long )__clk_get_rate (dd->clk_ref) * dpll_mult; + dpll_clk = (long long )clk_get_rate (dd->clk_ref) * dpll_mult;do_div (dpll_clk, dpll_div +1 );return dpll_clk;
@@ -300,8 +301,8 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, dd = clk->dpll_data; - ref_rate =__clk_get_rate (dd->clk_ref); - clk_name =__clk_get_name (hw->clk); + ref_rate =clk_get_rate (dd->clk_ref); + clk_name =clk_hw_get_name (hw);pr_debug ("clock: %s: starting DPLL round_rate, target rate %lu\n" , clk_name, target_rate);
drivers/clk/ti/clock.h +1 -1
@@ -204,7 +204,7 @@ int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw, ti_of_clk_init_cb_t func);int ti_clk_add_component (struct device_node *node,struct clk_hw *hw,int type); -void omap2_init_clk_hw_omap_clocks (struct clk *clk); +void omap2_init_clk_hw_omap_clocks (struct clk_hw *hw);int of_ti_clk_autoidle_setup (struct device_node *node);void omap2_clk_enable_init_clocks (const char **clk_names,u8 num_clocks);
drivers/clk/ti/divider.c +3 -3
@@ -109,7 +109,7 @@ static unsigned long ti_clk_divider_recalc_rate(struct clk_hw *hw,if (!div) {WARN (!(divider->flags &CLK_DIVIDER_ALLOW_ZERO ),"%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n" , -__clk_get_name (hw->clk)); +clk_hw_get_name (hw));return parent_rate; }
@@ -181,7 +181,7 @@ static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate, *best_parent_rate = parent_rate_saved;return i; } - parent_rate =__clk_round_rate (__clk_get_parent (hw->clk), + parent_rate =clk_hw_round_rate (clk_hw_get_parent (hw),MULT_ROUND_UP (rate, i)); now =DIV_ROUND_UP (parent_rate, i);if (now <= rate && now > best) {
@@ -194,7 +194,7 @@ static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,if (!bestdiv) { bestdiv =_get_maxdiv (divider); *best_parent_rate = -__clk_round_rate (__clk_get_parent (hw->clk),1 ); +clk_hw_round_rate (clk_hw_get_parent (hw),1 ); }return bestdiv;
drivers/clk/ti/dpll3xxx.c +14 -17
@@ -69,7 +69,7 @@ static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state)const char *clk_name; dd = clk->dpll_data; - clk_name =__clk_get_name (clk->hw.clk); + clk_name =clk_hw_get_name (&clk->hw); state <<=__ffs (dd->idlest_mask);
@@ -98,7 +98,7 @@ static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n)unsigned long fint;u16 f =0 ; - fint =__clk_get_rate (clk->dpll_data->clk_ref) / n; + fint =clk_get_rate (clk->dpll_data->clk_ref) / n;pr_debug ("clock: fint is %lu\n" , fint);
@@ -145,7 +145,7 @@ static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk)u8 state =1 ;int r =0 ; -pr_debug ("clock: locking DPLL %s\n" ,__clk_get_name (clk->hw.clk)); +pr_debug ("clock: locking DPLL %s\n" ,clk_hw_get_name (&clk->hw)); dd = clk->dpll_data; state <<=__ffs (dd->idlest_mask);
@@ -193,7 +193,7 @@ static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *clk)return -EINVAL ;pr_debug ("clock: configuring DPLL %s for low-power bypass\n" , -__clk_get_name (clk->hw.clk)); +clk_hw_get_name (&clk->hw)); ai =omap3_dpll_autoidle_read (clk);
@@ -223,7 +223,7 @@ static int _omap3_noncore_dpll_stop(struct clk_hw_omap *clk)if (!(clk->dpll_data->modes & (1 <<DPLL_LOW_POWER_STOP )))return -EINVAL ; -pr_debug ("clock: stopping DPLL %s\n" ,__clk_get_name (clk->hw.clk)); +pr_debug ("clock: stopping DPLL %s\n" ,clk_hw_get_name (&clk->hw)); ai =omap3_dpll_autoidle_read (clk);
@@ -251,7 +251,7 @@ static void _lookup_dco(struct clk_hw_omap *clk, u8 *dco, u16 m, u8 n) {unsigned long fint, clkinp;/* watch out for overflow */ - clkinp =__clk_get_rate (__clk_get_parent (clk->hw.clk)); + clkinp =clk_hw_get_rate (clk_hw_get_parent (&clk->hw)); fint = (clkinp / n) * m;if (fint <1000000000 )
@@ -277,7 +277,7 @@ static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n)unsigned long clkinp, sd;/* watch out for overflow */ int mod1, mod2; - clkinp =__clk_get_rate (__clk_get_parent (clk->hw.clk)); + clkinp =clk_hw_get_rate (clk_hw_get_parent (&clk->hw));/* * target sigma-delta to near 250MHz
@@ -429,15 +429,15 @@ int omap3_noncore_dpll_enable(struct clk_hw *hw)if (r) {WARN (1 ,"%s: could not enable %s's clockdomain %s: %d\n" , - __func__,__clk_get_name (hw->clk), + __func__,clk_hw_get_name (hw), clk->clkdm_name, r);return r; } } - parent =__clk_get_hw (__clk_get_parent (hw->clk)); + parent =clk_hw_get_parent (hw); -if (__clk_get_rate (hw->clk) ==__clk_get_rate (dd->clk_bypass)) { +if (clk_hw_get_rate (hw) ==clk_get_rate (dd->clk_bypass)) {WARN_ON (parent !=__clk_get_hw (dd->clk_bypass)); r =_omap3_noncore_dpll_bypass (clk); }else {
@@ -489,7 +489,7 @@ int omap3_noncore_dpll_determine_rate(struct clk_hw *hw,if (!dd)return -EINVAL ; -if (__clk_get_rate (dd->clk_bypass) == req->rate && +if (clk_get_rate (dd->clk_bypass) == req->rate && (dd->modes & (1 <<DPLL_LOW_POWER_BYPASS ))) { req->best_parent_hw =__clk_get_hw (dd->clk_bypass); }else {
@@ -553,8 +553,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,if (!dd)return -EINVAL ; -if (__clk_get_hw (__clk_get_parent (hw->clk)) != -__clk_get_hw (dd->clk_ref)) +if (clk_hw_get_parent (hw) !=__clk_get_hw (dd->clk_ref))return -EINVAL ;if (dd->last_rounded_rate ==0 )
@@ -567,7 +566,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, }pr_debug ("%s: %s: set rate: locking rate to %lu.\n" , __func__, -__clk_get_name (hw->clk), rate); +clk_hw_get_name (hw), rate); ret =omap3_noncore_dpll_program (clk, freqsel);
@@ -704,13 +703,11 @@ static void omap3_dpll_deny_idle(struct clk_hw_omap *clk)static struct clk_hw_omap *omap3_find_clkoutx2_dpll (struct clk_hw *hw) {struct clk_hw_omap *pclk =NULL ; -struct clk *parent;/* Walk up the parents of clk, looking for a DPLL */ do { do { - parent = __clk_get_parent(hw->clk); - hw = __clk_get_hw(parent); + hw = clk_hw_get_parent(hw); } while (hw && (clk_hw_get_flags(hw) & CLK_IS_BASIC)); if (!hw) break;
drivers/clk/ti/dpll44xx.c +2 -2
@@ -94,7 +94,7 @@ static void omap4_dpll_lpmode_recalc(struct dpll_data *dd) {long fint, fout; - fint =__clk_get_rate (dd->clk_ref) / (dd->last_rounded_n +1 ); + fint =clk_get_rate (dd->clk_ref) / (dd->last_rounded_n +1 ); fout = fint * dd->last_rounded_m;if ((fint <OMAP4_DPLL_LP_FINT_MAX ) && (fout <OMAP4_DPLL_LP_FOUT_MAX ))
@@ -212,7 +212,7 @@ int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,if (!dd)return -EINVAL ; -if (__clk_get_rate (dd->clk_bypass) == req->rate && +if (clk_get_rate (dd->clk_bypass) == req->rate && (dd->modes & (1 <<DPLL_LOW_POWER_BYPASS ))) { req->best_parent_hw =__clk_get_hw (dd->clk_bypass); }else {
drivers/clk/ti/gate.c +3 -3
@@ -62,7 +62,7 @@ static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = {* (Any other value different from the Read value) to the * corresponding CM_CLKSEL register will refresh the dividers. */ -static int omap36xx_gate_clk_enable_with_hsdiv_restore (struct clk_hw *clk) +static int omap36xx_gate_clk_enable_with_hsdiv_restore (struct clk_hw *hw) {struct clk_divider *parent;struct clk_hw *parent_hw;
@@ -70,10 +70,10 @@ static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk)int ret;/* Clear PWRDN bit of HSDIVIDER */ - ret =omap2_dflt_clk_enable (clk); + ret =omap2_dflt_clk_enable (hw);/* Parent is the x2 node, get parent of parent for the m2 div */ - parent_hw =__clk_get_hw (__clk_get_parent (__clk_get_parent (clk->clk))); + parent_hw =clk_hw_get_parent (clk_hw_get_parent (hw)); parent =to_clk_divider (parent_hw);/* Restore the dividers */
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH 23/26] clk: tegra: Convert to clk_hw based provider APIs
Quoted 3 lines · Stephen Boyd
We're removing struct clk from the clk provider API, so switch this code to using the
clk_hwbased provider APIs.
Subject should be clk: ti: ...
Other than that, seems ok to me. Also, gave clk-next + this set a quick testing on the boards accessible to me, and seems to work fine.
So, once the subject is fixed, for TI relevant parts for patches 2, 5, 7, 8, 23:
-Tero
Quoted 314 lines
Cc Tero Kristo <[email protected]>Signed-off-by Stephen Boyd <[email protected]>--- drivers/clk/ti/autoidle.c | 8 ++++---- drivers/clk/ti/clkt_dpll.c | 11 ++++++----- drivers/clk/ti/clock.h | 2 +- drivers/clk/ti/divider.c | 6 +++--- drivers/clk/ti/dpll3xxx.c | 31 ++++++++++++++----------------- drivers/clk/ti/dpll44xx.c | 4 ++-- drivers/clk/ti/gate.c | 6 +++--- 7 files changed, 33 insertions(+), 35 deletions(-)drivers/clk/ti/autoidle.c +4
-4@@ -169,21 +169,21 @@ int __init of_ti_clk_autoidle_setup(struct device_node *node)/** * omap2_init_clk_hw_omap_clocks - initialize an OMAP clock -* @clk: struct clk * to initialize +* @hw: struct clk_hw * to initialize * * Add an OMAP clock @clk to the internal list of OMAP clocks. Used * temporarily for autoidle handling, until this support can be * integrated into the common clock framework code in some way. No * return value. */ -void omap2_init_clk_hw_omap_clocks (struct clk *clk) +void omap2_init_clk_hw_omap_clocks (struct clk_hw *hw) {struct clk_hw_omap *c; -if (__clk_get_flags (clk) &CLK_IS_BASIC ) +if (clk_hw_get_flags (hw) &CLK_IS_BASIC )return ; - c =to_clk_hw_omap (__clk_get_hw (clk)); + c =to_clk_hw_omap (hw);list_add (&c->node, &clk_hw_omap_clocks); }drivers/clk/ti/clkt_dpll.c +6
-5@@ -16,6 +16,7 @@#include <linux/kernel.h> #include <linux/errno.h> +#include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/io.h> #include <linux/clk/ti.h> @@ -75,7 +76,7 @@ static int _dpll_test_fint(struct clk_hw_omap *clk, unsigned int n) dd = clk->dpll_data;/* DPLL divider must result in a valid jitter correction val */ - fint =__clk_get_rate (__clk_get_parent (clk->hw.clk)) / n; + fint =clk_hw_get_rate (clk_hw_get_parent (&clk->hw)) / n;if (dd->flags &DPLL_J_TYPE ) { fint_min =OMAP3PLUS_DPLL_FINT_JTYPE_MIN ;@@ -253,7 +254,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) v >>=__ffs (dd->enable_mask);if (_omap2_dpll_is_in_bypass (v)) -return __clk_get_rate (dd->clk_bypass); +return clk_get_rate (dd->clk_bypass); v = ti_clk_ll_ops->clk_readl (dd->mult_div1_reg); dpll_mult = v & dd->mult_mask;@@ -261,7 +262,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) dpll_div = v & dd->div1_mask; dpll_div >>=__ffs (dd->div1_mask); - dpll_clk = (long long )__clk_get_rate (dd->clk_ref) * dpll_mult; + dpll_clk = (long long )clk_get_rate (dd->clk_ref) * dpll_mult;do_div (dpll_clk, dpll_div +1 );return dpll_clk;@@ -300,8 +301,8 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, dd = clk->dpll_data; - ref_rate =__clk_get_rate (dd->clk_ref); - clk_name =__clk_get_name (hw->clk); + ref_rate =clk_get_rate (dd->clk_ref); + clk_name =clk_hw_get_name (hw);pr_debug ("clock: %s: starting DPLL round_rate, target rate %lu\n" , clk_name, target_rate);drivers/clk/ti/clock.h +1
-1@@ -204,7 +204,7 @@ int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw, ti_of_clk_init_cb_t func);int ti_clk_add_component (struct device_node *node,struct clk_hw *hw,int type); -void omap2_init_clk_hw_omap_clocks (struct clk *clk); +void omap2_init_clk_hw_omap_clocks (struct clk_hw *hw);int of_ti_clk_autoidle_setup (struct device_node *node);void omap2_clk_enable_init_clocks (const char **clk_names,u8 num_clocks);drivers/clk/ti/divider.c +3
-3@@ -109,7 +109,7 @@ static unsigned long ti_clk_divider_recalc_rate(struct clk_hw *hw,if (!div) {WARN (!(divider->flags &CLK_DIVIDER_ALLOW_ZERO ),"%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n" , -__clk_get_name (hw->clk)); +clk_hw_get_name (hw));return parent_rate; }@@ -181,7 +181,7 @@ static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate, *best_parent_rate = parent_rate_saved;return i; } - parent_rate =__clk_round_rate (__clk_get_parent (hw->clk), + parent_rate =clk_hw_round_rate (clk_hw_get_parent (hw),MULT_ROUND_UP (rate, i)); now =DIV_ROUND_UP (parent_rate, i);if (now <= rate && now > best) {@@ -194,7 +194,7 @@ static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,if (!bestdiv) { bestdiv =_get_maxdiv (divider); *best_parent_rate = -__clk_round_rate (__clk_get_parent (hw->clk),1 ); +clk_hw_round_rate (clk_hw_get_parent (hw),1 ); }return bestdiv;drivers/clk/ti/dpll3xxx.c +14
-17@@ -69,7 +69,7 @@ static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state)const char *clk_name; dd = clk->dpll_data; - clk_name =__clk_get_name (clk->hw.clk); + clk_name =clk_hw_get_name (&clk->hw); state <<=__ffs (dd->idlest_mask);@@ -98,7 +98,7 @@ static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n)unsigned long fint;u16 f =0 ; - fint =__clk_get_rate (clk->dpll_data->clk_ref) / n; + fint =clk_get_rate (clk->dpll_data->clk_ref) / n;pr_debug ("clock: fint is %lu\n" , fint);@@ -145,7 +145,7 @@ static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk)u8 state =1 ;int r =0 ; -pr_debug ("clock: locking DPLL %s\n" ,__clk_get_name (clk->hw.clk)); +pr_debug ("clock: locking DPLL %s\n" ,clk_hw_get_name (&clk->hw)); dd = clk->dpll_data; state <<=__ffs (dd->idlest_mask);@@ -193,7 +193,7 @@ static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *clk)return -EINVAL ;pr_debug ("clock: configuring DPLL %s for low-power bypass\n" , -__clk_get_name (clk->hw.clk)); +clk_hw_get_name (&clk->hw)); ai =omap3_dpll_autoidle_read (clk);@@ -223,7 +223,7 @@ static int _omap3_noncore_dpll_stop(struct clk_hw_omap *clk)if (!(clk->dpll_data->modes & (1 <<DPLL_LOW_POWER_STOP )))return -EINVAL ; -pr_debug ("clock: stopping DPLL %s\n" ,__clk_get_name (clk->hw.clk)); +pr_debug ("clock: stopping DPLL %s\n" ,clk_hw_get_name (&clk->hw)); ai =omap3_dpll_autoidle_read (clk);@@ -251,7 +251,7 @@ static void _lookup_dco(struct clk_hw_omap *clk, u8 *dco, u16 m, u8 n) {unsigned long fint, clkinp;/* watch out for overflow */ - clkinp =__clk_get_rate (__clk_get_parent (clk->hw.clk)); + clkinp =clk_hw_get_rate (clk_hw_get_parent (&clk->hw)); fint = (clkinp / n) * m;if (fint <1000000000 )@@ -277,7 +277,7 @@ static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n)unsigned long clkinp, sd;/* watch out for overflow */ int mod1, mod2; - clkinp =__clk_get_rate (__clk_get_parent (clk->hw.clk)); + clkinp =clk_hw_get_rate (clk_hw_get_parent (&clk->hw));/* * target sigma-delta to near 250MHz @@ -429,15 +429,15 @@ int omap3_noncore_dpll_enable(struct clk_hw *hw)if (r) {WARN (1 ,"%s: could not enable %s's clockdomain %s: %d\n" , - __func__,__clk_get_name (hw->clk), + __func__,clk_hw_get_name (hw), clk->clkdm_name, r);return r; } } - parent =__clk_get_hw (__clk_get_parent (hw->clk)); + parent =clk_hw_get_parent (hw); -if (__clk_get_rate (hw->clk) ==__clk_get_rate (dd->clk_bypass)) { +if (clk_hw_get_rate (hw) ==clk_get_rate (dd->clk_bypass)) {WARN_ON (parent !=__clk_get_hw (dd->clk_bypass)); r =_omap3_noncore_dpll_bypass (clk); }else {@@ -489,7 +489,7 @@ int omap3_noncore_dpll_determine_rate(struct clk_hw *hw,if (!dd)return -EINVAL ; -if (__clk_get_rate (dd->clk_bypass) == req->rate && +if (clk_get_rate (dd->clk_bypass) == req->rate && (dd->modes & (1 <<DPLL_LOW_POWER_BYPASS ))) { req->best_parent_hw =__clk_get_hw (dd->clk_bypass); }else {@@ -553,8 +553,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,if (!dd)return -EINVAL ; -if (__clk_get_hw (__clk_get_parent (hw->clk)) != -__clk_get_hw (dd->clk_ref)) +if (clk_hw_get_parent (hw) !=__clk_get_hw (dd->clk_ref))return -EINVAL ;if (dd->last_rounded_rate ==0 )@@ -567,7 +566,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, }pr_debug ("%s: %s: set rate: locking rate to %lu.\n" , __func__, -__clk_get_name (hw->clk), rate); +clk_hw_get_name (hw), rate); ret =omap3_noncore_dpll_program (clk, freqsel);@@ -704,13 +703,11 @@ static void omap3_dpll_deny_idle(struct clk_hw_omap *clk)static struct clk_hw_omap *omap3_find_clkoutx2_dpll (struct clk_hw *hw) {struct clk_hw_omap *pclk =NULL ; -struct clk *parent;/* Walk up the parents of clk, looking for a DPLL */ do { do { - parent = __clk_get_parent(hw->clk); - hw = __clk_get_hw(parent); + hw = clk_hw_get_parent(hw); } while (hw && (clk_hw_get_flags(hw) & CLK_IS_BASIC)); if (!hw) break;drivers/clk/ti/dpll44xx.c +2
-2@@ -94,7 +94,7 @@ static void omap4_dpll_lpmode_recalc(struct dpll_data *dd) {long fint, fout; - fint =__clk_get_rate (dd->clk_ref) / (dd->last_rounded_n +1 ); + fint =clk_get_rate (dd->clk_ref) / (dd->last_rounded_n +1 ); fout = fint * dd->last_rounded_m;if ((fint <OMAP4_DPLL_LP_FINT_MAX ) && (fout <OMAP4_DPLL_LP_FOUT_MAX ))@@ -212,7 +212,7 @@ int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,if (!dd)return -EINVAL ; -if (__clk_get_rate (dd->clk_bypass) == req->rate && +if (clk_get_rate (dd->clk_bypass) == req->rate && (dd->modes & (1 <<DPLL_LOW_POWER_BYPASS ))) { req->best_parent_hw =__clk_get_hw (dd->clk_bypass); }else {drivers/clk/ti/gate.c +3
-3@@ -62,7 +62,7 @@ static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = {* (Any other value different from the Read value) to the * corresponding CM_CLKSEL register will refresh the dividers. */ -static int omap36xx_gate_clk_enable_with_hsdiv_restore (struct clk_hw *clk) +static int omap36xx_gate_clk_enable_with_hsdiv_restore (struct clk_hw *hw) {struct clk_divider *parent;struct clk_hw *parent_hw;@@ -70,10 +70,10 @@ static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk)int ret;/* Clear PWRDN bit of HSDIVIDER */ - ret =omap2_dflt_clk_enable (clk); + ret =omap2_dflt_clk_enable (hw);/* Parent is the x2 node, get parent of parent for the m2 div */ - parent_hw =__clk_get_hw (__clk_get_parent (__clk_get_parent (clk->clk))); + parent_hw =clk_hw_get_parent (clk_hw_get_parent (hw)); parent =to_clk_divider (parent_hw);/* Restore the dividers */
Re: [PATCH 23/26] clk: tegra: Convert to clk_hw based provider APIs
Quoted 7 lines · Tero Kristo
Quoted 3 lines · Stephen Boyd
We're removing struct clk from the clk provider API, so switch this code to using the
clk_hwbased provider APIs.Subject should be clk: ti: ...
Quoted 9 lines
Other than that, seems ok to me. Also, gave clk-next + this set a quick testing on the boards accessible to me, and seems to work fine.
So, once the subject is fixed, for TI relevant parts for patches 2, 5, 7, 8, 23:
Acked-by Tero Kristo <[email protected]>
Thanks. I fixed the subject.
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH 24/26 clk: versatile: Convert to clk_hw based provider APIs
In reply to Stephen BoydWe're removing struct clk from the clk provider API, so switch this code to using the clk_hw based provider APIs.
--- drivers/clk/versatile/clk-sp810.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/clk/versatile/clk-sp810.c +1 -1
@@ -80,7 +80,7 @@ static int clk_sp810_timerclken_prepare(struct clk_hw *hw) {struct clk_sp810_timerclken *timerclken =to_clk_sp810_timerclken (hw);struct clk_sp810 *sp810 = timerclken->sp810; -struct clk *old_parent =__clk_get_parent (hw->clk); +struct clk_hw *old_parent =clk_hw_get_parent (hw);struct clk *new_parent;if (!sp810->refclk)
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH 24/26] clk: versatile: Convert to clk_hw based provider APIs
Quoted 15 lines · Stephen Boyd
We're removing struct clk from the clk provider API, so switch this code to using the
clk_hwbased provider APIs.Cc Pawel Moll <[email protected]>Cc Linus Walleij <[email protected]>Signed-off-by Stephen Boyd <[email protected]>--- drivers/clk/versatile/clk-sp810.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)drivers/clk/versatile/clk-sp810.c +0
-0
drivers/clk/versatile/clk-sp810.c static int clk_sp810_timerclken_prepare(struct clk_hw *hw) · line 86
Quoted 8 lines
drivers/clk/versatile/clk-sp810.c +1
-1@@ -80,7 +80,7 @@ static int clk_sp810_timerclken_prepare(struct clk_hw *hw) {struct clk_sp810_timerclken *timerclken =to_clk_sp810_timerclken (hw);struct clk_sp810 *sp810 = timerclken->sp810; -struct clk *old_parent =__clk_get_parent (hw->clk); +struct clk_hw *old_parent =clk_hw_get_parent (hw);struct clk *new_parent;if (!sp810->refclk)
(disclaimer: not tested ;-)
Thanks!
Pawel
Re: [PATCH 24/26] clk: versatile: Convert to clk_hw based provider APIs
Quoted 23 lines · Pawel Moll
Quoted 22 lines · Stephen Boyd
We're removing struct clk from the clk provider API, so switch this code to using the
clk_hwbased provider APIs.Cc Pawel Moll <[email protected]>Cc Linus Walleij <[email protected]>Signed-off-by Stephen Boyd <[email protected]>--- drivers/clk/versatile/clk-sp810.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)drivers/clk/versatile/clk-sp810.c +1
-1@@ -80,7 +80,7 @@ static int clk_sp810_timerclken_prepare(struct clk_hw *hw) {struct clk_sp810_timerclken *timerclken =to_clk_sp810_timerclken (hw);struct clk_sp810 *sp810 = timerclken->sp810; -struct clk *old_parent =__clk_get_parent (hw->clk); +struct clk_hw *old_parent =clk_hw_get_parent (hw);struct clk *new_parent;
Quoted 5 lines
drivers/clk/versatile/clk-sp810.c static int clk_sp810_timerclken_prepare(struct clk_hw *hw) · line 86
Quoted 1 line
drivers/clk/versatile/clk-sp810.c +0
-0if (!sp810->refclk)Acked-by Pawel Moll <[email protected]>(disclaimer: not tested ;-)
Oh yeah this patch is broken... better patch coming soon that will force usage of assigned-parents in DT.
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
cover Move clk-sp810 to assigned clock parents
This patch set converts this code to use the assigned-clock-parents property instead of doing some interesting stuff in the .prepare op. I can route the dts patches through arm-soc but I'd like to take the clk patch through clk tree because it removes some usage of the struct clk based provider APIs that we're trying to get rid of. Also, this is completely untested, so testing would be appreciated. Can this be tested with qemu? I haven't tried but I was thinking that might be an option.
Stephen Boyd (3):
clk: versatile: Switch to assigned clock parents
ARM: dts: vexpress: Use assigned-clock-parents for sp810
ARM64: dts: vexpress: Use assigned-clock-parents for sp810
arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 2 + arch/arm/boot/dts/vexpress-v2m.dtsi | 2 + arch/arm64/boot/dts/arm/juno-motherboard.dtsi | 2 + arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi | 2 + drivers/clk/versatile/clk-sp810.c | 76 +++++------------------- 5 files changed, 23 insertions(+), 61 deletions(-)
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH 1/3 clk: versatile: Switch to assigned clock parents
We're removing struct clk from the clk provider API. This code is calling the consumer APIs to change the parent to a 1 MHz fixed rate clock for each of the clocks that the driver provides. Move to using the assigned-clock-parents DT property for this instead. Because this is an ABI break, detect if the property is missing and fall back to setting the parent explicitly before the clocks are registered.
--- drivers/clk/versatile/clk-sp810.c | 76 ++++++++------------------------------- 1 file changed, 15 insertions(+), 61 deletions(-)
drivers/clk/versatile/clk-sp810.c +15 -61
@@ -33,12 +33,9 @@ struct clk_sp810_timerclken {struct clk_sp810 {struct device_node *node; -int refclk_index, timclk_index;void __iomem *base;spinlock_t lock;struct clk_sp810_timerclken timerclken[4 ]; -struct clk *refclk; -struct clk *timclk; };static u8 clk_sp810_timerclken_get_parent (struct clk_hw *hw)
@@ -71,55 +68,7 @@ static int clk_sp810_timerclken_set_parent(struct clk_hw *hw, u8 index)return 0 ; } -/* -* FIXME - setting the parent every time .prepare is invoked is inefficient. -* This is better handled by a dedicated clock tree configuration mechanism at -* init-time. Revisit this later when such a mechanism exists -*/ -static int clk_sp810_timerclken_prepare (struct clk_hw *hw) -{ -struct clk_sp810_timerclken *timerclken =to_clk_sp810_timerclken (hw); -struct clk_sp810 *sp810 = timerclken->sp810; -struct clk *old_parent =__clk_get_parent (hw->clk); -struct clk *new_parent; - -if (!sp810->refclk) - sp810->refclk =of_clk_get (sp810->node, sp810->refclk_index); - -if (!sp810->timclk) - sp810->timclk =of_clk_get (sp810->node, sp810->timclk_index); - -if (WARN_ON (IS_ERR (sp810->refclk) ||IS_ERR (sp810->timclk))) -return -ENOENT ; - -/* Select fastest parent */ -if (clk_get_rate (sp810->refclk) >clk_get_rate (sp810->timclk)) - new_parent = sp810->refclk; -else - new_parent = sp810->timclk; - -/* Switch the parent if necessary */ -if (old_parent != new_parent) { -clk_prepare (new_parent); -clk_set_parent (hw->clk, new_parent); -clk_unprepare (old_parent); - } - -return 0 ; -} - -static void clk_sp810_timerclken_unprepare (struct clk_hw *hw) -{ -struct clk_sp810_timerclken *timerclken =to_clk_sp810_timerclken (hw); -struct clk_sp810 *sp810 = timerclken->sp810; - -clk_put (sp810->timclk); -clk_put (sp810->refclk); -} -static const struct clk_ops clk_sp810_timerclken_ops = { - .prepare = clk_sp810_timerclken_prepare, - .unprepare = clk_sp810_timerclken_unprepare, .get_parent = clk_sp810_timerclken_get_parent, .set_parent = clk_sp810_timerclken_set_parent, };
@@ -140,24 +89,18 @@ static void __init clk_sp810_of_setup(struct device_node *node) {struct clk_sp810 *sp810 =kzalloc (sizeof (*sp810),GFP_KERNEL );const char *parent_names[2 ]; +int num =ARRAY_SIZE (parent_names);char name[12 ];struct clk_init_data init;int i; +bool deprecated;if (!sp810) {pr_err ("Failed to allocate memory for SP810!\n" );return ; } - sp810->refclk_index =of_property_match_string (node,"clock-names" , -"refclk" ); - parent_names[0 ] =of_clk_get_parent_name (node, sp810->refclk_index); - - sp810->timclk_index =of_property_match_string (node,"clock-names" , -"timclk" ); - parent_names[1 ] =of_clk_get_parent_name (node, sp810->timclk_index); - -if (!parent_names[0 ] || !parent_names[1 ]) { +if (of_clk_parent_fill (node, parent_names, num) != num) {pr_warn ("Failed to obtain parent clocks for SP810!\n" );return ; }
@@ -170,7 +113,9 @@ static void __init clk_sp810_of_setup(struct device_node *node) init.ops = &clk_sp810_timerclken_ops; init.flags =CLK_IS_BASIC ; init.parent_names = parent_names; - init.num_parents =ARRAY_SIZE (parent_names); + init.num_parents = num; + + deprecated = !of_find_property (node,"assigned-clock-parents" ,NULL );for (i =0 ; i <ARRAY_SIZE (sp810->timerclken); i++) {snprintf (name,ARRAY_SIZE (name),"timerclken%d" , i);
@@ -179,6 +124,15 @@ static void __init clk_sp810_of_setup(struct device_node *node) sp810->timerclken[i].channel = i; sp810->timerclken[i].hw.init = &init; +/* +* If DT isn't setting the parent, force it to be +* the 1 MHz clock without going through the framework. +* We do this before clk_register() so that it can determine +* the parent and setup the tree properly. +*/ +if (deprecated) + init.ops->set_parent (&sp810->timerclken[i].hw,1 ); + sp810->timerclken[i].clk =clk_register (NULL , &sp810->timerclken[i].hw);WARN_ON (IS_ERR (sp810->timerclken[i].clk));
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH 1/3] clk: versatile: Switch to assigned clock parents
Quoted 6 lines · Stephen Boyd
drivers/clk/versatile/clk-sp810.c +2
-0@@ -179,6 +124,15 @@ static void __init clk_sp810_of_setup(struct device_node *node) sp810->timerclken[i].channel = i; sp810->timerclken[i].hw.init = &init; +/* +* If DT isn't setting the parent, force it to be
drivers/clk/versatile/clk-sp810.c static void __init clk_sp810_of_setup(struct device_node *node) · line 138
Quoted 10 lines
drivers/clk/versatile/clk-sp810.c +7
-0+* the 1 MHz clock without going through the framework. +* We do this before clk_register() so that it can determine +* the parent and setup the tree properly. +*/ +if (deprecated) + init.ops->set_parent (&sp810->timerclken[i].hw,1 ); + sp810->timerclken[i].clk =clk_register (NULL , &sp810->timerclken[i].hw);WARN_ON (IS_ERR (sp810->timerclken[i].clk));
So that's one thing I've got a (small) problem here...
The above change assumes that SP810 always have 32kHz clock on input 0 and 1MHz clock on input 1. Yes, this is how it made on VExpress, but it doesn't have to be the case. The magic picking up the faster clock was added to handle all possible cases.
The bottom line is: if all we care is VExpress than it works, but it's still a hack. Personally I don't like it, however I won't nak the patch because of this.
Pawel
Re: [PATCH 1/3] clk: versatile: Switch to assigned clock parents
Quoted 19 lines · Pawel Moll
Quoted 6 lines · Stephen Boyd
drivers/clk/versatile/clk-sp810.c +2
-0@@ -179,6 +124,15 @@ static void __init clk_sp810_of_setup(struct device_node *node) sp810->timerclken[i].channel = i; sp810->timerclken[i].hw.init = &init; +/* +* If DT isn't setting the parent, force it to be drivers/clk/versatile/clk-sp810.c static void __init clk_sp810_of_setup(struct device_node *node) · line 138
Quoted 10 lines
drivers/clk/versatile/clk-sp810.c +7
-0+* the 1 MHz clock without going through the framework. +* We do this before clk_register() so that it can determine +* the parent and setup the tree properly. +*/ +if (deprecated) + init.ops->set_parent (&sp810->timerclken[i].hw,1 ); + sp810->timerclken[i].clk =clk_register (NULL , &sp810->timerclken[i].hw);WARN_ON (IS_ERR (sp810->timerclken[i].clk));So that's one thing I've got a (small) problem here...
Quoted 9 lines
The above change assumes that SP810 always have 32kHz clock on input 0 and 1MHz clock on input 1. Yes, this is how it made on VExpress, but it doesn't have to be the case. The magic picking up the faster clock was added to handle all possible cases.
The bottom line is: if all we care is VExpress than it works, but it's still a hack. Personally I don't like it, however I won't nak the patch because of this.
All current dts files in the kernel tree have 1MHz on input 1, so we make this change here to set the parent to input 1 if there isn't an assigned-clock-parents property. Presumably new dts files should have the new property so that things work properly. I tried to find the binding document, but it doesn't look to exist, so I didn't have anything to update.
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH 1/3] clk: versatile: Switch to assigned clock parents
Quoted 25 lines · Stephen Boyd
Quoted 24 lines · Pawel Moll
Quoted 6 lines · Stephen Boyd
drivers/clk/versatile/clk-sp810.c +2
-0@@ -179,6 +124,15 @@ static void __init clk_sp810_of_setup(struct device_node *node) sp810->timerclken[i].channel = i; sp810->timerclken[i].hw.init = &init; +/* +* If DT isn't setting the parent, force it to be drivers/clk/versatile/clk-sp810.c static void __init clk_sp810_of_setup(struct device_node *node) · line 138
Quoted 10 lines
drivers/clk/versatile/clk-sp810.c +7
-0+* the 1 MHz clock without going through the framework. +* We do this before clk_register() so that it can determine +* the parent and setup the tree properly. +*/ +if (deprecated) + init.ops->set_parent (&sp810->timerclken[i].hw,1 ); + sp810->timerclken[i].clk =clk_register (NULL , &sp810->timerclken[i].hw);WARN_ON (IS_ERR (sp810->timerclken[i].clk));So that's one thing I've got a (small) problem here...
The above change assumes that SP810 always have 32kHz clock on input 0 and 1MHz clock on input 1. Yes, this is how it made on VExpress, but it doesn't have to be the case. The magic picking up the faster clock was added to handle all possible cases.
Quoted 7 lines
Quoted 3 lines
The bottom line is: if all we care is VExpress than it works, but it's still a hack. Personally I don't like it, however I won't nak the patch because of this.
All current dts files in the kernel tree have 1MHz on input 1, so we make this change here to set the parent to input 1 if there isn't an assigned-clock-parents property.
That's what I said - all VE platforms known to me will work, because they all have the clocks wired up the same way. And I still don't like code in a "generic SP810 driver" assuming this. Call me what you want ;-)
Quoted 2 lines
Presumably new dts files should have
the new property so that things work properly.
Sure, no argument here.
Quoted 3 lines
I tried to find the
binding document, but it doesn't look to exist, so I didn't have anything to update.
Right, that's probably my fault. The sp810 nodes appeared in the VE trees very early (in terms of the "DT era"), when we weren't so strict about documentation. So far, it would be fairly simple, something like the text below - feel free to take it, mend it, extend it with your changes and include in the series:
Thanks!
Pawel
8<-------------------------
SP810 System Controller
-----------------------
Required properties:
- compatible: standard compatible string for a Primecell peripheral,
see Documentation/devicetree/bindings/arm/primecell.txt for more details should be: "arm,sp810", "arm,primecell"
- reg: standard registers property, physical address and size
of the control registers
- clock-names: from the common clock bindings, for more details see
Documentation/devicetree/bindings/clock/clock-bindings.txt; should be: "refclk", "timclk", "apb_pclk"
- clocks: from the common clock bindings, phandle and clock
specifier pairs for the entries of clock-names property
- #clock-cells: from the common clock bindings;
should be: <1>
- clock-output-names: from the common clock bindings;
should be: "timerclken0", "timerclken1", "timerclken2", "timerclken3"
Example:
sysctl at 020000 {
compatible = "arm,sp810", "arm,primecell";
reg = <0x020000 0x1000>;
clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
clock-names = "refclk", "timclk", "apb_pclk";
#clock-cells = <1>;
clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
};Re: [PATCH 1/3] clk: versatile: Switch to assigned clock parents
Quoted 8 lines · Pawel Moll
Right, that's probably my fault. The sp810 nodes appeared in the VE trees very early (in terms of the "DT era"), when we weren't so strict about documentation. So far, it would be fairly simple, something like the text below - feel free to take it, mend it, extend it with your changes and include in the series:
Thanks!
Great! Can you please provide your signed-off-by? I can make it up into a patch with some commit text that either you or I provide and throw it into the series.
Signature · 2 lines
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Re: [PATCH 1/3] clk: versatile: Switch to assigned clock parents
Quoted 11 lines · Stephen Boyd
Quoted 8 lines · Pawel Moll
Right, that's probably my fault. The sp810 nodes appeared in the VE trees very early (in terms of the "DT era"), when we weren't so strict about documentation. So far, it would be fairly simple, something like the text below - feel free to take it, mend it, extend it with your changes and include in the series:
Thanks!
Great! Can you please provide your signed-off-by?
Sure.
8<--------------------------------------------------------
Quoted 1 line
From
cddb00e4c8b6b57e82008fa23a7359560e5c997cMon Sep 17 00:00:00 2001
From: Pawel Moll <[email protected]>
Date: Thu, 6 Aug 2015 16:04:10 +0100
Subject: [PATCH] clk: versatile: Add SP810 device tree bindings document
--- Documentation/devicetree/bindings/arm/sp810.txt | 35 +++++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/sp810.txt
Documentation/devicetree/bindings/arm/sp810.txt new file +35 -0
@@ -0,0 +1,35 @@ +SP810 System Controller +----------------------- + +Required properties: + +- compatible: standard compatible string for a Primecell peripheral, + see Documentation/devicetree/bindings/arm/primecell.txt + for more details + should be: "arm,sp810", "arm,primecell" + +- reg: standard registers property, physical address and size + of the control registers + +- clock-names: from the common clock bindings, for more details see + Documentation/devicetree/bindings/clock/clock-bindings.txt; + should be: "refclk", "timclk", "apb_pclk" + +- clocks: from the common clock bindings, phandle and clock + specifier pairs for the entries of clock-names property + +- #clock-cells: from the common clock bindings; + should be: <1> + +- clock-output-names: from the common clock bindings; + should be: "timerclken0", "timerclken1", "timerclken2", "timerclken3" + +Example: + sysctl at 020000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x020000 0x1000>; + clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>; + clock-names = "refclk", "timclk", "apb_pclk"; + #clock-cells = <1>; + clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; + };
Signature · 1 line
2.1.4
Re: [PATCH 1/3] clk: versatile: Switch to assigned clock parents
Quoted 9 lines · Pawel Moll
Quoted 8 lines · Stephen Boyd
Quoted 7 lines · Pawel Moll
Right, that's probably my fault. The sp810 nodes appeared in the VE trees very early (in terms of the "DT era"), when we weren't so strict about documentation. So far, it would be fairly simple, something like the text below - feel free to take it, mend it, extend it with your changes and include in the series:
Quoted 5 lines
Quoted 3 lines
Quoted 1 line
Thanks!
Great! Can you please provide your signed-off-by?
Sure.
Thanks! I've put that patch before my series and squashed this into patch 1/3.
----8<----
Documentation/devicetree/bindings/arm/sp810.txt +12 -1
@@ -24,12 +24,23 @@ Required properties: - clock-output-names: from the common clock bindings; should be: "timerclken0", "timerclken1", "timerclken2", "timerclken3" +- assigned-clocks: from the common clock binding; + should be: clock specifier for each output clock of this + provider node + +- assigned-clock-parents: from the common clock binding; + should be: clock specifier of input clock listed in clocks + property with the highest frequency + Example: - sysctl at 020000 { + v2m_sysctl: sysctl@020000 { compatible = "arm,sp810", "arm,primecell"; reg = <0x020000 0x1000>; clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>; clock-names = "refclk", "timclk", "apb_pclk"; #clock-cells = <1>; clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; + assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; + assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; + };
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PATCH 2/3 ARM: dts: vexpress: Use assigned-clock-parents for sp810
In reply to Stephen BoydThe sp810 clk driver is calling the clk consumer APIs from clk_prepare ops to change the parent to a 1 MHz fixed rate clock for each of the clocks that the driver provides. Use assigned-clock-parents for this instead of doing it in the driver to avoid using the consumer API in provider code. This also allows us to remove the usage of clk provider APIs that take a struct clk as an argument from the sp810 driver.
--- arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 2 ++ arch/arm/boot/dts/vexpress-v2m.dtsi | 2 ++ 2 files changed, 4 insertions(+)
arch/arm/boot/dts/vexpress-v2m-rs1.dtsi +2 -0
@@ -101,6 +101,8 @@ clock-names = "refclk", "timclk", "apb_pclk"; #clock-cells = <1>; clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; + assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; + assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; }; /* PCI-E I2C bus */
arch/arm/boot/dts/vexpress-v2m.dtsi +2 -0
@@ -100,6 +100,8 @@ clock-names = "refclk", "timclk", "apb_pclk"; #clock-cells = <1>; clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; + assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; + assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; }; /* PCI-E I2C bus */
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PATCH 3/3 ARM64: dts: vexpress: Use assigned-clock-parents for sp810
In reply to Stephen BoydThe sp810 clk driver is calling the clk consumer APIs from clk_prepare ops to change the parent to a 1 MHz fixed rate clock for each of the clocks that the driver provides. Use assigned-clock-parents for this instead of doing it in the driver to avoid using the consumer API in provider code. This also allows us to remove the usage of clk provider APIs that take a struct clk as an argument from the sp810 driver.
--- arch/arm64/boot/dts/arm/juno-motherboard.dtsi | 2 ++ arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi | 2 ++ 2 files changed, 4 insertions(+)
arch/arm64/boot/dts/arm/juno-motherboard.dtsi +2 -0
@@ -136,6 +136,8 @@ clock-names = "refclk", "timclk", "apb_pclk"; #clock-cells = <1>; clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; + assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; + assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; }; apbregs at 010000 {
arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi +2 -0
@@ -74,6 +74,8 @@ clock-names = "refclk", "timclk", "apb_pclk"; #clock-cells = <1>; clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; + assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; + assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; }; aaci at 040000 {
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Re: [PATCH 0/3] Move clk-sp810 to assigned clock parents
In reply to Stephen BoydHi Stephen,
Quoted 9 lines · Stephen Boyd
This patch set converts this code to use the assigned-clock-parents property instead of doing some interesting stuff in the .prepare op. I can route the dts patches through arm-soc but I'd like to take the clk patch through clk tree because it removes some usage of the struct clk based provider APIs that we're trying to get rid of. Also, this is completely untested, so testing would be appreciated. Can this be tested with qemu? I haven't tried but I was thinking that might be an option.
Quoted 4 lines
Cc Pawel Moll <[email protected]>Cc Linus Walleij <[email protected]>Cc Sudeep Holla <[email protected]>
(Tested the series on Juno R0 and Vexpress TC2 platform)
Regards,
Sudeep
PATCH 25/26 drm/msm/dsi: Convert to clk_hw based provider APIs
In reply to Stephen BoydWe're removing struct clk from the clk provider API, so switch this code to using the clk_hw based provider APIs.
--- drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c +2 -2
@@ -455,7 +455,7 @@ static void dsi_pll_28nm_save_state(struct msm_dsi_pll *pll) cached_state->postdiv1 =pll_read (base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG); cached_state->byte_mux =pll_read (base + REG_DSI_28nm_PHY_PLL_VREG_CFG); - cached_state->vco_rate =__clk_get_rate (pll->clk_hw.clk); + cached_state->vco_rate =clk_hw_get_rate (&pll->clk_hw); }static int dsi_pll_28nm_restore_state (struct msm_dsi_pll *pll)
@@ -466,7 +466,7 @@ static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll)int ret;if ((cached_state->vco_rate !=0 ) && - (cached_state->vco_rate ==__clk_get_rate (pll->clk_hw.clk))) { + (cached_state->vco_rate ==clk_hw_get_rate (&pll->clk_hw))) { ret =dsi_pll_28nm_clk_set_rate (&pll->clk_hw, cached_state->vco_rate,0 );if (ret) {
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PATCH 26/26 clk: Remove unused provider APIs
In reply to Stephen BoydRemove these APIs now that we've converted the users of these APIs to their replacement clk_hw based versions.
--- drivers/clk/clk.c | 86 +++++++++----------------------------------- include/linux/clk-provider.h | 5 --- 2 files changed, 16 insertions(+), 75 deletions(-)
drivers/clk/clk.c +16 -70
@@ -295,16 +295,6 @@ unsigned int clk_hw_get_num_parents(struct clk_hw *hw) }EXPORT_SYMBOL_GPL (clk_hw_get_num_parents); -struct clk *__clk_get_parent (struct clk *clk) -{ -if (!clk) -return NULL ; - -/* TODO: Create a per-user clk and change callers to call clk_put */ -return !clk->core->parent ?NULL : clk->core->parent->hw->clk; -} -EXPORT_SYMBOL_GPL (__clk_get_parent); -struct clk_hw *clk_hw_get_parent (struct clk_hw *hw) {return hw->core->parent ? hw->core->parent->hw :NULL ;
@@ -368,19 +358,6 @@ static struct clk_core *clk_core_get_parent_by_index(struct clk_core *core,return core->parents[index]; } -struct clk *clk_get_parent_by_index (struct clk *clk,u8 index) -{ -struct clk_core *parent; - -if (!clk) -return NULL ; - - parent =clk_core_get_parent_by_index (clk->core, index); - -return !parent ?NULL : parent->hw->clk; -} -EXPORT_SYMBOL_GPL (clk_get_parent_by_index); -struct clk_hw *clk_hw_get_parent_by_index (struct clk_hw *hw,unsigned int index) {struct clk_core *parent;
@@ -417,15 +394,6 @@ out:return ret; } -unsigned long __clk_get_rate (struct clk *clk) -{ -if (!clk) -return 0 ; - -return clk_core_get_rate_nolock (clk->core); -} -EXPORT_SYMBOL_GPL (__clk_get_rate); -unsigned long clk_hw_get_rate (struct clk_hw *hw) {return clk_core_get_rate_nolock (hw->core);
@@ -452,14 +420,6 @@ unsigned long clk_hw_get_flags(struct clk_hw *hw) }EXPORT_SYMBOL_GPL (clk_hw_get_flags); -bool __clk_is_prepared (struct clk *clk) -{ -if (!clk) -return false; - -return clk_core_is_prepared (clk->core); -} -bool clk_hw_is_prepared (struct clk_hw *hw) {return clk_core_is_prepared (hw->core);
@@ -873,32 +833,6 @@ int __clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) }EXPORT_SYMBOL_GPL (__clk_determine_rate); -/** -* __clk_round_rate - round the given rate for a clk -* @clk: round the rate of this clock -* @rate: the rate which is to be rounded -* -* Useful for clk_ops such as .set_rate -*/ -unsigned long __clk_round_rate (struct clk *clk,unsigned long rate) -{ -struct clk_rate_request req; -int ret; - -if (!clk) -return 0 ; - -clk_core_get_boundaries (clk->core, &req.min_rate, &req.max_rate); - req.rate = rate; - - ret =clk_core_round_rate_nolock (clk->core, &req); -if (ret) -return 0 ; - -return req.rate; -} -EXPORT_SYMBOL_GPL (__clk_round_rate); -unsigned long clk_hw_round_rate (struct clk_hw *hw,unsigned long rate) {int ret;
@@ -926,16 +860,24 @@ EXPORT_SYMBOL_GPL(clk_hw_round_rate);*/ long clk_round_rate (struct clk *clk,unsigned long rate) { -unsigned long ret; +struct clk_rate_request req; +int ret;if (!clk)return 0 ;clk_prepare_lock (); - ret =__clk_round_rate (clk, rate); + +clk_core_get_boundaries (clk->core, &req.min_rate, &req.max_rate); + req.rate = rate; + + ret =clk_core_round_rate_nolock (clk->core, &req);clk_prepare_unlock (); -return ret; +if (ret) +return ret; + +return req.rate; }EXPORT_SYMBOL_GPL (clk_round_rate);
@@ -1682,8 +1624,12 @@ struct clk *clk_get_parent(struct clk *clk) {struct clk *parent; +if (!clk) +return NULL ; +clk_prepare_lock (); - parent =__clk_get_parent (clk); +/* TODO: Create a per-user clk and change callers to call clk_put */ + parent = !clk->core->parent ?NULL : clk->core->parent->hw->clk;clk_prepare_unlock ();return parent;
include/linux/clk-provider.h +0 -5
@@ -610,17 +610,13 @@ const char *__clk_get_name(struct clk *clk);const char *clk_hw_get_name (struct clk_hw *hw);struct clk_hw *__clk_get_hw (struct clk *clk);unsigned int clk_hw_get_num_parents (struct clk_hw *hw); -struct clk *__clk_get_parent (struct clk *clk);struct clk_hw *clk_hw_get_parent (struct clk_hw *hw); -struct clk *clk_get_parent_by_index (struct clk *clk,u8 index);struct clk_hw *clk_hw_get_parent_by_index (struct clk_hw *hw,unsigned int index);unsigned int __clk_get_enable_count (struct clk *clk); -unsigned long __clk_get_rate (struct clk *clk);unsigned long clk_hw_get_rate (struct clk_hw *hw);unsigned long __clk_get_flags (struct clk *clk);unsigned long clk_hw_get_flags (struct clk_hw *hw); -bool __clk_is_prepared (struct clk *clk);bool clk_hw_is_prepared (struct clk_hw *hw);bool __clk_is_enabled (struct clk *clk);struct clk *__clk_lookup (const char *name);
@@ -642,7 +638,6 @@ static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)/* * FIXME clock api without lock protection */ -unsigned long __clk_round_rate (struct clk *clk,unsigned long rate);unsigned long clk_hw_round_rate (struct clk_hw *hw,unsigned long rate);struct of_device_id ;
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