tegra: pll: fix pllx cpcon in pllinfo table for t20/t30

-----Original Message-----
From: Marcel Ziswiler [mailto:marcel at ziswiler.com]
Sent: Wednesday, August 05, 2015 7:37 AM
To: u-boot at lists.denx.de
Cc: Tom Warren; Tom Warren; Albert Aribaud; Tom Rini; Thierry Reding; Simon Glass; Stephen Warren; Masahiro Yamada; Marcel Ziswiler
Subject: [PATCH] tegra: pll: fix pllx cpcon in pllinfo table for t20/t30

From: Marcel Ziswiler <[email protected]>

Fix CPCON mask and shift of PLLX for T20 as well as T30. While the former's PLLX did not even lock any more resulting is super slow operation the later seemed to still lock OK. Nonetheless I this patch fixes it for both.

Signed-off-by Marcel Ziswiler <[email protected]>

---
Note: This patch requires Tom's two Tegra PLL patches being applied first.

arch/arm/mach-tegra/tegra20/clock.c | 2 +- arch/arm/mach-
tegra/tegra30/clock.c | 2 +-

 2 files changed, 2 insertions(+), 2 deletions(-)

arch/arm/mach- renamed from arch/arm/mach-tegra/tegra20/clock.c +0 -0

tegra/tegra20/clock.c
index df9f412..dea459b 100644

arch/arm/mach-tegra/tegra20/clock.c +0 -0

@@ -379,7 +379,7 @@ struct clk_pll_info
 tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
 	{ .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift =
 20, .p_mask = 0x07,
 	  .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF,

.kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD */
{ .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift
= 20, .p_mask = 0x0F,

arch/arm/mach-tegra/tegra20/clock.c +0 -1

-	  .lock_ena = 18, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 0,

.kvco_shift = 0, .kvco_mask = 0 }, /* PLLX */

arch/arm/mach-tegra/tegra20/clock.c +1 -0

+	  .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF,

.kvco_shift = 0, .kvco_mask = 0 }, /* PLLX */
{ .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift =
0, .p_mask = 0,
.lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3,
.kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */
{ .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift =
20, .p_mask = 0x07, diff --git a/arch/arm/mach-tegra/tegra30/clock.c b/arch/arm/mach-tegra/tegra30/clock.c
index 4267bb2..3ce508b 100644

arch/arm/mach-tegra/tegra30/clock.c +0 -0

@@ -428,7 +428,7 @@ struct clk_pll_info
 tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
 	{ .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift =
 20, .p_mask = 0x07,
 	  .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF,

.kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD */
{ .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift =
20, .p_mask = 0x0F,

arch/arm/mach-tegra/tegra30/clock.c +0 -1

-	  .lock_ena = 18, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 0,

.kvco_shift = 0, .kvco_mask = 0 }, /* PLLX */

arch/arm/mach-tegra/tegra30/clock.c +1 -0

+	  .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF,

.kvco_shift = 0, .kvco_mask = 0 }, /* PLLX */
{ .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift =
0, .p_mask = 0,
.lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3,
.kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */
{ .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift =
20, .p_mask = 0x07,
--
2.4.3

Do you mind if I just roll this into my pllinfo patch when I apply it to u-boot-tegra/master and send the PR? I'll be sure to credit your work!

-----Original Message-----
From: Marcel Ziswiler [mailto:marcel.ziswiler at toradex.com]
Sent: Wednesday, August 05, 2015 8:33 AM
To: u-boot at lists.denx.de; Tom Warren
Cc: sjg at chromium.org; trini at konsulko.com; tomcwarren3959 at gmail.com; Thierry Reding; albert.u.boot at aribaud.net; Stephen Warren; yamada.m at jp.panasonic.com
Subject: Re: [PATCH] tegra: pll: fix pllx cpcon in pllinfo table for t20/t30

On Wed, 2015-08-05 at 15:23 +0000, Tom Warren wrote:

Quoted 3 lines

Do you mind if I just roll this into my pllinfo patch when I apply it to u-boot-tegra/master and send the PR? I'll be sure to credit your work!

Fine with me and no need for any further credits. Thanks Tom.

BTW: We are currently planning our ELCE trip to Dublin. Will any of you NVIDIA open-source maintainers make it there as well (e.g. to the U -Boot Summit)?

Quoted 17 lines

-----Original Message-----
From: Marcel Ziswiler [mailto:marcel.ziswiler at toradex.com]
Sent: Wednesday, August 05, 2015 8:33 AM
To: u-boot at lists.denx.de; Tom Warren
Cc: sjg at chromium.org; trini at konsulko.com; tomcwarren3959 at gmail.com; Thierry Reding; albert.u.boot at aribaud.net; Stephen Warren; yamada.m at jp.panasonic.com
Subject: Re: [PATCH] tegra: pll: fix pllx cpcon in pllinfo table for t20/t30

Quoted 3 lines · Tom Warren

Do you mind if I just roll this into my pllinfo patch when I apply it to u-boot-tegra/master and send the PR? I'll be sure to credit your work!

Quoted 4 lines

Fine with me and no need for any further credits. Thanks Tom.

BTW: We are currently planning our ELCE trip to Dublin. Will any of you NVIDIA open-source maintainers make it there as well (e.g. to the U -Boot Summit)?

I won't be able to make it - maybe Stephen?