Patch "MIPS: c-r4k: Fix cache flushing for MT cores" has been added to the 4.1-stable tree

This is a note to let you know that I've just added the patch titled

MIPS: c-r4k: Fix cache flushing for MT cores

to the 4.1-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
mips-c-r4k-fix-cache-flushing-for-mt-cores.patch
and it can be found in the queue-4.1 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From: Markos Chandras <[email protected]>
Date: Fri, 10 Jul 2015 09:29:10 +0100
Subject: MIPS: c-r4k: Fix cache flushing for MT cores

From: Markos Chandras <[email protected]>

commit cccf34e9411c41b0cbfb41980fe55fc8e7c98fd2 upstream.

MT_SMP is not the only SMP option for MT cores. The MT_SMP option allows more than one VPE per core to appear as a secondary CPU in the system. Because of how CM works, it propagates the address-based cache ops to the secondary cores but not the index-based ones. Because of that, the code does not use IPIs to flush the L1 caches on secondary cores because the CM would have done that already. However, the CM functionality is independent of the type of SMP kernel so even in non-MT kernels, IPIs are not necessary. As a result of which, we change the conditional to depend on the CM presence. Moreover, since VPEs on the same core share the same L1 caches, there is no need to send an IPI on all of them so we calculate a suitable cpumask with only one VPE per core.

Patchwork: https://patchwork.linux-mips.org/patch/10654/

---
 arch/mips/include/asm/smp.h |    1 +
 arch/mips/kernel/smp.c      |   44 +++++++++++++++++++++++++++++++++++++++++++-
 arch/mips/mm/c-r4k.c        |   14 +++++++++++---
 3 files changed, 55 insertions(+), 4 deletions(-)

@@ -23,6 +23,7 @@
 extern int smp_num_siblings;
 extern cpumask_t cpu_sibling_map[];
 extern cpumask_t cpu_core_map[];
+extern cpumask_t cpu_foreign_map;
 
 #define raw_smp_processor_id() (current_thread_info()->cpu)
 

@@ -37,6 +37,7 @@
 #include <asm/cacheflush.h> /* for run_uncached() */
 #include <asm/traps.h>
 #include <asm/dma-coherence.h>
+#include <asm/mips-cm.h>
 
 /*
  * Special Variant of smp_call_function for use by cache functions:

@@ -51,9 +52,16 @@ static inline void r4k_on_each_cpu(void
 {
 	preempt_disable();
 
-#ifndef CONFIG_MIPS_MT_SMP
-	smp_call_function(func, info, 1);
-#endif
+	/*
+	 * The Coherent Manager propagates address-based cache ops to other
+	 * cores but not index-based ops. However, r4k_on_each_cpu is used
+	 * in both cases so there is no easy way to tell what kind of op is
+	 * executed to the other cores. The best we can probably do is
+	 * to restrict that call when a CM is not present because both
+	 * CM-based SMP protocols (CMP & CPS) restrict index-based cache ops.
+	 */
+	if (!mips_cm_present())
+		smp_call_function_many(&cpu_foreign_map, func, info, 1);
 	func(info);
 	preempt_enable();
 }

Patches currently in stable-queue which might be from [email protected] are

queue-4.1/mips-kernel-cps-vec-replace-mips32r2-isa-level-with-mips64r2.patch queue-4.1/mips-kernel-cps-vec-use-ta0-ta3-pseudo-registers-for-64-bit.patch queue-4.1/revert-mips-kconfig-disable-smp-cps-for-64-bit.patch queue-4.1/mips-require-o32-fp64-support-for-mips64-with-o32-compat.patch queue-4.1/mips-fpu.h-allow-64-bit-fpu-on-a-64-bit-mips-r6-cpu.patch queue-4.1/mips-kernel-cps-vec-replace-la-macro-with-ptr_la.patch queue-4.1/mips-c-r4k-fix-cache-flushing-for-mt-cores.patch queue-4.1/mips-kernel-smp-cps-fix-64-bit-compatibility-errors-due-to-pointer-casting.patch queue-4.1/mips-kernel-cps-vec-replace-kseg0-with-ckseg0.patch queue-4.1/mips-fix-erroneous-jr-emulation-for-mips-r6.patch queue-4.1/mips-cps-vec-use-macros-for-various-arithmetics-and-memory-operations.patch