clk: Constify clk_hw argument to provider APIs

PATCH In review Stephen Boyd 6 participants 7 messages Aug 12, 2015 – Aug 13, 2015

Subsystems (10)

Arm Qualcomm mailing list Common clk Arm Samsung Exynos Tegra architecture support +6 more subsystems

lore

Share & tools

lore

Stephen Boyd

author

2015-08-12 23:12 UTC #0 lore raw

PATCH 1/2 clk: Constify clk_hw argument to provider APIs

We don't modify the clk_hw argument in these functions, so it's safe to mark it as const.

Signed-off-by Stephen Boyd <[email protected]>

---
 drivers/clk/clk.c            | 15 ++++++++-------
 include/linux/clk-provider.h | 14 +++++++-------
 2 files changed, 15 insertions(+), 14 deletions(-)

drivers/clk/clk.c +8 -7

index 128ad748b682..8e6688d1ecbd 100644
@@ -278,7 +278,7 @@ const char *__clk_get_name(struct clk *clk)
 }
 EXPORT_SYMBOL_GPL(__clk_get_name);
 
-const char *clk_hw_get_name(struct clk_hw *hw)
+const char *clk_hw_get_name(const struct clk_hw *hw)
 {
 	return hw->core->name;
 }

@@ -290,13 +290,13 @@ struct clk_hw *__clk_get_hw(struct clk *clk)
 }
 EXPORT_SYMBOL_GPL(__clk_get_hw);
 
-unsigned int clk_hw_get_num_parents(struct clk_hw *hw)
+unsigned int clk_hw_get_num_parents(const struct clk_hw *hw)
 {
 	return hw->core->num_parents;
 }
 EXPORT_SYMBOL_GPL(clk_hw_get_num_parents);
 
-struct clk_hw *clk_hw_get_parent(struct clk_hw *hw)
+struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw)
 {
 	return hw->core->parent ? hw->core->parent->hw : NULL;
 }

@@ -359,7 +359,8 @@ static struct clk_core *clk_core_get_parent_by_index(struct clk_core *core,
 		return core->parents[index];
 }
 
-struct clk_hw *clk_hw_get_parent_by_index(struct clk_hw *hw, unsigned int index)
+struct clk_hw *
+clk_hw_get_parent_by_index(const struct clk_hw *hw, unsigned int index)
 {
 	struct clk_core *parent;

@@ -395,7 +396,7 @@ out:
 	return ret;
 }
 
-unsigned long clk_hw_get_rate(struct clk_hw *hw)
+unsigned long clk_hw_get_rate(const struct clk_hw *hw)
 {
 	return clk_core_get_rate_nolock(hw->core);
 }

@@ -415,13 +416,13 @@ unsigned long __clk_get_flags(struct clk *clk)
 }
 EXPORT_SYMBOL_GPL(__clk_get_flags);
 
-unsigned long clk_hw_get_flags(struct clk_hw *hw)
+unsigned long clk_hw_get_flags(const struct clk_hw *hw)
 {
 	return hw->core->flags;
 }
 EXPORT_SYMBOL_GPL(clk_hw_get_flags);
 
-bool clk_hw_is_prepared(struct clk_hw *hw)
+bool clk_hw_is_prepared(const struct clk_hw *hw)
 {
 	return clk_core_is_prepared(hw->core);
 }

include/linux/clk-provider.h +7 -7

index 0d3128fbc14e..3ecc07d0da77 100644
@@ -607,17 +607,17 @@ void devm_clk_unregister(struct device *dev, struct clk *clk);
 
 /* helper functions */
 const char *__clk_get_name(struct clk *clk);
-const char *clk_hw_get_name(struct clk_hw *hw);
+const char *clk_hw_get_name(const struct clk_hw *hw);
 struct clk_hw *__clk_get_hw(struct clk *clk);
-unsigned int clk_hw_get_num_parents(struct clk_hw *hw);
-struct clk_hw *clk_hw_get_parent(struct clk_hw *hw);
-struct clk_hw *clk_hw_get_parent_by_index(struct clk_hw *hw,
+unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
+struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
+struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
 					  unsigned int index);
 unsigned int __clk_get_enable_count(struct clk *clk);
-unsigned long clk_hw_get_rate(struct clk_hw *hw);
+unsigned long clk_hw_get_rate(const struct clk_hw *hw);
 unsigned long __clk_get_flags(struct clk *clk);
-unsigned long clk_hw_get_flags(struct clk_hw *hw);
-bool clk_hw_is_prepared(struct clk_hw *hw);
+unsigned long clk_hw_get_flags(const struct clk_hw *hw);
+bool clk_hw_is_prepared(const struct clk_hw *hw);
 bool __clk_is_enabled(struct clk *clk);
 struct clk *__clk_lookup(const char *name);
 int __clk_mux_determine_rate(struct clk_hw *hw,

Signature · 2 lines

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Stephen Boyd

author

2015-08-12 23:12 UTC #1 lore raw

PATCH 2/2 clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)

Use the provider based method to get a clock's name so that we can get rid of the clk member in struct clk_hw one day. Mostly converted with the following coccinelle script.

@@
struct clk_hw *E;
@@

-__clk_get_name(E->clk)
+clk_hw_get_name(E)

Cc Heiko Stuebner <[email protected]>

Cc Sylwester Nawrocki <[email protected]>

Cc Tomasz Figa <[email protected]>

Cc Peter De Schrijver <[email protected]>

Cc Prashant Gaikwad <[email protected]>

Cc Stephen Warren <[email protected]>

Cc Thierry Reding <[email protected]>

Cc Alexandre Courbot <[email protected]>

Cc Tero Kristo <[email protected]>

Cc Ulf Hansson <[email protected]>

Cc Sebastian Hesselbarth <[email protected]>

Cc Andrew Bresticker <[email protected]>

Cc Ezequiel Garcia <[email protected]>

Cc Ralf Baechle <[email protected]>

Cc Kevin Cernekee <[email protected]>

Cc Geert Uytterhoeven <[email protected]>

Cc Ulrich Hecht <[email protected]>

Cc linux-arm-kernel at lists.infradead.org

Cc linux-rockchip at lists.infradead.org

Cc linux-samsung-soc at vger.kernel.org

Cc linux-tegra at vger.kernel.org

Cc linux-omap at vger.kernel.org

Signed-off-by Stephen Boyd <[email protected]>

---
 drivers/clk/berlin/berlin2-pll.c     |  4 ++--
 drivers/clk/clk-xgene.c              | 22 +++++++++++-----------
 drivers/clk/pistachio/clk-pll.c      |  4 ++--
 drivers/clk/qcom/clk-branch.c        |  2 +-
 drivers/clk/rockchip/clk-inverter.c  |  2 +-
 drivers/clk/rockchip/clk-mmc-phase.c |  2 +-
 drivers/clk/samsung/clk-pll.c        | 18 +++++++++---------
 drivers/clk/shmobile/clk-div6.c      |  2 +-
 drivers/clk/st/clk-flexgen.c         |  4 ++--
 drivers/clk/st/clkgen-fsyn.c         | 18 +++++++++---------
 drivers/clk/st/clkgen-mux.c          |  2 +-
 drivers/clk/st/clkgen-pll.c          |  8 ++++----
 drivers/clk/tegra/clk-pll.c          |  8 ++++----
 drivers/clk/ti/apll.c                |  4 ++--
 drivers/clk/ti/clkt_dflt.c           |  8 ++++----
 drivers/clk/ti/clockdomain.c         | 14 +++++++-------
 drivers/clk/ux500/clk-prcmu.c        | 16 ++++++++--------
 drivers/clk/ux500/clk-sysctrl.c      |  2 +-
 18 files changed, 70 insertions(+), 70 deletions(-)

drivers/clk/berlin/berlin2-pll.c +2 -2

index f4b8d324b083..1c2294d3ba85 100644
@@ -61,7 +61,7 @@ berlin2_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 	fbdiv = (val >> map->fbdiv_shift) & FBDIV_MASK;
 	rfdiv = (val >> map->rfdiv_shift) & RFDIV_MASK;
 	if (rfdiv == 0) {
-		pr_warn("%s has zero rfdiv\n", __clk_get_name(hw->clk));
+		pr_warn("%s has zero rfdiv\n", clk_hw_get_name(hw));
 		rfdiv = 1;
 	}

@@ -70,7 +70,7 @@ berlin2_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 	vcodiv = map->vcodiv[vcodivsel];
 	if (vcodiv == 0) {
 		pr_warn("%s has zero vcodiv (index %d)\n",
-			__clk_get_name(hw->clk), vcodivsel);
+			clk_hw_get_name(hw), vcodivsel);
 		vcodiv = 1;
 	}

drivers/clk/clk-xgene.c +11 ~~-11~~

index 4caee9356407..96a6190acac2 100644
@@ -74,7 +74,7 @@ static int xgene_clk_pll_is_enabled(struct clk_hw *hw)
 	u32 data;
 
 	data = xgene_clk_read(pllclk->reg + pllclk->pll_offset);
-	pr_debug("%s pll %s\n", __clk_get_name(hw->clk),
+	pr_debug("%s pll %s\n", clk_hw_get_name(hw),
 		data & REGSPEC_RESET_F1_MASK ? "disabled" : "enabled");
 
 	return data & REGSPEC_RESET_F1_MASK ? 0 : 1;

@@ -112,7 +112,7 @@ static unsigned long xgene_clk_pll_recalc_rate(struct clk_hw *hw,
 		fref = parent_rate / nref;
 		fvco = fref * nfb;
 	}
-	pr_debug("%s pll recalc rate %ld parent %ld\n", __clk_get_name(hw->clk),
+	pr_debug("%s pll recalc rate %ld parent %ld\n", clk_hw_get_name(hw),
 		fvco / nout, parent_rate);
 
 	return fvco / nout;

@@ -225,7 +225,7 @@ static int xgene_clk_enable(struct clk_hw *hw)
 		spin_lock_irqsave(pclk->lock, flags);
 
 	if (pclk->param.csr_reg != NULL) {
-		pr_debug("%s clock enabled\n", __clk_get_name(hw->clk));
+		pr_debug("%s clock enabled\n", clk_hw_get_name(hw));
 		reg = __pa(pclk->param.csr_reg);
 		/* First enable the clock */
 		data = xgene_clk_read(pclk->param.csr_reg +

@@ -234,7 +234,7 @@ static int xgene_clk_enable(struct clk_hw *hw)
 		xgene_clk_write(data, pclk->param.csr_reg +
 					pclk->param.reg_clk_offset);
 		pr_debug("%s clock PADDR base %pa clk offset 0x%08X mask 0x%08X value 0x%08X\n",
-			__clk_get_name(hw->clk), &reg,
+			clk_hw_get_name(hw), &reg,
 			pclk->param.reg_clk_offset, pclk->param.reg_clk_mask,
 			data);

@@ -245,7 +245,7 @@ static int xgene_clk_enable(struct clk_hw *hw)
 		xgene_clk_write(data, pclk->param.csr_reg +
 					pclk->param.reg_csr_offset);
 		pr_debug("%s CSR RESET PADDR base %pa csr offset 0x%08X mask 0x%08X value 0x%08X\n",
-			__clk_get_name(hw->clk), &reg,
+			clk_hw_get_name(hw), &reg,
 			pclk->param.reg_csr_offset, pclk->param.reg_csr_mask,
 			data);
 	}

@@ -266,7 +266,7 @@ static void xgene_clk_disable(struct clk_hw *hw)
 		spin_lock_irqsave(pclk->lock, flags);
 
 	if (pclk->param.csr_reg != NULL) {
-		pr_debug("%s clock disabled\n", __clk_get_name(hw->clk));
+		pr_debug("%s clock disabled\n", clk_hw_get_name(hw));
 		/* First put the CSR in reset */
 		data = xgene_clk_read(pclk->param.csr_reg +
 					pclk->param.reg_csr_offset);

@@ -292,10 +292,10 @@ static int xgene_clk_is_enabled(struct clk_hw *hw)
 	u32 data = 0;
 
 	if (pclk->param.csr_reg != NULL) {
-		pr_debug("%s clock checking\n", __clk_get_name(hw->clk));
+		pr_debug("%s clock checking\n", clk_hw_get_name(hw));
 		data = xgene_clk_read(pclk->param.csr_reg +
 					pclk->param.reg_clk_offset);
-		pr_debug("%s clock is %s\n", __clk_get_name(hw->clk),
+		pr_debug("%s clock is %s\n", clk_hw_get_name(hw),
 			data & pclk->param.reg_clk_mask ? "enabled" :
 							"disabled");
 	}

@@ -318,13 +318,13 @@ static unsigned long xgene_clk_recalc_rate(struct clk_hw *hw,
 		data &= (1 << pclk->param.reg_divider_width) - 1;
 
 		pr_debug("%s clock recalc rate %ld parent %ld\n",
-			__clk_get_name(hw->clk),
+			clk_hw_get_name(hw),
 			parent_rate / data, parent_rate);
 
 		return parent_rate / data;
 	} else {
 		pr_debug("%s clock recalc rate %ld parent %ld\n",
-			__clk_get_name(hw->clk), parent_rate, parent_rate);
+			clk_hw_get_name(hw), parent_rate, parent_rate);
 		return parent_rate;
 	}
 }

@@ -356,7 +356,7 @@ static int xgene_clk_set_rate(struct clk_hw *hw, unsigned long rate,
 		data |= divider;
 		xgene_clk_write(data, pclk->param.divider_reg +
 					pclk->param.reg_divider_offset);
-		pr_debug("%s clock set rate %ld\n", __clk_get_name(hw->clk),
+		pr_debug("%s clock set rate %ld\n", clk_hw_get_name(hw),
 			parent_rate / divider_save);
 	} else {
 		divider_save = 1;

drivers/clk/pistachio/clk-pll.c +2 -2

index e17dada0dd21..addfec731333 100644
@@ -174,7 +174,7 @@ static int pll_gf40lp_frac_set_rate(struct clk_hw *hw, unsigned long rate,
 	struct pistachio_pll_rate_table *params;
 	int enabled = pll_gf40lp_frac_is_enabled(hw);
 	u32 val, vco, old_postdiv1, old_postdiv2;
-	const char *name = __clk_get_name(hw->clk);
+	const char *name = clk_hw_get_name(hw);
 
 	if (rate < MIN_OUTPUT_FRAC || rate > MAX_OUTPUT_FRAC)
 		return -EINVAL;

@@ -316,7 +316,7 @@ static int pll_gf40lp_laint_set_rate(struct clk_hw *hw, unsigned long rate,
 	struct pistachio_pll_rate_table *params;
 	int enabled = pll_gf40lp_laint_is_enabled(hw);
 	u32 val, vco, old_postdiv1, old_postdiv2;
-	const char *name = __clk_get_name(hw->clk);
+	const char *name = clk_hw_get_name(hw);
 
 	if (rate < MIN_OUTPUT_LA || rate > MAX_OUTPUT_LA)
 		return -EINVAL;

drivers/clk/qcom/clk-branch.c +1 -1

index 6b4d2bcb1a53..26f7af315066 100644
@@ -75,7 +75,7 @@ static int clk_branch_wait(const struct clk_branch *br, bool enabling,
 		bool (check_halt)(const struct clk_branch *, bool))
 {
 	bool voted = br->halt_check & BRANCH_VOTED;
-	const char *name = __clk_get_name(br->clkr.hw.clk);
+	const char *name = clk_hw_get_name(&br->clkr.hw);
 
 	/* Skip checking halt bit if the clock is in hardware gated mode */
 	if (clk_branch_in_hwcg_mode(br))

drivers/clk/rockchip/clk-inverter.c +1 -1

index 8054fdb5effb..7cbf43beb3c6 100644
@@ -50,7 +50,7 @@ static int rockchip_inv_set_phase(struct clk_hw *hw, int degrees)
 		val = !!degrees;
 	} else {
 		pr_err("%s: unsupported phase %d for %s\n",
-		       __func__, degrees, __clk_get_name(hw->clk));
+		       __func__, degrees, clk_hw_get_name(hw));
 		return -EINVAL;
 	}

drivers/clk/rockchip/clk-mmc-phase.c +1 -1

index 77e19097bdc7..9b613426e968 100644
@@ -108,7 +108,7 @@ static int rockchip_mmc_set_phase(struct clk_hw *hw, int degrees)
 	writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift), mmc_clock->reg);
 
 	pr_debug("%s->set_phase(%d) delay_nums=%u reg[0x%p]=0x%03x actual_degrees=%d\n",
-		__clk_get_name(hw->clk), degrees, delay_num,
+		clk_hw_get_name(hw), degrees, delay_num,
 		mmc_clock->reg, raw_value>>(mmc_clock->shift),
 		rockchip_mmc_get_phase(hw)
 	);

drivers/clk/samsung/clk-pll.c +9 -9

index e9394261f80f..b7dd396100d8 100644
@@ -182,7 +182,7 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
 	rate = samsung_get_pll_settings(pll, drate);
 	if (!rate) {
 		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
-			drate, __clk_get_name(hw->clk));
+			drate, clk_hw_get_name(hw));
 		return -EINVAL;
 	}

@@ -290,7 +290,7 @@ static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate,
 	rate = samsung_get_pll_settings(pll, drate);
 	if (!rate) {
 		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
-			drate, __clk_get_name(hw->clk));
+			drate, clk_hw_get_name(hw));
 		return -EINVAL;
 	}

@@ -405,7 +405,7 @@ static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate,
 	rate = samsung_get_pll_settings(pll, drate);
 	if (!rate) {
 		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
-			drate, __clk_get_name(hw->clk));
+			drate, clk_hw_get_name(hw));
 		return -EINVAL;
 	}

@@ -457,7 +457,7 @@ static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate,
 
 		if (ktime_to_ms(delta) > PLL_TIMEOUT_MS) {
 			pr_err("%s: could not lock PLL %s\n",
-					__func__, __clk_get_name(hw->clk));
+					__func__, clk_hw_get_name(hw));
 			return -EFAULT;
 		}

@@ -556,7 +556,7 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate,
 	rate = samsung_get_pll_settings(pll, drate);
 	if (!rate) {
 		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
-			drate, __clk_get_name(hw->clk));
+			drate, clk_hw_get_name(hw));
 		return -EINVAL;
 	}

@@ -616,7 +616,7 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate,
 
 		if (ktime_to_ms(delta) > PLL_TIMEOUT_MS) {
 			pr_err("%s: could not lock PLL %s\n",
-					__func__, __clk_get_name(hw->clk));
+					__func__, clk_hw_get_name(hw));
 			return -EFAULT;
 		}

@@ -774,7 +774,7 @@ static int samsung_s3c2410_pll_set_rate(struct clk_hw *hw, unsigned long drate,
 	rate = samsung_get_pll_settings(pll, drate);
 	if (!rate) {
 		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
-			drate, __clk_get_name(hw->clk));
+			drate, clk_hw_get_name(hw));
 		return -EINVAL;
 	}

@@ -1015,7 +1015,7 @@ static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate,
 	rate = samsung_get_pll_settings(pll, drate);
 	if (!rate) {
 		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
-			drate, __clk_get_name(hw->clk));
+			drate, clk_hw_get_name(hw));
 		return -EINVAL;
 	}

@@ -1113,7 +1113,7 @@ static int samsung_pll2650xx_set_rate(struct clk_hw *hw, unsigned long drate,
 	rate = samsung_get_pll_settings(pll, drate);
 	if (!rate) {
 		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
-			drate, __clk_get_name(hw->clk));
+			drate, clk_hw_get_name(hw));
 		return -EINVAL;
 	}

drivers/clk/shmobile/clk-div6.c +1 -1

index ee66f49812df..b4c8d6746f68 100644
@@ -139,7 +139,7 @@ static u8 cpg_div6_clock_get_parent(struct clk_hw *hw)
 	}
 
 	pr_err("%s: %s DIV6 clock set to invalid parent %u\n",
-	       __func__, __clk_get_name(hw->clk), hw_index);
+	       __func__, clk_hw_get_name(hw), hw_index);
 	return 0;
 }

drivers/clk/st/clk-flexgen.c +2 -2

index 965b13ba3515..bd355ee33766 100644
@@ -45,7 +45,7 @@ static int flexgen_enable(struct clk_hw *hw)
 
 	clk_gate_ops.enable(fgate_hw);
 
-	pr_debug("%s: flexgen output enabled\n", __clk_get_name(hw->clk));
+	pr_debug("%s: flexgen output enabled\n", clk_hw_get_name(hw));
 	return 0;
 }

@@ -59,7 +59,7 @@ static void flexgen_disable(struct clk_hw *hw)
 
 	clk_gate_ops.disable(fgate_hw);
 
-	pr_debug("%s: flexgen output disabled\n", __clk_get_name(hw->clk));
+	pr_debug("%s: flexgen output disabled\n", clk_hw_get_name(hw));
 }
 
 static int flexgen_is_enabled(struct clk_hw *hw)

drivers/clk/st/clkgen-fsyn.c +9 -9

index aa3117db4514..83ccf142ff2a 100644
@@ -513,7 +513,7 @@ static unsigned long quadfs_pll_fs660c32_recalc_rate(struct clk_hw *hw,
 	params.ndiv = CLKGEN_READ(pll, ndiv);
 	if (clk_fs660c32_vco_get_rate(parent_rate, &params, &rate))
 		pr_err("%s:%s error calculating rate\n",
-		       __clk_get_name(hw->clk), __func__);
+		       clk_hw_get_name(hw), __func__);
 
 	pll->ndiv = params.ndiv;

@@ -558,7 +558,7 @@ static long quadfs_pll_fs660c32_round_rate(struct clk_hw *hw, unsigned long rate
 		clk_fs660c32_vco_get_rate(*prate, &params, &rate);
 
 	pr_debug("%s: %s new rate %ld [sdiv=0x%x,md=0x%x,pe=0x%x,nsdiv3=%u]\n",
-		 __func__, __clk_get_name(hw->clk),
+		 __func__, clk_hw_get_name(hw),
 		 rate, (unsigned int)params.sdiv,
 		 (unsigned int)params.mdiv,
 		 (unsigned int)params.pe, (unsigned int)params.nsdiv);

@@ -581,7 +581,7 @@ static int quadfs_pll_fs660c32_set_rate(struct clk_hw *hw, unsigned long rate,
 		clk_fs660c32_vco_get_rate(parent_rate, &params, &hwrate);
 
 	pr_debug("%s: %s new rate %ld [ndiv=0x%x]\n",
-		 __func__, __clk_get_name(hw->clk),
+		 __func__, clk_hw_get_name(hw),
 		 hwrate, (unsigned int)params.ndiv);
 
 	if (!hwrate)

@@ -745,7 +745,7 @@ static int quadfs_fsynth_enable(struct clk_hw *hw)
 	struct st_clk_quadfs_fsynth *fs = to_quadfs_fsynth(hw);
 	unsigned long flags = 0;
 
-	pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
+	pr_debug("%s: %s\n", __func__, clk_hw_get_name(hw));
 
 	quadfs_fsynth_program_rate(fs);

@@ -770,7 +770,7 @@ static void quadfs_fsynth_disable(struct clk_hw *hw)
 	struct st_clk_quadfs_fsynth *fs = to_quadfs_fsynth(hw);
 	unsigned long flags = 0;
 
-	pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
+	pr_debug("%s: %s\n", __func__, clk_hw_get_name(hw));
 
 	if (fs->lock)
 		spin_lock_irqsave(fs->lock, flags);

@@ -787,7 +787,7 @@ static int quadfs_fsynth_is_enabled(struct clk_hw *hw)
 	u32 nsb = CLKGEN_READ(fs, nsb[fs->chan]);
 
 	pr_debug("%s: %s enable bit = 0x%x\n",
-		 __func__, __clk_get_name(hw->clk), nsb);
+		 __func__, clk_hw_get_name(hw), nsb);
 
 	return fs->data->standby_polarity ? !nsb : !!nsb;
 }

@@ -946,10 +946,10 @@ static unsigned long quadfs_recalc_rate(struct clk_hw *hw,
 
 	if (clk_fs_get_rate(parent_rate, &params, &rate)) {
 		pr_err("%s:%s error calculating rate\n",
-		       __clk_get_name(hw->clk), __func__);
+		       clk_hw_get_name(hw), __func__);
 	}
 
-	pr_debug("%s:%s rate %lu\n", __clk_get_name(hw->clk), __func__, rate);
+	pr_debug("%s:%s rate %lu\n", clk_hw_get_name(hw), __func__, rate);
 
 	return rate;
 }

@@ -962,7 +962,7 @@ static long quadfs_round_rate(struct clk_hw *hw, unsigned long rate,
 	rate = quadfs_find_best_rate(hw, rate, *prate, &params);
 
 	pr_debug("%s: %s new rate %ld [sdiv=0x%x,md=0x%x,pe=0x%x,nsdiv3=%u]\n",
-		 __func__, __clk_get_name(hw->clk),
+		 __func__, clk_hw_get_name(hw),
 		 rate, (unsigned int)params.sdiv, (unsigned int)params.mdiv,
 			 (unsigned int)params.pe, (unsigned int)params.nsdiv);

drivers/clk/st/clkgen-mux.c +1 -1

index 81f2372b97ff..4f7f6c00b219 100644
@@ -139,7 +139,7 @@ static u8 clkgena_divmux_get_parent(struct clk_hw *hw)
 	genamux->muxsel = clk_mux_ops.get_parent(mux_hw);
 	if ((s8)genamux->muxsel < 0) {
 		pr_debug("%s: %s: Invalid parent, setting to default.\n",
-		      __func__, __clk_get_name(hw->clk));
+		      __func__, clk_hw_get_name(hw));
 		genamux->muxsel = 0;
 	}

drivers/clk/st/clkgen-pll.c +4 -4

index cc2b52ec730a..47a38a994cac 100644
@@ -292,7 +292,7 @@ static unsigned long recalc_stm_pll800c65(struct clk_hw *hw,
 	res = (uint64_t)2 * (uint64_t)parent_rate * (uint64_t)ndiv;
 	rate = (unsigned long)div64_u64(res, mdiv * (1 << pdiv));
 
-	pr_debug("%s:%s rate %lu\n", __clk_get_name(hw->clk), __func__, rate);
+	pr_debug("%s:%s rate %lu\n", clk_hw_get_name(hw), __func__, rate);
 
 	return rate;

@@ -317,7 +317,7 @@ static unsigned long recalc_stm_pll1600c65(struct clk_hw *hw,
 	/* Note: input is divided by 1000 to avoid overflow */
 	rate = ((2 * (parent_rate / 1000) * ndiv) / mdiv) * 1000;
 
-	pr_debug("%s:%s rate %lu\n", __clk_get_name(hw->clk), __func__, rate);
+	pr_debug("%s:%s rate %lu\n", clk_hw_get_name(hw), __func__, rate);
 
 	return rate;
 }

@@ -339,7 +339,7 @@ static unsigned long recalc_stm_pll3200c32(struct clk_hw *hw,
 		/* Note: input is divided to avoid overflow */
 		rate = ((2 * (parent_rate/1000) * ndiv) / idf) * 1000;
 
-	pr_debug("%s:%s rate %lu\n", __clk_get_name(hw->clk), __func__, rate);
+	pr_debug("%s:%s rate %lu\n", clk_hw_get_name(hw), __func__, rate);
 
 	return rate;
 }

@@ -366,7 +366,7 @@ static unsigned long recalc_stm_pll1200c32(struct clk_hw *hw,
 	/* Note: input is divided by 1000 to avoid overflow */
 	rate = (((parent_rate / 1000) * ldf) / (odf * idf)) * 1000;
 
-	pr_debug("%s:%s rate %lu\n", __clk_get_name(hw->clk), __func__, rate);
+	pr_debug("%s:%s rate %lu\n", clk_hw_get_name(hw), __func__, rate);
 
 	return rate;
 }

drivers/clk/tegra/clk-pll.c +4 -4

index 69fea7d08681..d6d4ecb88e94 100644
@@ -264,7 +264,7 @@ static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
 	}
 
 	pr_err("%s: Timed out waiting for pll %s lock\n", __func__,
-	       __clk_get_name(pll->hw.clk));
+	       clk_hw_get_name(&pll->hw));
 
 	return -1;
 }

@@ -595,7 +595,7 @@ static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 	if (pll->params->flags & TEGRA_PLL_FIXED) {
 		if (rate != pll->params->fixed_rate) {
 			pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
-				__func__, __clk_get_name(hw->clk),
+				__func__, clk_hw_get_name(hw),
 				pll->params->fixed_rate, rate);
 			return -EINVAL;
 		}

@@ -605,7 +605,7 @@ static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 	if (_get_table_rate(hw, &cfg, rate, parent_rate) &&
 	    _calc_rate(hw, &cfg, rate, parent_rate)) {
 		pr_err("%s: Failed to set %s rate %lu\n", __func__,
-		       __clk_get_name(hw->clk), rate);
+		       clk_hw_get_name(hw), rate);
 		WARN_ON(1);
 		return -EINVAL;
 	}

@@ -663,7 +663,7 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
 		if (_get_table_rate(hw, &sel, pll->params->fixed_rate,
 					parent_rate)) {
 			pr_err("Clock %s has unknown fixed frequency\n",
-			       __clk_get_name(hw->clk));
+			       clk_hw_get_name(hw));
 			BUG();
 		}
 		return pll->params->fixed_rate;

drivers/clk/ti/apll.c +2 -2

index 24febd4fe324..f3eab6e79027 100644
@@ -50,7 +50,7 @@ static int dra7_apll_enable(struct clk_hw *hw)
 	if (!ad)
 		return -EINVAL;
 
-	clk_name = __clk_get_name(clk->hw.clk);
+	clk_name = clk_hw_get_name(&clk->hw);
 
 	state <<= __ffs(ad->idlest_mask);

@@ -273,7 +273,7 @@ static int omap2_apll_enable(struct clk_hw *hw)
 
 	if (i == MAX_APLL_WAIT_TRIES) {
 		pr_warn("%s failed to transition to locked\n",
-			__clk_get_name(clk->hw.clk));
+			clk_hw_get_name(&clk->hw));
 		return -EBUSY;
 	}

drivers/clk/ti/clkt_dflt.c +4 -4

index a176b8ac8dd0..90d7d8a21c49 100644
@@ -110,7 +110,7 @@ static void _omap2_module_wait_ready(struct clk_hw_omap *clk)
 	if (r) {
 		/* IDLEST register not in the CM module */
 		_wait_idlest_generic(clk, idlest_reg, (1 << idlest_bit),
-				     idlest_val, __clk_get_name(clk->hw.clk));
+				     idlest_val, clk_hw_get_name(&clk->hw));
 	} else {
 		ti_clk_ll_ops->cm_wait_module_ready(0, prcm_mod, idlest_reg_id,
 						    idlest_bit);

@@ -216,7 +216,7 @@ int omap2_dflt_clk_enable(struct clk_hw *hw)
 		if (ret) {
 			WARN(1,
 			     "%s: could not enable %s's clockdomain %s: %d\n",
-			     __func__, __clk_get_name(hw->clk),
+			     __func__, clk_hw_get_name(hw),
 			     clk->clkdm_name, ret);
 			return ret;
 		}

@@ -224,7 +224,7 @@ int omap2_dflt_clk_enable(struct clk_hw *hw)
 
 	if (unlikely(!clk->enable_reg)) {
 		pr_err("%s: %s missing enable_reg\n", __func__,
-		       __clk_get_name(hw->clk));
+		       clk_hw_get_name(hw));
 		ret = -EINVAL;
 		goto err;
 	}

@@ -270,7 +270,7 @@ void omap2_dflt_clk_disable(struct clk_hw *hw)
 		 * controlled by its parent.
 		 */
 		pr_err("%s: independent clock %s has no enable_reg\n",
-		       __func__, __clk_get_name(hw->clk));
+		       __func__, clk_hw_get_name(hw));
 		return;
 	}

drivers/clk/ti/clockdomain.c +7 -7

index 362a62c10311..b9bc3b8df659 100644
@@ -48,23 +48,23 @@ int omap2_clkops_enable_clkdm(struct clk_hw *hw)
 
 	if (unlikely(!clk->clkdm)) {
 		pr_err("%s: %s: no clkdm set ?!\n", __func__,
-		       __clk_get_name(hw->clk));
+		       clk_hw_get_name(hw));
 		return -EINVAL;
 	}
 
 	if (unlikely(clk->enable_reg))
 		pr_err("%s: %s: should use dflt_clk_enable ?!\n", __func__,
-		       __clk_get_name(hw->clk));
+		       clk_hw_get_name(hw));
 
 	if (ti_clk_get_features()->flags & TI_CLK_DISABLE_CLKDM_CONTROL) {
 		pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n",
-		       __func__, __clk_get_name(hw->clk));
+		       __func__, clk_hw_get_name(hw));
 		return 0;
 	}
 
 	ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk);
 	WARN(ret, "%s: could not enable %s's clockdomain %s: %d\n",
-	     __func__, __clk_get_name(hw->clk), clk->clkdm_name, ret);
+	     __func__, clk_hw_get_name(hw), clk->clkdm_name, ret);
 
 	return ret;
 }

@@ -86,17 +86,17 @@ void omap2_clkops_disable_clkdm(struct clk_hw *hw)
 
 	if (unlikely(!clk->clkdm)) {
 		pr_err("%s: %s: no clkdm set ?!\n", __func__,
-		       __clk_get_name(hw->clk));
+		       clk_hw_get_name(hw));
 		return;
 	}
 
 	if (unlikely(clk->enable_reg))
 		pr_err("%s: %s: should use dflt_clk_disable ?!\n", __func__,
-		       __clk_get_name(hw->clk));
+		       clk_hw_get_name(hw));
 
 	if (ti_clk_get_features()->flags & TI_CLK_DISABLE_CLKDM_CONTROL) {
 		pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n",
-		       __func__, __clk_get_name(hw->clk));
+		       __func__, clk_hw_get_name(hw));
 		return;
 	}

drivers/clk/ux500/clk-prcmu.c +8 -8

index bf63c96acb1a..7f343821f4e4 100644
@@ -43,7 +43,7 @@ static void clk_prcmu_unprepare(struct clk_hw *hw)
 	struct clk_prcmu *clk = to_clk_prcmu(hw);
 	if (prcmu_request_clock(clk->cg_sel, false))
 		pr_err("clk_prcmu: %s failed to disable %s.\n", __func__,
-			__clk_get_name(hw->clk));
+			clk_hw_get_name(hw));
 	else
 		clk->is_prepared = 0;
 }

@@ -101,11 +101,11 @@ static int clk_prcmu_opp_prepare(struct clk_hw *hw)
 
 	if (!clk->opp_requested) {
 		err = prcmu_qos_add_requirement(PRCMU_QOS_APE_OPP,
-						(char *)__clk_get_name(hw->clk),
+						(char *)clk_hw_get_name(hw),
 						100);
 		if (err) {
 			pr_err("clk_prcmu: %s fail req APE OPP for %s.\n",
-				__func__, __clk_get_name(hw->clk));
+				__func__, clk_hw_get_name(hw));
 			return err;
 		}
 		clk->opp_requested = 1;

@@ -114,7 +114,7 @@ static int clk_prcmu_opp_prepare(struct clk_hw *hw)
 	err = prcmu_request_clock(clk->cg_sel, true);
 	if (err) {
 		prcmu_qos_remove_requirement(PRCMU_QOS_APE_OPP,
-					(char *)__clk_get_name(hw->clk));
+					(char *)clk_hw_get_name(hw));
 		clk->opp_requested = 0;
 		return err;
 	}

@@ -129,13 +129,13 @@ static void clk_prcmu_opp_unprepare(struct clk_hw *hw)
 
 	if (prcmu_request_clock(clk->cg_sel, false)) {
 		pr_err("clk_prcmu: %s failed to disable %s.\n", __func__,
-			__clk_get_name(hw->clk));
+			clk_hw_get_name(hw));
 		return;
 	}
 
 	if (clk->opp_requested) {
 		prcmu_qos_remove_requirement(PRCMU_QOS_APE_OPP,
-					(char *)__clk_get_name(hw->clk));
+					(char *)clk_hw_get_name(hw));
 		clk->opp_requested = 0;
 	}

@@ -151,7 +151,7 @@ static int clk_prcmu_opp_volt_prepare(struct clk_hw *hw)
 		err = prcmu_request_ape_opp_100_voltage(true);
 		if (err) {
 			pr_err("clk_prcmu: %s fail req APE OPP VOLT for %s.\n",
-				__func__, __clk_get_name(hw->clk));
+				__func__, clk_hw_get_name(hw));
 			return err;
 		}
 		clk->opp_requested = 1;

@@ -174,7 +174,7 @@ static void clk_prcmu_opp_volt_unprepare(struct clk_hw *hw)
 
 	if (prcmu_request_clock(clk->cg_sel, false)) {
 		pr_err("clk_prcmu: %s failed to disable %s.\n", __func__,
-			__clk_get_name(hw->clk));
+			clk_hw_get_name(hw));
 		return;
 	}

drivers/clk/ux500/clk-sysctrl.c +1 -1

index e364c9d4aa60..266ddea630d2 100644
@@ -52,7 +52,7 @@ static void clk_sysctrl_unprepare(struct clk_hw *hw)
 	struct clk_sysctrl *clk = to_clk_sysctrl(hw);
 	if (ab8500_sysctrl_clear(clk->reg_sel[0], clk->reg_mask[0]))
 		dev_err(clk->dev, "clk_sysctrl: %s fail to clear %s.\n",
-			__func__, __clk_get_name(hw->clk));
+			__func__, clk_hw_get_name(hw));
 }
 
 static unsigned long clk_sysctrl_recalc_rate(struct clk_hw *hw,

Signature · 2 lines

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Heiko Stübner

maintainer Reviewed-by on v1 2/2

2015-08-13 07:57 UTC #2 lore raw

Re: [PATCH 2/2] clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)

Am Mittwoch, 12. August 2015, 16:12:41 schrieb Stephen Boyd:

Review

Quoted 11 lines

Use the provider based method to get a clock's name so that we can get rid of the clk member in struct clk_hw one day. Mostly converted with the following coccinelle script.
@@
struct clk_hw *E;
@@
(quoted diff) +1 -1
-__clk_get_name(E->clk)
+clk_hw_get_name(E)

For the Rockchip part

Reviewed-by Heiko Stuebner <[email protected]>

Heiko

Quoted 29 lines

(quoted diff) +0 -0

b/drivers/clk/rockchip/clk-inverter.c index 8054fdb5effb..7cbf43beb3c6 100644

drivers/clk/rockchip/clk-inverter.c +1 -1

@@ -50,7 +50,7 @@ static int rockchip_inv_set_phase(struct clk_hw *hw, int
 degrees) val = !!degrees;
 	} else {
 		pr_err("%s: unsupported phase %d for %s\n",
-		       __func__, degrees, __clk_get_name(hw->clk));
+		       __func__, degrees, clk_hw_get_name(hw));
 		return -EINVAL;
 	}

(quoted diff) +0 -0

b/drivers/clk/rockchip/clk-mmc-phase.c index 77e19097bdc7..9b613426e968 100644

drivers/clk/rockchip/clk-mmc-phase.c +1 -0

@@ -108,7 +108,7 @@ static int rockchip_mmc_set_phase(struct clk_hw *hw, int
 degrees) writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift),
 mmc_clock->reg);
 
 	pr_debug("%s->set_phase(%d) delay_nums=%u reg[0x%p]=0x%03x
 actual_degrees=%d\n", -		__clk_get_name(hw->clk), degrees, delay_num,
+		clk_hw_get_name(hw), degrees, delay_num,
 		mmc_clock->reg, raw_value>>(mmc_clock->shift),
 		rockchip_mmc_get_phase(hw)
 	);

Geert Uytterhoeven

Acked-by on v1 2/2

2015-08-13 08:41 UTC #3 lore raw

Re: [PATCH 2/2] clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)

In reply to Stephen Boyd

Quoted 35 lines · Stephen Boyd

Use the provider based method to get a clock's name so that we can get rid of the clk member in struct clk_hw one day. Mostly converted with the following coccinelle script.
@@
struct clk_hw *E;
@@
(quoted diff) +1 -1
-__clk_get_name(E->clk)
+clk_hw_get_name(E)
Cc Heiko Stuebner <[email protected]>
Cc Sylwester Nawrocki <[email protected]>
Cc Tomasz Figa <[email protected]>
Cc Peter De Schrijver <[email protected]>
Cc Prashant Gaikwad <[email protected]>
Cc Stephen Warren <[email protected]>
Cc Thierry Reding <[email protected]>
Cc Alexandre Courbot <[email protected]>
Cc Tero Kristo <[email protected]>
Cc Ulf Hansson <[email protected]>
Cc Sebastian Hesselbarth <[email protected]>
Cc Andrew Bresticker <[email protected]>
Cc Ezequiel Garcia <[email protected]>
Cc Ralf Baechle <[email protected]>
Cc Kevin Cernekee <[email protected]>
Cc Geert Uytterhoeven <[email protected]>
Cc Ulrich Hecht <[email protected]>
Cc linux-arm-kernel at lists.infradead.org
Cc linux-rockchip at lists.infradead.org
Cc linux-samsung-soc at vger.kernel.org
Cc linux-tegra at vger.kernel.org
Cc linux-omap at vger.kernel.org
Signed-off-by Stephen Boyd <[email protected]>

Quoted 1 line

 drivers/clk/shmobile/clk-div6.c      |  2 +-

For the shmobile part:

Acked-by Geert Uytterhoeven <[email protected]>

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Sebastian Hesselbarth

Acked-by on v1 2/2

2015-08-13 08:56 UTC #4 lore raw

Re: [PATCH 2/2] clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)

In reply to Stephen Boyd

Quoted 10 lines · Stephen Boyd

Use the provider based method to get a clock's name so that we can get rid of the clk member in struct clk_hw one day. Mostly converted with the following coccinelle script.
@@
struct clk_hw *E;
@@
(quoted diff) +1 -1
-__clk_get_name(E->clk)
+clk_hw_get_name(E)

[...]

Quoted 3 lines

Signed-off-by Stephen Boyd <[email protected]>
---
  drivers/clk/berlin/berlin2-pll.c     |  4 ++--

For Berlin,

Acked-by Sebastian Hesselbarth <[email protected]>

Thanks!

[...]

Quoted 21 lines

drivers/clk/berlin/berlin2-pll.c +2 -2

index f4b8d324b083..1c2294d3ba85 100644
@@ -61,7 +61,7 @@ berlin2_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
  	fbdiv = (val >> map->fbdiv_shift) & FBDIV_MASK;
  	rfdiv = (val >> map->rfdiv_shift) & RFDIV_MASK;
  	if (rfdiv == 0) {
-		pr_warn("%s has zero rfdiv\n", __clk_get_name(hw->clk));
+		pr_warn("%s has zero rfdiv\n", clk_hw_get_name(hw));
  		rfdiv = 1;
  	}

@@ -70,7 +70,7 @@ berlin2_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
  	vcodiv = map->vcodiv[vcodivsel];
  	if (vcodiv == 0) {
  		pr_warn("%s has zero vcodiv (index %d)\n",
-			__clk_get_name(hw->clk), vcodivsel);
+			clk_hw_get_name(hw), vcodivsel);
  		vcodiv = 1;
  	}

Thierry Reding

Acked-by on v1 2/2

2015-08-13 09:07 UTC #5 lore raw

Re: [PATCH 2/2] clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)

In reply to Stephen Boyd

Quoted 11 lines · Stephen Boyd

Use the provider based method to get a clock's name so that we can get rid of the clk member in struct clk_hw one day. Mostly converted with the following coccinelle script.
@@
struct clk_hw *E;
@@
(quoted diff) +1 -1
-__clk_get_name(E->clk)
+clk_hw_get_name(E)

[...]

Quoted 1 line

 drivers/clk/tegra/clk-pll.c          |  8 ++++----

Acked-by Thierry Reding <[email protected]>

-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 819 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20150813/acb6e08a/attachment.sig>

Andrew Bresticker

Acked-by on v1 2/2

2015-08-13 16:40 UTC #6 lore raw

Re: [PATCH 2/2] clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)

In reply to Stephen Boyd

Quoted 35 lines · Stephen Boyd

Use the provider based method to get a clock's name so that we can get rid of the clk member in struct clk_hw one day. Mostly converted with the following coccinelle script.
@@
struct clk_hw *E;
@@
(quoted diff) +1 -1
-__clk_get_name(E->clk)
+clk_hw_get_name(E)
Cc Heiko Stuebner <[email protected]>
Cc Sylwester Nawrocki <[email protected]>
Cc Tomasz Figa <[email protected]>
Cc Peter De Schrijver <[email protected]>
Cc Prashant Gaikwad <[email protected]>
Cc Stephen Warren <[email protected]>
Cc Thierry Reding <[email protected]>
Cc Alexandre Courbot <[email protected]>
Cc Tero Kristo <[email protected]>
Cc Ulf Hansson <[email protected]>
Cc Sebastian Hesselbarth <[email protected]>
Cc Andrew Bresticker <[email protected]>
Cc Ezequiel Garcia <[email protected]>
Cc Ralf Baechle <[email protected]>
Cc Kevin Cernekee <[email protected]>
Cc Geert Uytterhoeven <[email protected]>
Cc Ulrich Hecht <[email protected]>
Cc linux-arm-kernel at lists.infradead.org
Cc linux-rockchip at lists.infradead.org
Cc linux-samsung-soc at vger.kernel.org
Cc linux-tegra at vger.kernel.org
Cc linux-omap at vger.kernel.org
Signed-off-by Stephen Boyd <[email protected]>

Quoted 1 line

 drivers/clk/pistachio/clk-pll.c      |  4 ++--

For Pistachio,

Acked-by Andrew Bresticker <[email protected]>