spi: zynq qspi support

These are the last two version patches links.
https://patchwork.ozlabs.org/patch/302945/
https://patchwork.ozlabs.org/patch/264440/

This series adds zynq qspi controller driver in driver model and enabled support on relevent zynq boards and tested the same.

Branch to verify:

$ git clone git://git.denx.de/u-boot-spi.git
$ cd u-boot-spi
$ git checkout -b spi-nor spi-nor

Changes for v3:
- Added driver-model to zynq-qspi driver
- devicetree support on zynq-qspi
- Enabled qspi nodes on relevent board dts files
- Enabled qspi driver on relevent board config files

Changes for v3:
- Fixes with macro's addition

Jagan Teki (16):
spi: Add zynq qspi controller driver
dts: zynq: Add zynq qspi controller nodes
doc: device-tree-bindings: spi: Add zynq qspi info
dts: microzed: Enable zynq qspi controller node
dts: zc702: Enable zynq qspi controller node
dts: zc706: Enable zynq qspi controller node
dts: zc770-xm010: Enable zynq qspi controller node
dts: zed: Enable zynq qspi controller node
configs: Enable legacy SPI flash interface support
zynq-common: Enable zynq qspi controller support
zynq-common: Enable Bank/Extended address register support
configs: zynq: Enable zynq qspi controller
spi: Kconfig: Add Zynq QSPI controller entry
spi: zynq_spi: Add config reg shift named macros
spi: zynq_spi: Rename baudrate divisor mask name
spi: zynq_spi: Store cs value into private data

 arch/arm/dts/zynq-7000.dtsi                    |  12 +
 arch/arm/dts/zynq-microzed.dts                 |   5 +
 arch/arm/dts/zynq-zc702.dts                    |   5 +
 arch/arm/dts/zynq-zc706.dts                    |   5 +
 arch/arm/dts/zynq-zc770-xm010.dts              |   5 +
 arch/arm/dts/zynq-zed.dts                      |   5 +
 configs/zynq_microzed_defconfig                |   2 +
 configs/zynq_zc702_defconfig                   |   2 +
 configs/zynq_zc706_defconfig                   |   2 +
 configs/zynq_zc70x_defconfig                   |   2 +
 configs/zynq_zc770_xm010_defconfig             |   1 +
 configs/zynq_zed_defconfig                     |   2 +
 doc/device-tree-bindings/spi/spi-zynq-qspi.txt |  26 ++
 drivers/spi/Kconfig                            |   9 +
 drivers/spi/Makefile                           |   1 +
 drivers/spi/zynq_qspi.c                        | 622 +++++++++++++++++++++++++
 drivers/spi/zynq_spi.c                         |  20 +-
 include/configs/zynq-common.h                  |  10 +
 18 files changed, 729 insertions(+), 7 deletions(-)
 create mode 100644 doc/device-tree-bindings/spi/spi-zynq-qspi.txt
 create mode 100644 drivers/spi/zynq_qspi.c

1.9.1

Added zynq qspi controller driver for Xilinx Zynq APSOC, this driver is driver-model driven with devicetree support.

=> sf probe
SF: Detected S25FL128S_64K with page size 256 Bytes, erase size 64 KiB, total 16 MiB => mw.b 0x100 0xCC 0x1000000
=> sf update 0x100 0x0 0x1000000
device 0 whole chip
16777216 bytes written, 0 bytes skipped in 59.842s, speed 289262 B/s => sf read 0x3000000 0x0 0x1000000
device 0 whole chip
SF: 16777216 bytes @ 0x0 Read: OK
=> cmp.b 0x3000000 0x100 0x1000000
Total of 16777216 byte(s) were the same

---
 drivers/spi/Makefile    |   1 +
 drivers/spi/zynq_qspi.c | 622 ++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 623 insertions(+)
 create mode 100644 drivers/spi/zynq_qspi.c

index ee88aa1..f59312b 100644
@@ -48,3 +48,4 @@ obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
 obj-$(CONFIG_TI_QSPI) += ti_qspi.o
 obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
 obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
+obj-$(CONFIG_ZYNQ_QSPI) += zynq_qspi.o

1.9.1

This patch adds zynq qspi controller nodes in zynq-7000.dtsi.

---
 arch/arm/dts/zynq-7000.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

index 0b62cb0..84c15b5 100644
@@ -191,6 +191,18 @@
 			#size-cells = <0>;
 		};
 
+		qspi: spi at e000d000 {
+			clock-names = "ref_clk", "pclk";
+			clocks = <&clkc 10>, <&clkc 43>;
+			compatible = "xlnx,zynq-qspi-1.0";
+			status = "disabled";
+			interrupt-parent = <&intc>;
+			interrupts = <0 19 4>;
+			reg = <0xe000d000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		gem0: ethernet at e000b000 {
 			compatible = "cdns,zynq-gem", "cdns,gem";
 			reg = <0xe000b000 0x1000>;

1.9.1

Added device-tree-binding information for zynq qspi controller driver.

---
 doc/device-tree-bindings/spi/spi-zynq-qspi.txt | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)
 create mode 100644 doc/device-tree-bindings/spi/spi-zynq-qspi.txt

new file mode 100644
index 0000000..47472fd
@@ -0,0 +1,26 @@
+Xilinx Zynq QSPI controller Device Tree Bindings
+-------------------------------------------------
+
+Required properties:
+- compatible		: Should be "xlnx,zynq-qspi-1.0".
+- reg			: Physical base address and size of QSPI registers map.
+- interrupts		: Property with a value describing the interrupt
+			  number.
+- interrupt-parent	: Must be core interrupt controller
+- clock-names		: List of input clock names - "ref_clk", "pclk"
+			  (See clock bindings for details).
+- clocks		: Clock phandles (see clock bindings for details).
+
+Optional properties:
+- num-cs		: Number of chip selects used.
+
+Example:
+	qspi at e000d000 {
+		compatible = "xlnx,zynq-qspi-1.0";
+		clock-names = "ref_clk", "pclk";
+		clocks = <&clkc 10>, <&clkc 43>;
+		interrupt-parent = <&intc>;
+		interrupts = <0 19 4>;
+		num-cs = <1>;
+		reg = <0xe000d000 0x1000>;
+	} ;

1.9.1

Enabled zynq qspi controller node for microzed board, verified the same on spansion spi-nor flash.

---
 arch/arm/dts/zynq-microzed.dts | 5 +++++
 1 file changed, 5 insertions(+)

index c373a2c..d5e0050 100644
@@ -14,6 +14,7 @@
 
 	aliases {
 		serial0 = &uart1;
+		spi0 = &qspi;
 	};
 
 	memory {

@@ -21,3 +22,7 @@
 		reg = <0 0x40000000>;
 	};
 };
+
+&qspi {
+	status = "okay";
+};

1.9.1

Enabled zynq qspi controller node for zc702 board.

---
 arch/arm/dts/zynq-zc702.dts | 5 +++++
 1 file changed, 5 insertions(+)

index 6691a8d..4d86960 100644
@@ -17,6 +17,7 @@
 		ethernet0 = &gem0;
 		i2c0 = &i2c0;
 		serial0 = &uart1;
+		spi0 = &qspi;
 	};
 
 	memory {

@@ -380,6 +381,10 @@
 	pinctrl-0 = <&pinctrl_uart1_default>;
 };
 
+&qspi {
+	status = "okay";
+};
+
 &usb0 {
 	status = "okay";
 	dr_mode = "host";

1.9.1

Enabled zynq qspi controller node for zc706 board.

---
 arch/arm/dts/zynq-zc706.dts | 5 +++++
 1 file changed, 5 insertions(+)

index cf7bce4..fc336ea 100644
@@ -17,6 +17,7 @@
 		ethernet0 = &gem0;
 		i2c0 = &i2c0;
 		serial0 = &uart1;
+		spi0 = &qspi;
 	};
 
 	memory {

@@ -301,6 +302,10 @@
 	pinctrl-0 = <&pinctrl_uart1_default>;
 };
 
+&qspi {
+	status = "okay";
+};
+
 &usb0 {
 	status = "okay";
 	dr_mode = "host";

1.9.1

Enabled zynq qspi controller node for zc770-xm010 board.

=> sf probe 0 -- bus0 for selecting spi controller => sf probe 1 -- bus1 for selecting qspi controller

---
 arch/arm/dts/zynq-zc770-xm010.dts | 5 +++++
 1 file changed, 5 insertions(+)

index da3a182..a5c9da5 100644
@@ -17,6 +17,7 @@
 		i2c0 = &i2c0;
 		serial0 = &uart1;
 		spi0 = &spi1;
+		spi1 = &qspi;
 	};
 
 	chosen {

@@ -53,6 +54,10 @@
 	};
 };
 
+&qspi {
+	status = "okay";
+};
+
 &can0 {
 	status = "okay";
 };

1.9.1

Enabled zynq qspi controller node for zed board.

---
 arch/arm/dts/zynq-zed.dts | 5 +++++
 1 file changed, 5 insertions(+)

index 5762576..3630490 100644
@@ -16,6 +16,7 @@
 	aliases {
 		ethernet0 = &gem0;
 		serial0 = &uart1;
+		spi0 = &qspi;
 	};
 
 	memory {

@@ -56,6 +57,10 @@
 	status = "okay";
 };
 
+&qspi {
+	status = "okay";
+};
+
 &usb0 {
 	status = "okay";
 	dr_mode = "host";

1.9.1

Enable legacy spi-flash interface support for boards which supports qspi controller with connected spi-nor flash.

---
 configs/zynq_microzed_defconfig | 1 +
 configs/zynq_zc702_defconfig    | 1 +
 configs/zynq_zc706_defconfig    | 1 +
 configs/zynq_zc70x_defconfig    | 1 +
 configs/zynq_zed_defconfig      | 1 +
 5 files changed, 5 insertions(+)

index c878924..838f8ae 100644
@@ -10,3 +10,4 @@ CONFIG_FIT_SIGNATURE=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y

index 5dde452..1aaa296 100644
@@ -10,3 +10,4 @@ CONFIG_FIT_SIGNATURE=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y

index 0f96d16..4f12fd2 100644
@@ -10,3 +10,4 @@ CONFIG_FIT_SIGNATURE=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y

index 525c538..856b9fd 100644
@@ -10,3 +10,4 @@ CONFIG_FIT_SIGNATURE=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y

index f3c63f9..a49b6bb 100644
@@ -10,3 +10,4 @@ CONFIG_FIT_SIGNATURE=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y

1.9.1

This patch adds support for zynq qspi controller driver on zynq-common.h

---
 include/configs/zynq-common.h | 9 +++++++++
 1 file changed, 9 insertions(+)

index cc72c86..13903ec 100644
@@ -72,6 +72,15 @@
 # define CONFIG_CMD_SF
 #endif
 
+/* QSPI */
+#ifdef CONFIG_ZYNQ_QSPI
+# define CONFIG_SF_DEFAULT_SPEED	30000000
+# define CONFIG_SPI_FLASH_SPANSION
+# define CONFIG_SPI_FLASH_STMICRO
+# define CONFIG_SPI_FLASH_WINBOND
+# define CONFIG_CMD_SF
+#endif
+
 /* NOR */
 #ifndef CONFIG_SYS_NO_FLASH
 # define CONFIG_SYS_FLASH_BASE		0xE2000000

1.9.1

Enabled SPI flash Bank/Extended address register support.

Bank/Extended address registers are used to access the flash which has size > 16MiB in 3-byte addressing.

---
 include/configs/zynq-common.h | 1 +
 1 file changed, 1 insertion(+)

index 13903ec..181d393 100644
@@ -78,6 +78,7 @@
 # define CONFIG_SPI_FLASH_SPANSION
 # define CONFIG_SPI_FLASH_STMICRO
 # define CONFIG_SPI_FLASH_WINBOND
+# define CONFIG_SPI_FLASH_BAR
 # define CONFIG_CMD_SF
 #endif
 

1.9.1

Enable zynq qspi controller driver on respective zynq boards.

---
 configs/zynq_microzed_defconfig    | 1 +
 configs/zynq_zc702_defconfig       | 1 +
 configs/zynq_zc706_defconfig       | 1 +
 configs/zynq_zc70x_defconfig       | 1 +
 configs/zynq_zc770_xm010_defconfig | 1 +
 configs/zynq_zed_defconfig         | 1 +
 6 files changed, 6 insertions(+)

index 838f8ae..c055704 100644
@@ -11,3 +11,4 @@ CONFIG_FIT_SIGNATURE=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SPI_FLASH=y
+CONFIG_ZYNQ_QSPI=y

index 1aaa296..a5812ce 100644
@@ -11,3 +11,4 @@ CONFIG_FIT_SIGNATURE=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SPI_FLASH=y
+CONFIG_ZYNQ_QSPI=y

index 4f12fd2..a2fcaad 100644
@@ -11,3 +11,4 @@ CONFIG_FIT_SIGNATURE=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SPI_FLASH=y
+CONFIG_ZYNQ_QSPI=y

index 856b9fd..20737c0 100644
@@ -11,3 +11,4 @@ CONFIG_FIT_SIGNATURE=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SPI_FLASH=y
+CONFIG_ZYNQ_QSPI=y

index f1fc283..b824342 100644
@@ -12,3 +12,4 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010"
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SPI_FLASH=y
+CONFIG_ZYNQ_QSPI=y

index a49b6bb..163eed1 100644
@@ -11,3 +11,4 @@ CONFIG_FIT_SIGNATURE=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_SPI_FLASH=y
+CONFIG_ZYNQ_QSPI=y

1.9.1

Add Zynq QSPI controller Kconfig entry.

---
 drivers/spi/Kconfig | 9 +++++++++
 1 file changed, 9 insertions(+)

index c84a7b7..facd94d 100644
@@ -123,6 +123,15 @@ config ZYNQ_SPI
 	  access the SPI NOR flash on platforms embedding this Zynq
 	  SPI IP core.
 
+config ZYNQ_QSPI
+	bool "Zynq QSPI driver"
+	depends on ARCH_ZYNQ || TARGET_XILINX_ZYNQMP
+	help
+	  Enable the Zynq Quad-SPI (QSPI) driver. This driver can be
+	  used to access the SPI NOR flash on platforms embedding this
+	  Zynq QSPI IP core. This IP is used to connect the flash in
+	  4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel.
+
 endif # if DM_SPI
 
 config FSL_ESPI

1.9.1

Update the numerical values for baudrate and chipselect with config reg shift named macro's

---
 drivers/spi/zynq_spi.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

index b9cf335..817728c 100644
@@ -28,6 +28,10 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ZYNQ_SPI_IXR_ALL_MASK		0x7F		/* All IXR bits */
 #define ZYNQ_SPI_ENR_SPI_EN_MASK	(1 << 0)	/* SPI Enable */
 
+#define ZYNQ_SPI_CR_BAUD_MAX		8	/* Baud rate divisor max val */
+#define ZYNQ_SPI_CR_BAUD_SHIFT		3	/* Baud rate divisor shift */
+#define ZYNQ_SPI_CR_SS_SHIFT		10	/* Slave select shift */
+
 #define ZYNQ_SPI_FIFO_DEPTH		128
 #ifndef CONFIG_SYS_ZYNQ_SPI_WAIT
 #define CONFIG_SYS_ZYNQ_SPI_WAIT	(CONFIG_SYS_HZ/100)	/* 10 ms */

@@ -139,7 +143,7 @@ static void spi_cs_activate(struct udevice *dev, uint cs)
 	 * xx01	- cs1
 	 * x011 - cs2
 	 */
-	cr |= (~(0x1 << cs) << 10) & ZYNQ_SPI_CR_CS_MASK;
+	cr |= (~(0x1 << cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK;
 	writel(cr, &regs->cr);
 }
 

@@ -256,14 +260,14 @@ static int zynq_spi_set_speed(struct udevice *bus, uint speed)
 		/* Set baudrate x8, if the freq is 0 */
 		baud_rate_val = 0x2;
 	} else if (plat->speed_hz != speed) {
-		while ((baud_rate_val < 8) &&
+		while ((baud_rate_val < ZYNQ_SPI_CR_BAUD_MAX) &&
 				((plat->frequency /
 				(2 << baud_rate_val)) > speed))
 			baud_rate_val++;
 		plat->speed_hz = speed / (2 << baud_rate_val);
 	}
 	confr &= ~ZYNQ_SPI_CR_BRD_MASK;
-	confr |= (baud_rate_val << 3);
+	confr |= (baud_rate_val << ZYNQ_SPI_CR_BAUD_SHIFT);
 
 	writel(confr, &regs->cr);
 	priv->freq = speed;

1.9.1

Rename ZYNQ_SPI_CR_BRD_MASK to ZYNQ_SPI_CR_BAUD_MASK for more readable.

---
 drivers/spi/zynq_spi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

index 817728c..70d7716 100644
@@ -19,7 +19,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ZYNQ_SPI_CR_MSA_MASK		(1 << 15)	/* Manual start enb */
 #define ZYNQ_SPI_CR_MCS_MASK		(1 << 14)	/* Manual chip select */
 #define ZYNQ_SPI_CR_CS_MASK		(0xF << 10)	/* Chip select */
-#define ZYNQ_SPI_CR_BRD_MASK		(0x7 << 3)	/* Baud rate div */
+#define ZYNQ_SPI_CR_BAUD_MASK		(0x7 << 3)	/* Baud rate div */
 #define ZYNQ_SPI_CR_CPHA_MASK		(1 << 2)	/* Clock phase */
 #define ZYNQ_SPI_CR_CPOL_MASK		(1 << 1)	/* Clock polarity */
 #define ZYNQ_SPI_CR_MSTREN_MASK		(1 << 0)	/* Mode select */

@@ -266,7 +266,7 @@ static int zynq_spi_set_speed(struct udevice *bus, uint speed)
 			baud_rate_val++;
 		plat->speed_hz = speed / (2 << baud_rate_val);
 	}
-	confr &= ~ZYNQ_SPI_CR_BRD_MASK;
+	confr &= ~ZYNQ_SPI_CR_BAUD_MASK;
 	confr |= (baud_rate_val << ZYNQ_SPI_CR_BAUD_SHIFT);
 
 	writel(confr, &regs->cr);

1.9.1

Store cs value into private data and use it while activating chipselect instead of passing through function.

---
 drivers/spi/zynq_spi.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

index 70d7716..70ddd7f 100644
@@ -61,6 +61,7 @@ struct zynq_spi_platdata {
 /* zynq spi priv */
 struct zynq_spi_priv {
 	struct zynq_spi_regs *regs;
+	u8 cs;
 	u8 mode;
 	u8 fifo_depth;
 	u32 freq;		/* required frequency */

@@ -128,7 +129,7 @@ static int zynq_spi_probe(struct udevice *bus)
 	return 0;
 }
 
-static void spi_cs_activate(struct udevice *dev, uint cs)
+static void spi_cs_activate(struct udevice *dev)
 {
 	struct udevice *bus = dev->parent;
 	struct zynq_spi_priv *priv = dev_get_priv(bus);

@@ -143,7 +144,7 @@ static void spi_cs_activate(struct udevice *dev, uint cs)
 	 * xx01	- cs1
 	 * x011 - cs2
 	 */
-	cr |= (~(0x1 << cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK;
+	cr |= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK;
 	writel(cr, &regs->cr);
 }
 

@@ -199,8 +200,9 @@ static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen,
 		return -1;
 	}
 
+	priv->cs = slave_plat->cs;
 	if (flags & SPI_XFER_BEGIN)
-		spi_cs_activate(dev, slave_plat->cs);
+		spi_cs_activate(dev);
 
 	while (rx_len > 0) {
 		/* Write the data into TX FIFO - tx threshold is fifo_depth */

1.9.1