armv8/mmu: Clean up TCR programming
PATCH 1/3 armv8/mmu: Clean up TCR programming
From: Thierry Reding <[email protected]>
Use the inner shareable attribute for memory, which makes more sense considering that this code is called when caches are being enabled.
--- arch/arm/include/asm/armv8/mmu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
arch/arm/include/asm/armv8/mmu.h +2 -2
@@ -102,9 +102,9 @@#define TCR_EL2_IPS_BITS (3 << 16)/* 42 bits physical address */ #define TCR_EL3_IPS_BITS (3 << 16)/* 42 bits physical address */ -/* PTWs cacheable, inner/outer WBWA and non-shareable */ +/* PTWs cacheable, inner/outer WBWA and inner shareable */ #define TCR_FLAGS (TCR_TG0_64K | \ - TCR_SHARED_NON | \ + TCR_SHARED_INNER | \ TCR_ORGN_WBWA | \ TCR_IRGN_WBWA | \ TCR_T0SZ(VA_BITS))
Signature · 1 line
2.4.5
PATCH 2/3 armv8/mmu: Set bits marked RES1 in TCR
From: Thierry Reding <[email protected]>
For EL3 and EL2, the documentation says that bits 31 and 23 are reserved but should be written as 1.
For EL1, only bit 23 is not reserved, so only write bit 31 as 1.
--- arch/arm/cpu/armv8/cache_v8.c | 6 +++--- arch/arm/include/asm/armv8/mmu.h | 4 ++++ 2 files changed, 7 insertions(+), 3 deletions(-)
arch/arm/cpu/armv8/cache_v8.c +3 -3
@@ -50,15 +50,15 @@ static void mmu_setup(void) el =current_el ();if (el ==1 ) {set_ttbr_tcr_mair (el, gd->arch.tlb_addr, -TCR_FLAGS |TCR_EL1_IPS_BITS , +TCR_EL1_RSVD |TCR_FLAGS |TCR_EL1_IPS_BITS ,MEMORY_ATTRIBUTES ); }else if (el ==2 ) {set_ttbr_tcr_mair (el, gd->arch.tlb_addr, -TCR_FLAGS |TCR_EL2_IPS_BITS , +TCR_EL2_RSVD |TCR_FLAGS |TCR_EL2_IPS_BITS ,MEMORY_ATTRIBUTES ); }else {set_ttbr_tcr_mair (el, gd->arch.tlb_addr, -TCR_FLAGS |TCR_EL3_IPS_BITS , +TCR_EL3_RSVD |TCR_FLAGS |TCR_EL3_IPS_BITS ,MEMORY_ATTRIBUTES ); }/* enable the mmu */
arch/arm/include/asm/armv8/mmu.h +4 -0
@@ -109,6 +109,10 @@ TCR_IRGN_WBWA | \ TCR_T0SZ(VA_BITS)) +#define TCR_EL1_RSVD (1 << 31) +#define TCR_EL2_RSVD (1 << 31 | 1 << 23) +#define TCR_EL3_RSVD (1 << 31 | 1 << 23) +#ifndef __ASSEMBLY__void set_pgtable_section (u64 *page_table,u64 index,u64 section,u64 memory_type);
Signature · 1 line
2.4.5
PATCH 3/3 armv8/gic: Fix GIC v2 initialization
In reply to Thierry RedingFrom: Thierry Reding <[email protected]>
Initialize all GICD_IGROUPRn registers and set up GICC_CTLR to enable interrupts to the primary CPU. This fixes issues seen after booting a Linux kernel from U-Boot.
--- arch/arm/lib/gic_64.S | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-)
arch/arm/lib/gic_64.S +9 -1
@@ -46,11 +46,19 @@ ENTRY(gic_init_secure) ldr w9, [x0, GICD_TYPER] and w10, w9, #0x1f /* ITLinesNumber */ cbz w10, 1f /* No SPIs */ - add x11, x0, (GICD_IGROUPRn + 4) + add x11, x0, GICD_IGROUPRn mov w9, #~0 /* Config SPIs as Grp1 */ + str w9, [x11], #0x4 0: str w9, [x11], #0x4 sub w10, w10, #0x1 cbnz w10, 0b + + ldr x1, =GICC_BASE /* GICC_CTLR */ + mov w0, #3 /* EnableGrp0 | EnableGrp1 */ + str w0, [x1] + + mov w0, #1 << 7 /* allow NS access to GICC_PMR */ + str w0, [x1, #4] /* GICC_PMR */ #endif 1: ret
Signature · 1 line
2.4.5
PATCH 1/3 armv8/mmu: Clean up TCR programming
In reply to Thierry RedingHello Thierry,
Quoted 8 lines · Thierry Reding
From: Thierry Reding <[email protected]>
Use the inner shareable attribute for memory, which makes more sense considering that this code is called when caches are being enabled.
Cc Albert Aribaud <[email protected]>Cc Marc Zyngier <[email protected]>Signed-off-by Thierry Reding <[email protected]>
Series applied to u-boot-arm/master as a bugfix.
Amicalement,
Signature · 1 line
Albert.