Add Broadcom Northstar Plus Support

Add the documentation for the Broadcom Northstar Plus device tree bindings.

Signed-off-by Jon Mason <[email protected]>

Add a very minimalistic set of Northstar Plus Device Tree files which describes the SoC and the BCM958625 implementation. The perpherials described are:

ARM Cortex A9 CPU
2 8250 UARTs
ARM GIC
PL310 L2 Cache
ARM A9 Global timer

Signed-off-by Kapil Hali <[email protected]>

Signed-off-by Jon Mason <[email protected]>

Add a very minimalistic set of Northstar Plus Device Tree files which describes the SoC and the BCM958625 implementation. The perpherials described are:

ARM Cortex A9 CPU
2 8250 UARTs
ARM GIC
PL310 L2 Cache
ARM A9 Global timer

Signed-off-by Kapil Hali <[email protected]>

Signed-off-by Jon Mason <[email protected]>

---
 arch/arm/boot/dts/Makefile       |   2 +
 arch/arm/boot/dts/bcm-nsp.dtsi   | 105 +++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/bcm958625k.dts |  57 +++++++++++++++++++++
 3 files changed, 164 insertions(+)
 create mode 100644 arch/arm/boot/dts/bcm-nsp.dtsi
 create mode 100644 arch/arm/boot/dts/bcm958625k.dts

arch/arm/boot/dts/Makefile +2 -0

index 246473a..adb5732 100644
@@ -82,6 +82,8 @@ dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
 dtb-$(CONFIG_ARCH_BCM_MOBILE) += \
        bcm28155-ap.dtb \
        bcm21664-garnet.dtb
+dtb-$(CONFIG_ARCH_BCM_NSP) += \
+       bcm958625k.dtb
 dtb-$(CONFIG_ARCH_BERLIN) += \
        berlin2-sony-nsz-gs7.dtb \
        berlin2cd-google-chromecast.dtb \

arch/arm/boot/dts/bcm-nsp.dtsi new file +57 -0

new file mode 100644
index 0000000..77f9bfc
@@ -0,0 +1,105 @@
+/*
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the
+ *      distribution.
+ *    * Neither the name of Broadcom Corporation nor the names of its
+ *      contributors may be used to endorse or promote products derived
+ *      from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#include "skeleton.dtsi"
+
+/ {
+       compatible = "brcm,nsp";
+       model = "Broadcom Northstar Plus SoC";
+       interrupt-parent = <&gic>;
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu at 0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a9";
+                       next-level-cache = <&L2>;
+                       reg = <0x0>;
+               };
+       };
+
+       clocks {
+               #address-cells = <1>;
+               #size-cells = <1>;

arch/arm/boot/dts/bcm-nsp.dtsi new file +38 -0

+               compatible = "ns16550a";
+               reg = <0x18000300 0x100>;
+               interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+               clock-frequency = <62499840>;
+               status = "disabled";
+       };
+
+       uart1: serial at 18000400 {
+               compatible = "ns16550a";
+               reg = <0x18000400 0x100>;
+               interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+               clock-frequency = <62499840>;
+               status = "disabled";
+       };
+
+       gic: interrupt-controller at 19021000 {
+               compatible = "arm,cortex-a9-gic";
+               #interrupt-cells = <3>;
+               #address-cells = <0>;
+               interrupt-controller;
+               reg = <0x19021000 0x1000>,
+                     <0x19020100 0x100>;
+       };
+
+       L2: l2-cache {
+               compatible = "arm,pl310-cache";
+               reg = <0x19022000 0x1000>;
+               cache-unified;
+               cache-level = <2>;
+       };
+
+       timer at 19020200 {
+               compatible = "arm,cortex-a9-global-timer";
+               reg = <0x19020200 0x100>;
+               interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&periph_clk>;
+       };
+};

arch/arm/boot/dts/bcm958625k.dts new file +57 -1

new file mode 100644
index 0000000..16303db
@@ -0,0 +1,57 @@
+/*
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the
+ *      distribution.
+ *    * Neither the name of Broadcom Corporation nor the names of its
+ *      contributors may be used to endorse or promote products derived
+ *      from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+#include "bcm-nsp.dtsi"
+
+/ {
+       model = "NorthStar Plus SVK (BCM958625K)";
+       compatible = "brcm,bcm58625", "brcm,nsp";
+
+       aliases {
+               serial0 = &uart0;
+               serial1 = &uart1;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+};
+
+&uart0 {
+       status = "okay";
+};
+
+&uart1 {
+       status = "okay";
+};
--

1.9.1

Quoted 13 lines · Jon Mason

Add a very minimalistic set of Northstar Plus Device Tree files which describes the SoC and the BCM958625 implementation. The perpherials described are:

ARM Cortex A9 CPU
2 8250 UARTs
ARM GIC
PL310 L2 Cache
ARM A9 Global timer

Signed-off-by Kapil Hali <[email protected]>

Signed-off-by Jon Mason <[email protected]>

---

Quoted 7 lines

arch/arm/boot/dts/bcm-nsp.dtsi new file +7 -0

+       clocks {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+
+               periph_clk: periph_clk {
+                       compatible = "fixed-clock";

arch/arm/boot/dts/bcm-nsp.dtsi line 67

Quoted 6 lines

arch/arm/boot/dts/bcm-nsp.dtsi new file +6 -0

+                       #clock-cells = <0>;
+                       clock-frequency = <500000000>;
+               };
+       };
+
+       uart0: serial at 18000300 {

All these devices should go under a bus node.

Broadcom Northstar Plus family of SoCs are used for switching control and management applications as well as residential router/gateway applications. The SoC features dual core Cortex A9 ARM CPUs, integrating several peripheral interfaces including multiple Gigabit Ethernet PHYs, DDR3 memory, PCIE Gen-2, USB 2.0 and USB 3.0, serial and NAND flash, SATA and several other IO controllers.

Signed-off-by Kapil Hali <[email protected]>

Signed-off-by Jon Mason <[email protected]>

Add the Broadcom Northstar Plus SoC to the multi_v7_defconfig

Signed-off-by Jon Mason <[email protected]>

Modify the iProc MAINTAINER to cover the Nortstar Plus SoCs, and add me to the list of people responsible for it. Since iProc is a family of SoCs that includes more than just Cygnus (i.e., Northstar (BCM5301X), Northstar Plus, Northstar 2, and a number of other platforms), remove it from the title to avoid any future confusion.

Signed-off-by Jon Mason <[email protected]>

Acked-by Scott Branden <[email protected]>

Changes in version 2 incorporate Olof's comments regarding:
* the removal of all "Reviewed-by" lines not occurring on external mailing lists
* reordering of s-o-b lines
* modification of the device tree file to use labels when enabling
* increated description of the modification to the MAINTAINERS entry

Also, modifying the "to" and "cc" recepients so that everyone is receving all of the patches.

--

This patch series adds support for the Broadcom Northstar Plus family of SoCs. NSP is a Cortex A9 based SoC under the Broadcom iProc family.

Jon Mason (5):
dt-bindings: Create Documentation for NSP DT bindings
ARM: NSP: add minimal Northstar Plus device tree
ARM: NSP: Add basic support for Broadcom Northstar Plus SoC
ARM: multi_v7_defconfig: Add NSP to defconfig
MAINTAINERS: add entry for the Broadcom Northstar Plus SoCs

  .../devicetree/bindings/arm/bcm/brcm,nsp.txt       |  34 +++++++
  MAINTAINERS                                        |  12 ++-
  arch/arm/boot/dts/Makefile                         |   2 +
  arch/arm/boot/dts/bcm-nsp.dtsi                     | 105 +++++++++++++++++++++
  arch/arm/boot/dts/bcm958625k.dts                   |  57 +++++++++++
  arch/arm/configs/multi_v7_defconfig                |   1 +
  arch/arm/mach-bcm/Kconfig                          |  14 +++
  arch/arm/mach-bcm/Makefile                         |   5 +-
  arch/arm/mach-bcm/bcm_nsp.c                        |  25 +++++
  9 files changed, 252 insertions(+), 3 deletions(-)

create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp.txt create mode 100644 arch/arm/boot/dts/bcm-nsp.dtsi
create mode 100644 arch/arm/boot/dts/bcm958625k.dts
create mode 100644 arch/arm/mach-bcm/bcm_nsp.c