Patch "clk: pistachio: Fix override of clk-pll settings from boot loader" has been added to the 4.1-stable tree

This is a note to let you know that I've just added the patch titled

clk: pistachio: Fix override of clk-pll settings from boot loader

to the 4.1-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
clk-pistachio-fix-override-of-clk-pll-settings-from-boot-loader.patch
and it can be found in the queue-4.1 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From: Zdenko Pulitika <[email protected]>
Date: Wed, 26 Aug 2015 17:11:38 +0100
Subject: clk: pistachio: Fix override of clk-pll settings from boot loader

From: Zdenko Pulitika <[email protected]>

commit e53f21c761d141bbcbce06e9ddab3b4e0a828f2c upstream.

PLL enable callbacks are overriding PLL mode (int/frac) and Noise reduction (on/off) settings set by the boot loader which results in the incorrect clock rate.

PLL mode and noise reduction are defined by the DSMPD and DACPD bits of the PLL control register. PLL .enable() callbacks enable PLL by deasserting all power-down bits of the PLL control register, including DSMPD and DACPD bits, which is not necessary since these bits don't actually enable/disable PLL.

This commit fixes the problem by removing DSMPD and DACPD bits from the "PLL enable" mask.

---
 drivers/clk/pistachio/clk-pll.c |    5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

@@ -115,8 +115,7 @@ static int pll_gf40lp_frac_enable(struct
 	u32 val;
 
 	val = pll_readl(pll, PLL_CTRL3);
-	val &= ~(PLL_FRAC_CTRL3_PD | PLL_FRAC_CTRL3_DACPD |
-		 PLL_FRAC_CTRL3_DSMPD | PLL_FRAC_CTRL3_FOUTPOSTDIVPD |
+	val &= ~(PLL_FRAC_CTRL3_PD | PLL_FRAC_CTRL3_FOUTPOSTDIVPD |
 		 PLL_FRAC_CTRL3_FOUT4PHASEPD | PLL_FRAC_CTRL3_FOUTVCOPD);
 	pll_writel(pll, val, PLL_CTRL3);
 

@@ -233,7 +232,7 @@ static int pll_gf40lp_laint_enable(struc
 	u32 val;
 
 	val = pll_readl(pll, PLL_CTRL1);
-	val &= ~(PLL_INT_CTRL1_PD | PLL_INT_CTRL1_DSMPD |
+	val &= ~(PLL_INT_CTRL1_PD |
 		 PLL_INT_CTRL1_FOUTPOSTDIVPD | PLL_INT_CTRL1_FOUTVCOPD);
 	pll_writel(pll, val, PLL_CTRL1);
 

Patches currently in stable-queue which might be from [email protected] are

queue-4.1/clk-pistachio-fix-override-of-clk-pll-settings-from-boot-loader.patch