Patch "MIPS: CPS: use 32b accesses to GCRs" has been added to the 4.2-stable tree

This is a note to let you know that I've just added the patch titled

MIPS: CPS: use 32b accesses to GCRs

to the 4.2-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
mips-cps-use-32b-accesses-to-gcrs.patch
and it can be found in the queue-4.2 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From: Paul Burton <[email protected]>
Date: Wed, 5 Aug 2015 15:42:35 -0700
Subject: MIPS: CPS: use 32b accesses to GCRs

From: Paul Burton <[email protected]>

commit 90996511187d6282db6d02d3f97006b4dbb5c457 upstream.

Commit b677bc03d757 ("MIPS: cps-vec: Use macros for various arithmetics and memory operations") replaced various load & store instructions through cps-vec.S with the PTR_L & PTR_S macros. However it was somewhat overzealous in doing so for CM GCR accesses, since the bit width of the CM doesn't necessarily match that of the CPU. The registers accessed (GCR_CL_COHERENCE & GCR_CL_ID) should be safe to simply always access using 32b instructions, so do so in order to avoid issues when using a 32b CM with a 64b CPU.

Patchwork: https://patchwork.linux-mips.org/patch/10864/

---
 arch/mips/kernel/cps-vec.S |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

@@ -152,7 +152,7 @@ dcache_done:
 
 	/* Enter the coherent domain */
 	li	t0, 0xff
-	PTR_S	t0, GCR_CL_COHERENCE_OFS(v1)
+	sw	t0, GCR_CL_COHERENCE_OFS(v1)
 	ehb
 
 	/* Jump to kseg0 */

@@ -302,7 +302,7 @@ LEAF(mips_cps_boot_vpes)
 	PTR_L	t0, 0(t0)
 
 	/* Calculate a pointer to this cores struct core_boot_config */
-	PTR_L	t0, GCR_CL_ID_OFS(t0)
+	lw	t0, GCR_CL_ID_OFS(t0)
 	li	t1, COREBOOTCFG_SIZE
 	mul	t0, t0, t1
 	PTR_LA	t1, mips_cps_core_bootcfg

Patches currently in stable-queue which might be from [email protected] are

queue-4.2/mips-cps-use-32b-accesses-to-gcrs.patch