add armv7 architecture support

From: Amruta Zende <[email protected]>

Signed-off-by Amruta Zende <[email protected]>

Signed-off-by David Hunt <[email protected]>

---
MAINTAINERS | 5 +

 config/defconfig_arm-native-linuxapp-gcc           |   56 ++++
 .../common/include/arch/arm/rte_atomic.h           |  269 ++++++++++++++++++++
 .../common/include/arch/arm/rte_byteorder.h        |  146 +++++++++++
 .../common/include/arch/arm/rte_cpuflags.h         |  138 ++++++++++
 .../common/include/arch/arm/rte_cycles.h           |   77 ++++++
 .../common/include/arch/arm/rte_memcpy.h           |  101 ++++++++
 .../common/include/arch/arm/rte_prefetch.h         |   64 +++++
 .../common/include/arch/arm/rte_rwlock.h           |   70 +++++
 .../common/include/arch/arm/rte_spinlock.h         |  116 +++++++++

 lib/librte_eal/common/include/arch/arm/rte_vect.h  |   37 +++
 lib/librte_eal/linuxapp/Makefile                   |    3 +
 lib/librte_eal/linuxapp/arm_pmu/Makefile           |   52 ++++
 lib/librte_eal/linuxapp/arm_pmu/rte_enable_pmu.c   |   83 ++++++
 mk/arch/arm/rte.vars.mk                            |   58 +++++
 mk/machine/armv7-a/rte.vars.mk                     |   63 +++++
 mk/toolchain/gcc/rte.vars.mk                       |    8 +-
 17 files changed, 1343 insertions(+), 3 deletions(-)
 create mode 100644 config/defconfig_arm-native-linuxapp-gcc
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_atomic.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_byteorder.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_cpuflags.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_cycles.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_memcpy.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_prefetch.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_rwlock.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_spinlock.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_vect.h
 create mode 100755 lib/librte_eal/linuxapp/arm_pmu/Makefile
 create mode 100644 lib/librte_eal/linuxapp/arm_pmu/rte_enable_pmu.c
 create mode 100644 mk/arch/arm/rte.vars.mk
 create mode 100644 mk/machine/armv7-a/rte.vars.mk

MAINTAINERS +0 -0

index 080a8e8..9d99d53 100644

new file mode 100644
index 0000000..159aa36

config/defconfig_arm-native-linuxapp-gcc new file +11 -0

@@ -0,0 +1,56 @@
+#   BSD LICENSE
+#
+#   Copyright(c) 2015 Intel Corporation. All rights reserved.
+#
[...]
+#
+
+#include "common_linuxapp"
+
+CONFIG_RTE_MACHINE="armv7-a"
+
+CONFIG_RTE_ARCH="arm"

config/defconfig_arm-native-linuxapp-gcc new file +4 -0

+CONFIG_RTE_IXGBE_INC_VECTOR=n
+CONFIG_RTE_LIBRTE_VIRTIO_PMD=n
+CONFIG_RTE_LIBRTE_CXGBE_PMD=n
+

lib/librte_eal/common/include/arch/arm/rte_atomic.h new file +37 -0

new file mode 100644
index 0000000..2a7339c
@@ -0,0 +1,269 @@
+/*-
+ *   BSD LICENSE
+ *
+ *   Copyright(c) 2015 Intel Corporation. All rights reserved.
+ *
[...]
+ */
+
+#ifndef _RTE_ATOMIC_ARM32_H_
+#define _RTE_ATOMIC_ARM32_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_atomic.h"
+
+/**
+ * @file
+ * Atomic Operations
+ *
+ * This file defines a API for atomic operations.
+ */
+
+/**
+ * General memory barrier.
+ *
+ * Guarantees that the LOAD and STORE operations generated before the
+ * barrier occur before the LOAD and STORE operations generated after.
+ */
+#define	rte_mb()  { __sync_synchronize(); }
+
+/**
+ * Write memory barrier.
+ *
+ * Guarantees that the STORE operations generated before the barrier
+ * occur before the STORE operations generated after.
+ */

lib/librte_eal/common/include/arch/arm/rte_atomic.h new file +68 -0

+}
+
+static inline void
+rte_atomic16_inc(rte_atomic16_t *v)
+{
+	rte_atomic16_add(v, 1);
+}
+
+static inline void
+rte_atomic16_dec(rte_atomic16_t *v)
+{
+	rte_atomic16_sub(v, 1);
+}
+
+static inline int rte_atomic16_inc_and_test(rte_atomic16_t *v)
+{
+	return (__sync_add_and_fetch(&v->cnt, 1) == 0);
+}
+
+static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v)
+{
+	return (__sync_sub_and_fetch(&v->cnt, 1) == 0);
+}
+
+static inline int rte_atomic16_test_and_set(rte_atomic16_t *v)
+{
+	return rte_atomic16_cmpset((volatile uint16_t *)&v->cnt, 0, 1);
+}
+
+
+/*------------------------- 32 bit atomic operations -------------------------*/
+
+static inline int
+rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src)
+{
+	return __sync_bool_compare_and_swap(dst, exp, src);
+}
+
+static inline void
+rte_atomic32_inc(rte_atomic32_t *v)
+{
+	rte_atomic32_add(v, 1);
+}
+
+static inline void
+rte_atomic32_dec(rte_atomic32_t *v)
+{
+	rte_atomic32_sub(v, 1);
+}
+
+static inline int rte_atomic32_inc_and_test(rte_atomic32_t *v)
+{
+	return (__sync_add_and_fetch(&v->cnt, 1) == 0);
+}
+
+static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)
+{
+	return (__sync_sub_and_fetch(&v->cnt, 1) == 0);
+}
+
+static inline int rte_atomic32_test_and_set(rte_atomic32_t *v)
+{
+	return rte_atomic32_cmpset((volatile uint32_t *)&v->cnt, 0, 1);
+}
+
+/*------------------------- 64 bit atomic operations -------------------------*/
+
+static inline int

lib/librte_eal/common/include/arch/arm/rte_atomic.h new file +110 -0

+#else
+	int success = 0;
+	uint64_t tmp;
+
+	while (success == 0) {
+		tmp = v->cnt;
+		success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
+				tmp, 0);
+	}
+#endif
+}
+
+static inline int64_t
+rte_atomic64_read(rte_atomic64_t *v)
+{
+#ifdef __LP64__
+	return v->cnt;
+#else
+	int success = 0;
+	uint64_t tmp;
+
+	while (success == 0) {
+		tmp = v->cnt;
+		/* replace the value by itself */
+		success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
+				tmp, tmp);
+	}
+	return tmp;
+#endif
+}
+
+static inline void
+rte_atomic64_set(rte_atomic64_t *v, int64_t new_value)
+{
+#ifdef __LP64__
+	v->cnt = new_value;
+#else
+	int success = 0;
+	uint64_t tmp;
+
+	while (success == 0) {
+		tmp = v->cnt;
+		success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
+				tmp, new_value);
+	}
+#endif
+}
+
+static inline void
+rte_atomic64_add(rte_atomic64_t *v, int64_t inc)
+{
+	__sync_fetch_and_add(&v->cnt, inc);
+}
+
+static inline void
+rte_atomic64_sub(rte_atomic64_t *v, int64_t dec)
+{
+	__sync_fetch_and_sub(&v->cnt, dec);
+}
+
+static inline void
+rte_atomic64_inc(rte_atomic64_t *v)
+{
+	rte_atomic64_add(v, 1);
+}
+
+static inline void
+rte_atomic64_dec(rte_atomic64_t *v)
+{
+	rte_atomic64_sub(v, 1);
+}
+
+static inline int64_t
+rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)
+{
+	return __sync_add_and_fetch(&v->cnt, inc);
+}
+
+static inline int64_t
+rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)
+{
+	return __sync_sub_and_fetch(&v->cnt, dec);
+}
+
+static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)
+{
+	return rte_atomic64_add_return(v, 1) == 0;
+}
+
+static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)
+{
+	return rte_atomic64_sub_return(v, 1) == 0;
+}
+
+static inline int rte_atomic64_test_and_set(rte_atomic64_t *v)
+{
+	return rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);
+}
+
+static inline void rte_atomic64_clear(rte_atomic64_t *v)
+{
+	rte_atomic64_set(v, 0);
+}
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_ATOMIC_ARM32_H_ */

lib/librte_eal/common/include/arch/arm/rte_byteorder.h new file +21 -0

new file mode 100644
index 0000000..effbd62
@@ -0,0 +1,146 @@
+/*-
+ *   BSD LICENSE
+ *
+ *   Copyright (C) IBM Corporation 2014. All rights reserved.
+ *   Copyright(c) 2015 Intel Corporation. All rights reserved.
+ *
[...]
+ */
+
+/* Inspired from FreeBSD src/sys/powerpc/include/endian.h
+ * Copyright (c) 1987, 1991, 1993
+ * The Regents of the University of California.  All rights reserved.
+*/
+
+#ifndef _RTE_BYTEORDER_ARM32_H_
+#define _RTE_BYTEORDER_ARM32_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_byteorder.h"

lib/librte_eal/common/include/arch/arm/rte_byteorder.h new file +90 -0

+}
+
+/*
+ * An architecture-optimized byte swap for a 32-bit value.
+ *
+ * Do not use this function directly. The preferred function is rte_bswap32().
+ */
+static inline uint32_t
+rte_arch_bswap32(uint32_t _x)
+{
+	return __builtin_bswap32(_x);
+}
+
+/*
+ * An architecture-optimized byte swap for a 64-bit value.
+ *
+  * Do not use this function directly. The preferred function is rte_bswap64().
+ */
+/* 64-bit mode */
+static inline uint64_t
+rte_arch_bswap64(uint64_t _x)
+{
+	return __builtin_bswap64(_x);
+}
+
+#ifndef RTE_FORCE_INTRINSICS
+#define rte_bswap16(x) ((uint16_t)(__builtin_constant_p(x) ?		\
+			rte_constant_bswap16(x) :		\
+			rte_arch_bswap16(x)))
+
+#define rte_bswap32(x) ((uint32_t)(__builtin_constant_p(x) ?		\
+			rte_constant_bswap32(x) :		\
+			rte_arch_bswap32(x)))
+
+#define rte_bswap64(x) ((uint64_t)(__builtin_constant_p(x) ?		\
+			rte_constant_bswap64(x) :		\
+			rte_arch_bswap64(x)))
+#else
+		/*
+		 * __builtin_bswap16 is only available gcc 4.8 and upwards
+		 */
+#if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ < 8)
+#define rte_bswap16(x) ((uint16_t)(__builtin_constant_p(x) ?		\
+			rte_constant_bswap16(x) :		\
+			rte_arch_bswap16(x)))
+#endif
+#endif
+
+#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
+
+#define rte_cpu_to_le_16(x) (x)
+#define rte_cpu_to_le_32(x) (x)
+#define rte_cpu_to_le_64(x) (x)
+
+#define rte_cpu_to_be_16(x) rte_bswap16(x)
+#define rte_cpu_to_be_32(x) rte_bswap32(x)
+#define rte_cpu_to_be_64(x) rte_bswap64(x)
+
+#define rte_le_to_cpu_16(x) (x)
+#define rte_le_to_cpu_32(x) (x)
+#define rte_le_to_cpu_64(x) (x)
+
+#define rte_be_to_cpu_16(x) rte_bswap16(x)
+#define rte_be_to_cpu_32(x) rte_bswap32(x)
+#define rte_be_to_cpu_64(x) rte_bswap64(x)
+
+#else /* RTE_BIG_ENDIAN */
+
+#define rte_cpu_to_le_16(x) rte_bswap16(x)
+#define rte_cpu_to_le_32(x) rte_bswap32(x)
+#define rte_cpu_to_le_64(x) rte_bswap64(x)
+
+#define rte_cpu_to_be_16(x) (x)
+#define rte_cpu_to_be_32(x) (x)
+#define rte_cpu_to_be_64(x) (x)
+
+#define rte_le_to_cpu_16(x) rte_bswap16(x)
+#define rte_le_to_cpu_32(x) rte_bswap32(x)
+#define rte_le_to_cpu_64(x) rte_bswap64(x)
+
+#define rte_be_to_cpu_16(x) (x)
+#define rte_be_to_cpu_32(x) (x)
+#define rte_be_to_cpu_64(x) (x)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_BYTEORDER_ARM32_H_ */

lib/librte_eal/common/include/arch/arm/rte_cpuflags.h new file +23 -0

new file mode 100644
index 0000000..411ca37
@@ -0,0 +1,138 @@
+/*-
+ *   BSD LICENSE
+ *
+ *   Copyright (C) IBM Corporation 2014. All rights reserved.
+ *   Copyright(c) 2015 Intel Corporation. All rights reserved.
+ *
[...]
+ */
+
+#ifndef _RTE_CPUFLAGS_ARM32_H_
+#define _RTE_CPUFLAGS_ARM32_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <elf.h>
+#include <fcntl.h>
+#include <assert.h>
+#include <unistd.h>
+#include <string.h>
+
+#include "generic/rte_cpuflags.h"
+

lib/librte_eal/common/include/arch/arm/rte_cpuflags.h new file +25 -0

+	/* The last item */
+	RTE_CPUFLAG_NUMFLAGS,/**< This should always be the last! */
+};
+
+static const struct feature_entry cpu_feature_table[] = {
+	FEAT_DEF(FP, 0x00000001, 0, REG_HWCAP,  0)
+	FEAT_DEF(ASIMD, 0x00000001, 0, REG_HWCAP,  1)
+	FEAT_DEF(EVTSTRM, 0x00000001, 0, REG_HWCAP,  2)
+	FEAT_DEF(AARCH64, 0x00000001, 0, AARCH_MODE, 3)
+	FEAT_DEF(AARCH32, 0x00000001, 0, AARCH_MODE, 4)
+};
+
+/*
+ * Read AUXV software register and get cpu features for Power
+ */
+static inline void
+rte_cpu_get_features(__attribute__((unused)) uint32_t leaf,
+	__attribute__((unused)) uint32_t subleaf, cpuid_registers_t out)
+{
+	int auxv_fd;
+	Elf32_auxv_t auxv;
+
+	auxv_fd = open("/proc/self/auxv", O_RDONLY);
+	assert(auxv_fd);
+	while (read(auxv_fd, &auxv,

lib/librte_eal/common/include/arch/arm/rte_cpuflags.h new file +35 -0

+		}
+	}
+}
+
+/*
+ * Checks if a particular flag is available on current machine.
+ */
+static inline int
+rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
+{
+	const struct feature_entry *feat;
+	cpuid_registers_t regs = {0};
+
+	if (feature >= RTE_CPUFLAG_NUMFLAGS)
+		/* Flag does not match anything in the feature tables */
+		return -ENOENT;
+
+	feat = &cpu_feature_table[feature];
+
+	if (!feat->leaf)
+		/* This entry in the table wasn't filled out! */
+		return -EFAULT;
+
+	/* get the cpuid leaf containing the desired feature */
+	rte_cpu_get_features(feat->leaf, feat->subleaf, regs);
+
+	/* check if the feature is enabled */
+	return (regs[feat->reg] >> feat->bit) & 1;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_CPUFLAGS_ARM32_H_ */

lib/librte_eal/common/include/arch/arm/rte_cycles.h new file +25 -0

new file mode 100644
index 0000000..140d1bb
@@ -0,0 +1,77 @@
+/*-
+ *   BSD LICENSE
+ *
+ *   Copyright (C) IBM Corporation 2014. All rights reserved.
+ *   Copyright(c) 2015 Intel Corporation. All rights reserved.
[...]
+ */
+
+#ifndef _RTE_CYCLES_ARM32_H_
+#define _RTE_CYCLES_ARM32_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_cycles.h"
+
+/**
+ * Read the time base register.
+ *
+ * @return
+ *   The time base for this lcore.
+ */
+static inline uint64_t
+rte_rdtsc(void)
+{

lib/librte_eal/common/include/arch/arm/rte_cycles.h new file +16 -0

+
+static inline uint64_t
+rte_rdtsc_precise(void)
+{
+	asm volatile("isb sy" : : : );
+	return rte_rdtsc();
+}
+
+static inline uint64_t
+rte_get_tsc_cycles(void) { return rte_rdtsc(); }
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_CYCLES_ARM32_H_ */

lib/librte_eal/common/include/arch/arm/rte_memcpy.h new file +60 -0

new file mode 100644
index 0000000..341052e
@@ -0,0 +1,101 @@
+/*-
+ *   BSD LICENSE
+ *
+ *   Copyright (C) IBM Corporation 2014. All rights reserved.
+ *   Copyright(c) 2015 Intel Corporation. All rights reserved.
+ *
[...]
+ */
+
+#ifndef _RTE_MEMCPY_ARM32_H_
+#define _RTE_MEMCPY_ARM32_H_
+
+#include <stdint.h>
+#include <string.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_memcpy.h"
+
+
+
+static inline void
+rte_mov16(uint8_t *dst, const uint8_t *src)
+{
+	memcpy(dst, src, 16);
+}
+
+static inline void
+rte_mov32(uint8_t *dst, const uint8_t *src)
+{
+	memcpy(dst, src, 32);
+}
+
+static inline void
+rte_mov48(uint8_t *dst, const uint8_t *src)
+{
+	memcpy(dst, src, 48);
+}
+
+static inline void
+rte_mov64(uint8_t *dst, const uint8_t *src)
+{
+	memcpy(dst, src, 64);
+}
+
+static inline void
+rte_mov128(uint8_t *dst, const uint8_t *src)
+{
+	memcpy(dst, src, 128);
+}
+
+static inline void
+rte_mov256(uint8_t *dst, const uint8_t *src)
+{
+	memcpy(dst, src, 256);
+}
+
+static inline void *
+rte_memcpy(void *dst, const void *src, size_t n)

lib/librte_eal/common/include/arch/arm/rte_memcpy.h new file +6 -0

+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_MEMCPY_ARM32_H_ */

lib/librte_eal/common/include/arch/arm/rte_prefetch.h new file +23 -0

new file mode 100644
index 0000000..47be3b8
@@ -0,0 +1,64 @@
+/*-
+ *   BSD LICENSE
+ *
+ *   Copyright(c) 2015 Intel Corporation. All rights reserved.
+ *
[...]
+ */
+
+#ifndef _RTE_PREFETCH_ARM32_H_
+#define _RTE_PREFETCH_ARM32_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_prefetch.h"
+
+static inline void
+rte_prefetch0(const volatile void __attribute__((unused)) *p)
+{
+	asm volatile("nop");
+}
+
+static inline void

lib/librte_eal/common/include/arch/arm/rte_prefetch.h new file +6 -0

+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_PREFETCH_ARM32_H_ */

lib/librte_eal/common/include/arch/arm/rte_rwlock.h new file +45 -0

new file mode 100644
index 0000000..87349b9
@@ -0,0 +1,70 @@
+/*-
+ *   BSD LICENSE
+ *
+ *   Copyright(c) 2015 Intel Corporation. All rights reserved.
+ *
[...]
+ */
+
+#ifndef _RTE_RWLOCK_ARM32_H_
+#define _RTE_RWLOCK_ARM32_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_rwlock.h"
+
+static inline void
+rte_rwlock_read_lock_tm(rte_rwlock_t *rwl)
+{
+	rte_rwlock_read_lock(rwl);
+}
+
+static inline void
+rte_rwlock_read_unlock_tm(rte_rwlock_t *rwl)
+{
+	rte_rwlock_read_unlock(rwl);
+}
+
+static inline void
+rte_rwlock_write_lock_tm(rte_rwlock_t *rwl)
+{
+	rte_rwlock_write_lock(rwl);
+}
+
+static inline void
+rte_rwlock_write_unlock_tm(rte_rwlock_t *rwl)
+{
+	rte_rwlock_write_unlock(rwl);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_RWLOCK_ARM32_H_ */

lib/librte_eal/common/include/arch/arm/rte_spinlock.h new file +91 -0

new file mode 100644
index 0000000..45d01a0
@@ -0,0 +1,116 @@
+/*-
+ *   BSD LICENSE
+ *
+ *   Copyright (C) IBM Corporation 2014. All rights reserved.
+ *   Copyright(c) 2015 Intel Corporation. All rights reserved.
+ *
[...]
+ */
+
+#ifndef _RTE_SPINLOCK_ARM32_H_
+#define _RTE_SPINLOCK_ARM32_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rte_common.h>
+
+#include "generic/rte_spinlock.h"
+
+
+#ifndef RTE_FORCE_INTRINSICS
+
+static inline void
+rte_spinlock_lock(rte_spinlock_t *sl)
+{
+	while (__sync_lock_test_and_set(&sl->locked, 1))
+		while (sl->locked)
+			rte_pause();
+}
+
+static inline void
+rte_spinlock_unlock(rte_spinlock_t *sl)
+{
+	__sync_lock_release(&sl->locked);
+}
+
+static inline int
+rte_spinlock_trylock(rte_spinlock_t *sl)
+{
+	return (__sync_lock_test_and_set(&sl->locked, 1) == 0);
+}
+
+#endif
+
+static inline int
+rte_tm_supported(void)
+{
+	return 0;
+}
+
+static inline void
+rte_spinlock_lock_tm(rte_spinlock_t *sl)
+{
+	rte_spinlock_lock(sl); /* fall-back */
+}
+
+static inline int
+rte_spinlock_trylock_tm(rte_spinlock_t *sl)
+{
+	return rte_spinlock_trylock(sl);
+}
+
+static inline void
+rte_spinlock_unlock_tm(rte_spinlock_t *sl)
+{
+	rte_spinlock_unlock(sl);
+}
+
+static inline void
+rte_spinlock_recursive_lock_tm(rte_spinlock_recursive_t *slr)
+{
+	rte_spinlock_recursive_lock(slr); /* fall-back */
+}
+
+static inline void
+rte_spinlock_recursive_unlock_tm(rte_spinlock_recursive_t *slr)
+{
+	rte_spinlock_recursive_unlock(slr);
+}
+
+static inline int
+rte_spinlock_recursive_trylock_tm(rte_spinlock_recursive_t *slr)
+{
+	return rte_spinlock_recursive_trylock(slr);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_SPINLOCK_ARM32_H_ */

lib/librte_eal/common/include/arch/arm/rte_vect.h new file +12 -0

new file mode 100644
index 0000000..5994efd
@@ -0,0 +1,37 @@
+/*-
+ *   BSD LICENSE
+ *
+ *   Copyright(c) 2015 Intel Corporation. All rights reserved.
+ *
[...]
+ */
+
+#ifndef _RTE_VECT_ARM32_H_
+#define _RTE_VECT_ARM32_H_
+
+
+#endif /* _RTE_VECT_ARM32_H_*/

lib/librte_eal/linuxapp/Makefile +3 -0

index d9c5233..549f2ed 100644
@@ -35,6 +35,9 @@ ifeq ($(CONFIG_RTE_EAL_IGB_UIO),y)
 DIRS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += igb_uio
 endif
 DIRS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal
+ifeq ($(CONFIG_RTE_ARCH), "arm")
+DIRS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += arm_pmu
+endif
 ifeq ($(CONFIG_RTE_KNI_KMOD),y)
 DIRS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += kni
 endif

lib/librte_eal/linuxapp/arm_pmu/Makefile new file +27 -0

new file mode 100755
index 0000000..0adb23b
@@ -0,0 +1,52 @@
+#   BSD LICENSE
+#
+#   Copyright(c) 2015 Intel Corporation. All rights reserved.
+#
[...]
+
+include $(RTE_SDK)/mk/rte.vars.mk
+
+#
+# module name and path
+#
+MODULE = arm_pmu
+MODULE_PATH = drivers/net/arm_pmu
+
+#
+# CFLAGS
+#
+MODULE_CFLAGS += -I$(SRCDIR) --param max-inline-insns-single=100
+MODULE_CFLAGS += -I$(RTE_OUTPUT)/include
+MODULE_CFLAGS += -Winline -Wall -Werror
+MODULE_CFLAGS += -include $(RTE_OUTPUT)/include/rte_config.h
+
+#
+# all source are stored in SRCS-y
+#
+SRCS-y := rte_enable_pmu.c
+
+include $(RTE_SDK)/mk/rte.module.mk

lib/librte_eal/linuxapp/arm_pmu/rte_enable_pmu.c new file +48 -0

new file mode 100644
index 0000000..9d77271
@@ -0,0 +1,83 @@
+/*-
+ *   BSD LICENSE
+ *
+ *   Copyright(c) 2015 Intel Corporation. All rights reserved.
+ *
[...]
+ */
+
+ /**
+  * @file
+  * This file enables the ARM PMU.
+  *
+  * It contains the code to enable the usage of PMU registers
+  * by application code on all cores.
+  */
+
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/uio_driver.h>
+#include <linux/io.h>
+#include <linux/msi.h>
+#include <linux/version.h>
+#include <linux/slab.h>
+
+void enable_pmu(void __attribute__((unused)) *info)
+{
+	int core_id = 0;
+
+	core_id = smp_processor_id();
+	/* Configure PMUSERENR - Enables user mode to have access to the
+	 * Performance Monitor Registers. */
+	asm volatile("mcr p15, 0, %0, c9, c14, 0" : : "r"(1));
+	/* Configure PMCR */
+	asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(29));
+	/* Configure PMCNTENSET Enable counters */
+	asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r"(0x8000000f));
+	return;
+}
+
+int __init init_module_set_arm_pmu(void)
+{
+	int ret = 0;
+	/* smp_call_function will make sure that the registers
+	 * for all the cores are enabled for tracking their PMUs
+	 * This is required for the rdtsc equivalent on ARMv7 */
+	ret = smp_call_function(&enable_pmu, NULL, 0);
+	/* smp_call_function would only call on all other modules
+	 * so call it for the current module */

mk/arch/arm/rte.vars.mk new file +18 -0

new file mode 100644
index 0000000..3dfeb16
@@ -0,0 +1,58 @@
+#   BSD LICENSE
+#
+#   Copyright(c) 2015 Intel Corporation. All rights reserved.
+#
[...]
+#
+# arch:
+#
+#   - define ARCH variable (overriden by cmdline or by previous
+#     optional define in machine .mk)
+#   - define CROSS variable (overriden by cmdline or previous define
+#     in machine .mk)
+#   - define CPU_CFLAGS variable (overriden by cmdline or previous
+#     define in machine .mk)
+#   - define CPU_LDFLAGS variable (overriden by cmdline or previous
+#     define in machine .mk)
+#   - define CPU_ASFLAGS variable (overriden by cmdline or previous
+#     define in machine .mk)
+#   - may override any previously defined variable

mk/arch/arm/rte.vars.mk new file +2 -0

+
+export ARCH CROSS CPU_CFLAGS CPU_LDFLAGS CPU_ASFLAGS

mk/machine/armv7-a/rte.vars.mk new file +22 -0

new file mode 100644
index 0000000..feeebfa
@@ -0,0 +1,63 @@
+#   BSD LICENSE
+#
+#   Copyright(c) 2015 Intel Corporation. All rights reserved.
+#
[...]
+
+#
+# machine:
+#
+#   - can define ARCH variable (overriden by cmdline value)
+#   - can define CROSS variable (overriden by cmdline value)
+#   - define MACHINE_CFLAGS variable (overriden by cmdline value)
+#   - define MACHINE_LDFLAGS variable (overriden by cmdline value)
+#   - define MACHINE_ASFLAGS variable (overriden by cmdline value)
+#   - can define CPU_CFLAGS variable (overriden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_LDFLAGS variable (overriden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_ASFLAGS variable (overriden by cmdline value) that
+#     overrides the one defined in arch.
+#   - may override any previously defined variable
+#
+

mk/toolchain/gcc/rte.vars.mk +1 -2

index 0f51c66..501fce5 100644
@@ -1,7 +1,6 @@
 #   BSD LICENSE
 #
-#   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
-#   All rights reserved.
+#   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
 #
 #   Redistribution and use in source and binary forms, with or without
 #   modification, are permitted provided that the following conditions

@@ -73,7 +72,10 @@ endif
 

Hello David, all,

I am reviewing your patch for things to be included in the final ARMv7 support... It is quite long, you know. We should probably break the potential discussion in shorter e-mails, a thread per topic. See my comments below.

Regards
Jan

Jan, I would suggest that we should plan to include your patch into the DPDK 2.2 release. If there are any portions of our patch that you feel may be beneficial to that, please feel free to merge into your patch. I then suggest you release a v2 patch based on the best parts of both, which we all can then review. Regards, Dave. P.S. Apologies for the footer below, I'm working on getting it removed.

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