arm: Add msi.h to arch Kbuild files
Subsystems (5)
PATCH 1/2 arm: Add msi.h to arch Kbuild files
The patch adds msi.h to arch Kbuild files to avoid the following compile error when selecting PCI_MSI_IRQ_DOMAIN
include/linux/msi.h:172:21: fatal error: asm/msi.h: No such file or directory
--- arch/arm/include/asm/Kbuild | 1 + 1 file changed, 1 insertion(+)
arch/arm/include/asm/Kbuild +1 -0
@@ -14,6 +14,7 @@ generic-y += local.h generic-y += local64.h generic-y += mm-arch-hooks.h generic-y += msgbuf.h +generic-y += msi.h generic-y += param.h generic-y += parport.h generic-y += poll.h
Signature · 1 line
1.9.1
PATCH 2/2 irqchip/Layerscape: Add Layerscape MSI controller support
Some SoC of Freescale Layerscape provide a kind of MSI controller which uses two registers MSIIR and MSIR to support 32 MSI interrupts for each PCIe controller. The patch is to support it.
--- .../bindings/interrupt-controller/fsl,ls1-msi.txt | 26 +++ arch/arm/mach-imx/Kconfig | 1 + drivers/irqchip/Kconfig | 5 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-ls1-msi.c | 247 +++++++++++++++++++++ 5 files changed, 280 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,ls1-msi.txt create mode 100644 drivers/irqchip/irq-ls1-msi.c
Documentation/devicetree/bindings/interrupt-controller/fsl,ls1-msi.txt new file +26 -0
@@ -0,0 +1,26 @@ +* Freescale Layerscape PCIe MSI controller + +Required properties: + +- compatible: should be "fsl,<chip>-msi" to identify + Layerscape PCIe MSI controller block. +- msi-controller: indicates that this is a PCIe MSI controller node +- reg: Should contain msiir and msir registers location and length. + MSIIR is a MSI index register to trigger interrupts. + MSIR indicates which of the 32 interrupt sources have pending interrupt. +- reg-names: should be "msiir" and "msir". +- interrupts: A interrupt of the controller. + +Each PCIe node needs to have property msi-parent that points to +MSI controller node + +Examples: + + msi1: msi-controller1 at 1571000 { + compatible = "fsl,1s1043a-msi"; + reg = <0x0 0x1571000 0x0 0x4>, + <0x0 0x1571004 0x0 0x4>; + reg-names = "msiir", "msir"; + msi-controller; + interrupts = <0 116 0x4>; + };
arch/arm/mach-imx/Kconfig +1 -0
@@ -570,6 +570,7 @@ config SOC_LS1021A select ARM_GIC select HAVE_ARM_ARCH_TIMER select PCI_DOMAINS if PCI + select LS1_MSI if PCI_MSI select ZONE_DMA if ARM_LPAE help This enables support for Freescale LS1021A processor.
drivers/irqchip/Kconfig +5 -0
@@ -187,3 +187,8 @@ config IMX_GPCV2 select IRQ_DOMAIN help Enables the wakeup IRQs for IMX platforms with GPCv2 block + +config LS1_MSI + bool + depends on PCI && PCI_MSI + select PCI_MSI_IRQ_DOMAIN
drivers/irqchip/Makefile +1 -0
@@ -55,3 +55,4 @@ obj-$(CONFIG_RENESAS_H8S_INTC) += irq-renesas-h8s.o obj-$(CONFIG_ARCH_SA1100) += irq-sa11x0.o obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o obj-$(CONFIG_IMX_GPCV2) += irq-imx-gpcv2.o +obj-$(CONFIG_LS1_MSI) += irq-ls1-msi.o
drivers/irqchip/irq-ls1-msi.c new file +247 -0
247 lines not on this page · raw message
Signature · 1 line
1.9.1
PATCH 2/2 irqchip/Layerscape: Add Layerscape MSI controller support
Quoted 3 lines · Minghuan Lian
Some SoC of Freescale Layerscape provide a kind of MSI controller which uses two registers MSIIR and MSIR to support 32 MSI interrupts for each PCIe controller. The patch is to support it.
If this only applies to LS1 please say explicitly that this is only for Layerscape 1 series in the title, commit message and code comment. It seems that we are not delivering a consistent message here. Although I don't even know if associating this with LS 1 series will stay true in the future. Maybe we should instead mention it as MSI controller with an old GIC?
Regards,
Leo
PATCH 2/2 irqchip/Layerscape: Add Layerscape MSI controller support
Hi Leo,
Could you tell me how to get the detailed Layerscape route map.
I am not sure that only Layerscape 1 series use the similar GIC and SCFG to implement MSI. I am even not sure if ls1043 belongs Layerscape 1 series.
Could anyone tell me how to get the MSI route map?
Thanks,
Minghuan
Quoted 27 lines
-----Original Message-----
From: pku.leo at gmail.com [mailto:pku.leo at gmail.com] On Behalf Of Li Yang
Sent: Saturday, September 26, 2015 12:37 AM
To: Lian Minghuan-B31939 <[email protected]>
Cc: linux-arm-kernel at lists.infradead.org; Jason Cooper <[email protected]>; Hu Mingkai-B21284 <[email protected]>; Yoder Stuart-B08248 <[email protected]>; Zang Roy-R61911 <[email protected]>; Thomas Gleixner <[email protected]>
Subject: Re: [PATCH 2/2] irqchip/Layerscape: Add Layerscape MSI controller supportQuoted 3 lines · Minghuan Lian
Some SoC of Freescale Layerscape provide a kind of MSI controller which uses two registers MSIIR and MSIR to support 32 MSI interrupts for each PCIe controller. The patch is to support it.
If this only applies to LS1 please say explicitly that this is only for Layerscape 1 series in the title, commit message and code comment.
It seems that we are not delivering a consistent message here. Although I don't even know if associating this with LS 1 series will stay true in the future. Maybe we should instead mention it as MSI controller with an old GIC?Regards,
Leo
PATCH 2/2 irqchip/Layerscape: Add Layerscape MSI controller support
Quoted 7 lines · Lian M.H.
Hi Leo,
Could you tell me how to get the detailed Layerscape route map.
I am not sure that only Layerscape 1 series use the similar GIC and SCFG to implement MSI. I am even not sure if ls1043 belongs Layerscape 1 series.Could anyone tell me how to get the MSI route map?
MSI shouldn't be the key feature to determine the naming of an SoC. So I don't think anyone can tell if all 1 series in the future will use this approach. Probably it will be more generic to name it "fsl,scfg-msi"
Regards,
Leo
PATCH 2/2 irqchip/Layerscape: Add Layerscape MSI controller support
Hi Leo,
Thanks for your advice.
"fsl,scfg-msi" is better, I use it in next version.
Thanks,
Minghuan
Quoted 28 lines
-----Original Message-----
From: pku.leo at gmail.com [mailto:pku.leo at gmail.com] On Behalf Of Li Yang
Sent: Tuesday, September 29, 2015 6:19 AM
To: Lian Minghuan-B31939 <[email protected]>
Cc: Jason Cooper <[email protected]>; Yoder Stuart-B08248 <[email protected]>; Thomas Gleixner <[email protected]>; Zang Roy-R61911 <[email protected]>; Hu Mingkai-B21284 <[email protected]>; linux-arm-kernel at lists.infradead.org
Subject: Re: [PATCH 2/2] irqchip/Layerscape: Add Layerscape MSI controller supportQuoted 4 lines · Lian M.H.
Hi Leo,
Could you tell me how to get the detailed Layerscape route map. I am not sure that only Layerscape 1 series use the similar GIC and SCFG to
implement MSI.
Quoted 3 lines
I am even not sure if ls1043 belongs Layerscape 1 series.
Could anyone tell me how to get the MSI route map?
MSI shouldn't be the key feature to determine the naming of an SoC.
So I don't think anyone can tell if all 1 series in the future will use this approach. Probably it will be more generic to name it "fsl,scfg-msi"Regards,
Leo
PATCH 2/2 irqchip/Layerscape: Add Layerscape MSI controller support
Quoted 4 lines · Lian M.H.
Hi Leo,
Thanks for your advice.
"fsl,scfg-msi" is better, I use it in next version.
For the device tree compatible, "fsl,ls1043a-msi" is still a good name while you can add "fsl,scfg-msi" as an additional compatible. I'm actually saying we should replace all ls1-msi stuff with scfg-msi. And make it aligned in patch title/description, file name/description/comment, and etc.
Regards,
Leo
PATCH 2/2 irqchip/Layerscape: Add Layerscape MSI controller support
In reply to Li YangQuoted 9 lines · Li Yang
Quoted 7 lines · Lian M.H.
Hi Leo,
Could you tell me how to get the detailed Layerscape route map. I am not sure that only Layerscape 1 series use the similar GIC and SCFG to implement MSI.
I am even not sure if ls1043 belongs Layerscape 1 series.
Quoted 5 lines
Quoted 1 line
Could anyone tell me how to get the MSI route map?
MSI shouldn't be the key feature to determine the naming of an SoC. So I don't think anyone can tell if all 1 series in the future will use this approach.
In the past the only thing the first number of a QorIQ chip name has meant is an approximate positioning on the low-end/high-end spectrum. It cannot be used for grouping chips according to anything that software cares about.
Quoted 1 line
Probably it will be more generic to name it "fsl,scfg-msi"
Better would have a specific SoC in the name.
-Scott
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PATCH 2/2 irqchip/Layerscape: Add Layerscape MSI controller support
Quoted 59 lines
-----Original Message-----
From: Stuart Yoder [mailto:b08248 at gmail.com]
Sent: Thursday, October 08, 2015 7:48 PM
To: Yoder Stuart-B08248
Subject: Fwd: [PATCH 2/2] irqchip/Layerscape: Add Layerscape MSI controller support---------- Forwarded message ----------
From: Minghuan Lian <[email protected]>
Date: Thu, Sep 17, 2015 at 4:28 AM
Subject: [PATCH 2/2] irqchip/Layerscape: Add Layerscape MSI controller support
To: linux-arm-kernel at lists.infradead.org
Cc: Jason Cooper <[email protected]>, Hu Mingkai-B21284 <[email protected]>, Yoder Stuart-B08248 <[email protected]>, Zang Roy-R61911 <[email protected]>, Minghuan Lian <[email protected]>, Thomas Gleixner <[email protected]>, Li Yang <[email protected]>Some SoC of Freescale Layerscape provide a kind of MSI controller which uses two registers MSIIR and MSIR to support 32 MSI interrupts for each PCIe controller. The patch is to support it.
Signed-off-by Minghuan Lian <[email protected]>--- .../bindings/interrupt-controller/fsl,ls1-msi.txt | 26 +++ arch/arm/mach-imx/Kconfig | 1 + drivers/irqchip/Kconfig | 5 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-ls1-msi.c | 247 +++++++++++++++++++++ 5 files changed, 280 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,ls1-msi.txt create mode 100644 drivers/irqchip/irq-ls1-msi.cDocumentation/devicetree/bindings/interrupt-controller/fsl,ls1-msi.txt new file +16
-0@@ -0,0 +1,26 @@ +* Freescale Layerscape PCIe MSI controller + +Required properties: + +- compatible: should be "fsl,<chip>-msi" to identify + Layerscape PCIe MSI controller block. +- msi-controller: indicates that this is a PCIe MSI controller node +- reg: Should contain msiir and msir registers location and length. + MSIIR is a MSI index register to trigger interrupts. + MSIR indicates which of the 32 interrupt sources have pending interrupt. +- reg-names: should be "msiir" and "msir". +- interrupts: A interrupt of the controller. + +Each PCIe node needs to have property msi-parent that points to +MSI controller node +
Documentation/devicetree/bindings/interrupt-controller/fsl,ls1-msi.txt line 26
Quoted 10 lines
Documentation/devicetree/bindings/interrupt-controller/fsl,ls1-msi.txt new file +10
-0+Examples: + + msi1: msi-controller1 at 1571000 { + compatible = "fsl,1s1043a-msi"; + reg = <0x0 0x1571000 0x0 0x4>, + <0x0 0x1571004 0x0 0x4>; + reg-names = "msiir", "msir"; + msi-controller; + interrupts = <0 116 0x4>; + };
Why does this binding explicitly define registers like this? The 2 registers are in consecutive words, so why isn't a reg property defining both regs enough? Why do you have a reg-names property? It does not seem to be used by the driver.
Stuart
PATCH 2/2 irqchip/Layerscape: Add Layerscape MSI controller support
Hi Stuart,
Please see my comments inline.
Thanks,
Minghuan
Quoted 85 lines
-----Original Message-----
From: Yoder Stuart-B08248
Sent: Friday, October 09, 2015 8:52 AM
To: Lian Minghuan-B31939 <[email protected]>
Cc: linux-arm-kernel at lists.infradead.org; Jason Cooper <[email protected]>; Hu Mingkai-B21284 <[email protected]>; Zang Roy-R61911 <[email protected]>; Thomas Gleixner <[email protected]>; Li Yang-Leo-R58472 <[email protected]>
Subject: RE: [PATCH 2/2] irqchip/Layerscape: Add Layerscape MSI controller supportQuoted 24 lines
-----Original Message-----
From: Stuart Yoder [mailto:b08248 at gmail.com]
Sent: Thursday, October 08, 2015 7:48 PM
To: Yoder Stuart-B08248
Subject: Fwd: [PATCH 2/2] irqchip/Layerscape: Add Layerscape MSI controller support---------- Forwarded message ----------
From: Minghuan Lian <[email protected]>
Date: Thu, Sep 17, 2015 at 4:28 AM
Subject: [PATCH 2/2] irqchip/Layerscape: Add Layerscape MSI controller support
To: linux-arm-kernel at lists.infradead.org
Cc: Jason Cooper <[email protected]>, Hu Mingkai-B21284 <[email protected]>, Yoder Stuart-B08248 <[email protected]>, Zang Roy-R61911 <[email protected]>, Minghuan Lian <[email protected]>, Thomas Gleixner <[email protected]>, Li Yang <[email protected]>Some SoC of Freescale Layerscape provide a kind of MSI controller which uses two registers MSIIR and MSIR to support 32 MSI interrupts for each PCIe controller. The patch is to support it.
Quoted 7 lines
Signed-off-by Minghuan Lian <[email protected]>--- .../bindings/interrupt-controller/fsl,ls1-msi.txt | 26 +++ arch/arm/mach-imx/Kconfig | 1 + drivers/irqchip/Kconfig | 5 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-ls1-msi.c | 247+++++++++++++++++++++
Quoted 16 lines
5 files changed, 280 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,ls1-msi.txt create mode 100644 drivers/irqchip/irq-ls1-msi.cdiff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls1-msi.t xt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls1-msi.t xt
new file mode 100644
index 0000000..29296c1Documentation/devicetree/bindings/interrupt-controller/fsl,ls1-m new file +1
-0+++ si.txtDocumentation/devicetree/bindings/interrupt-controller/fsl,ls1-m line 10
Quoted 10 lines
Documentation/devicetree/bindings/interrupt-controller/fsl,ls1-m new file +10
-0@@ -0,0 +1,26 @@ +* Freescale Layerscape PCIe MSI controller + +Required properties: + +- compatible: should be "fsl,<chip>-msi" to identify + Layerscape PCIe MSI controller block. +- msi-controller: indicates that this is a PCIe MSI controller node +- reg: Should contain msiir and msir registers location and length. + MSIIR is a MSI index register to trigger interrupts. + MSIR indicates which of the 32 interrupt sources have pendinginterrupt.
Quoted 13 lines
Documentation/devicetree/bindings/interrupt-controller/fsl,ls1-m new file +13
-0+- reg-names: should be "msiir" and "msir". +- interrupts: A interrupt of the controller. + +Each PCIe node needs to have property msi-parent that points to MSI +controller node + +Examples: + + msi1: msi-controller1 at 1571000 { + compatible = "fsl,1s1043a-msi"; + reg = <0x0 0x1571000 0x0 0x4>, + <0x0 0x1571004 0x0 0x4>; + reg-names = "msiir", "msir";
Quoted 9 lines
Documentation/devicetree/bindings/interrupt-controller/fsl,ls1-m line 26
Quoted 3 lines
Documentation/devicetree/bindings/interrupt-controller/fsl,ls1-m new file +3
-0+ msi-controller; + interrupts = <0 116 0x4>; + };Why does this binding explicitly define registers like this? The 2 registers are in consecutive words, so why isn't a reg property defining both regs enough? Why do you have a reg-names property? It does not seem to be used by the driver.
[Lian Minghuan-B31939] Because the register MSIIR and MSIR on our PowerPC implementation is discontinuous, even the offset between them is different for different MSI controller. So I defines the register separately. Maybe I thought too much. If they are always continuous on all the Layerscape MSI implementation, I will remove 'reg-names'.
Quoted 1 line
Stuart