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qcom-scm fixes and support for OCMEM

PATCH In review Rob Clark 1 participant 10 messages Oct 5, 2015 – Oct 6, 2015 Arm Qualcomm mailing list

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Rob Clark

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#0 lore raw

cover qcom-scm fixes and support for OCMEM

Split out the restore-secure-config part from the ocmem lock/unlock, and updates to address review comments.

Rob Clark (5):
qcom-scm: fix endianess issue in __qcom_scm_is_call_available
qcom-scm: fix header compile errors
qcom-scm: add missing prototype for qcom_scm_is_available()
qcom-scm: add support to restore secure config
qcom-scm: add OCMEM lock/unlock interface

 drivers/firmware/qcom_scm-32.c | 60 ++++++++++++++++++++++++++++++++++++--
 drivers/firmware/qcom_scm-64.c | 16 +++++++++++
 drivers/firmware/qcom_scm.c    | 65 ++++++++++++++++++++++++++++++++++++++++--
 drivers/firmware/qcom_scm.h    | 12 ++++++++
 include/linux/qcom_scm.h       | 16 +++++++++--
 5 files changed, 162 insertions(+), 7 deletions(-)
Signature · 6 lines
2.4.3

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http://lists.freedesktop.org/mailman/listinfo/dri-devel
author
#1 lore raw

PATCH 1/5 qcom-scm: fix endianess issue in __qcom_scm_is_call_available

Signed-off-by Rob Clark <[email protected]>
Reviewed-by Stephen Boyd <[email protected]>
---
 drivers/firmware/qcom_scm-32.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)
drivers/firmware/qcom_scm-32.c +3 -3
index e9c306b..c1e4325 100644
@@ -480,15 +480,15 @@ void __qcom_scm_cpu_power_down(u32 flags)
 int __qcom_scm_is_call_available(u32 svc_id, u32 cmd_id)
 {
 	int ret;
-	u32 svc_cmd = (svc_id << 10) | cmd_id;
-	u32 ret_val = 0;
+	__le32 svc_cmd = cpu_to_le32((svc_id << 10) | cmd_id);
+	__le32 ret_val = 0;
 
 	ret = qcom_scm_call(QCOM_SCM_SVC_INFO, QCOM_IS_CALL_AVAIL_CMD, &svc_cmd,
 			sizeof(svc_cmd), &ret_val, sizeof(ret_val));
 	if (ret)
 		return ret;
 
-	return ret_val;
+	return le32_to_cpu(ret_val);
 }
 
 int __qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp)
Signature · 1 line
2.4.3
author
#2 lore raw

PATCH 2/5 qcom-scm: fix header compile errors

In reply to Rob Clark

Add missing #include for types.h to have u32, etc. And fwd declare 'struct cpumask'.

Signed-off-by Rob Clark <[email protected]>
---
 drivers/firmware/qcom_scm.c | 4 ++--
 include/linux/qcom_scm.h    | 7 +++++--
 2 files changed, 7 insertions(+), 4 deletions(-)
drivers/firmware/qcom_scm.c +2 -2
index 118df0a..39082c1 100644
@@ -76,7 +76,7 @@ static void qcom_scm_clk_disable(void)
  * Set the cold boot address of the cpus. Any cpu outside the supported
  * range would be removed from the cpu present mask.
  */
-int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
+int qcom_scm_set_cold_boot_addr(void *entry, const struct cpumask *cpus)
 {
 	return __qcom_scm_set_cold_boot_addr(entry, cpus);
 }

@@ -90,7 +90,7 @@ EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
  * Set the Linux entry point for the SCM to transfer control to when coming
  * out of a power down. CPU power down may be executed on cpuidle or hotplug.
  */
-int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
+int qcom_scm_set_warm_boot_addr(void *entry, const struct cpumask *cpus)
 {
 	return __qcom_scm_set_warm_boot_addr(entry, cpus);
 }
include/linux/qcom_scm.h +5 -2
index 46d41e4..c536b70 100644
@@ -13,8 +13,11 @@
 #ifndef __QCOM_SCM_H
 #define __QCOM_SCM_H
 
-extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
-extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
+#include <linux/types.h>
+
+struct cpumask;
+extern int qcom_scm_set_cold_boot_addr(void *entry, const struct cpumask *cpus);
+extern int qcom_scm_set_warm_boot_addr(void *entry, const struct cpumask *cpus);
 
 #define QCOM_SCM_HDCP_MAX_REQ_CNT	5
Signature · 1 line
2.4.3
author
#3 lore raw

PATCH 3/5 qcom-scm: add missing prototype for qcom_scm_is_available()

In reply to Rob Clark
Signed-off-by Rob Clark <[email protected]>
---
 include/linux/qcom_scm.h | 2 ++
 1 file changed, 2 insertions(+)
include/linux/qcom_scm.h +2 -0
index c536b70..e407c0a 100644
@@ -26,6 +26,8 @@ struct qcom_scm_hdcp_req {
 	u32 val;
 };
 
+extern bool qcom_scm_is_available(void);
+
 extern bool qcom_scm_hdcp_available(void);
 extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
 		u32 *resp);
Signature · 1 line
2.4.3
author
#4 lore raw

PATCH 4/5 qcom-scm: add support to restore secure config

In reply to Rob Clark

Needed by OCMEM driver.

Signed-off-by Rob Clark <[email protected]>
---
 drivers/firmware/qcom_scm-32.c | 20 ++++++++++++++++++++
 drivers/firmware/qcom_scm-64.c |  5 +++++
 drivers/firmware/qcom_scm.c    | 22 ++++++++++++++++++++++
 drivers/firmware/qcom_scm.h    |  5 +++++
 include/linux/qcom_scm.h       |  3 +++
 5 files changed, 55 insertions(+)
drivers/firmware/qcom_scm-32.c +20 -0
index c1e4325..a7bf6d4 100644
@@ -500,6 +500,26 @@ int __qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp)
 		req, req_cnt * sizeof(*req), resp, sizeof(*resp));
 }
 
+int __qcom_scm_restore_sec_config(u32 sec_id, u32 ctx_bank_num)
+{
+	int ret, scm_ret = 0;
+	struct msm_scm_sec_cfg {
+		__le32 id;
+		__le32 ctx_bank_num;
+	} cfg;
+
+	cfg.id = cpu_to_le32(sec_id);
+	cfg.ctx_bank_num = cpu_to_le32(sec_id);
+
+	ret = qcom_scm_call(QCOM_SCM_MP_SVC, QCOM_SCM_MP_RESTORE_SEC_CFG,
+			&cfg, sizeof(cfg), &scm_ret, sizeof(scm_ret));
+
+	if (ret || scm_ret)
+		return ret ? ret : -EINVAL;
+
+	return 0;
+}
+
 bool __qcom_scm_pas_supported(u32 peripheral)
 {
 	__le32 out;
drivers/firmware/qcom_scm-64.c +5 -0
index e64fd92..7329cf0f 100644
@@ -62,6 +62,11 @@ int __qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp)
 	return -ENOTSUPP;
 }
 
+int __qcom_scm_restore_sec_config(u32 sec_id, u32 ctx_bank_num)
+{
+	return -ENOTSUPP;
+}
+
 bool __qcom_scm_pas_supported(u32 peripheral)
 {
 	return false;
drivers/firmware/qcom_scm.c +22 -0
index 39082c1..8f43c0b 100644
@@ -154,6 +154,28 @@ int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp)
 EXPORT_SYMBOL(qcom_scm_hdcp_req);
 
 /**
+ * qcom_scm_restore_sec_config_available() - Check if secure environment
+ * supports restore security config interface.
+ *
+ * Return true if restore-cfg interface is supported, false if not.
+ */
+bool qcom_scm_restore_sec_config_available(void)
+{
+	return __qcom_scm_is_call_available(QCOM_SCM_MP_SVC,
+			QCOM_SCM_MP_RESTORE_SEC_CFG);
+}
+EXPORT_SYMBOL(qcom_scm_restore_sec_config_available);
+
+/**
+ * qcom_scm_restore_sec_config() - call restore-cfg interface
+ */
+int qcom_scm_restore_sec_config(unsigned sec_id)
+{
+	return __qcom_scm_restore_sec_config(sec_id, 0);
+}
+EXPORT_SYMBOL(qcom_scm_restore_sec_config);
+
+/**
  * qcom_scm_pas_supported() - Check if the peripheral authentication service is
  *			      available for the given peripherial
  * @peripheral:	peripheral id
drivers/firmware/qcom_scm.h +5 -0
index 220d19c..3085616 100644
@@ -36,6 +36,11 @@ extern int __qcom_scm_is_call_available(u32 svc_id, u32 cmd_id);
 extern int __qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
 		u32 *resp);
 
+#define QCOM_SCM_MP_SVC			0xc
+#define QCOM_SCM_MP_RESTORE_SEC_CFG		0x2
+
+extern int __qcom_scm_restore_sec_config(u32 sec_id, u32 ctx_bank_num);
+
 #define QCOM_SCM_SVC_PIL		0x2
 #define QCOM_SCM_PAS_INIT_IMAGE_CMD	0x1
 #define QCOM_SCM_PAS_MEM_SETUP_CMD	0x2
include/linux/qcom_scm.h +3 -0
index e407c0a..7be3d91 100644
@@ -32,6 +32,9 @@ extern bool qcom_scm_hdcp_available(void);
 extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
 		u32 *resp);
 
+extern bool qcom_scm_restore_sec_config_available(void);
+extern int qcom_scm_restore_sec_config(unsigned sec_id);
+
 extern bool qcom_scm_pas_supported(u32 peripheral);
 extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size);
 extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size);
Signature · 6 lines
2.4.3

_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/dri-devel
author
#5 lore raw

Re: [PATCH 4/5] qcom-scm: add support to restore secure config

Quoted 4 lines · Rob Clark

Needed by OCMEM driver.

Signed-off-by Rob Clark <[email protected]>

---

Note: I am contemplating squashing something like this in:

----------------

include/linux/qcom_scm.h +11 -2
index beadca4..d3f209d 100644
@@ -32,8 +32,18 @@ extern bool qcom_scm_hdcp_available(void);
 extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
         u32 *resp);
 
+enum qcom_scm_sec_dev_id {
+    QCOM_SCM_MDSS_DEV_ID    = 1,
+    QCOM_SCM_OCMEM_DEV_ID    = 5,
+    QCOM_SCM_PCIE0_DEV_ID    = 11,
+    QCOM_SCM_PCIE1_DEV_ID    = 12,
+    QCOM_SCM_GFX_DEV_ID    = 18,
+    QCOM_SCM_UFS_DEV_ID    = 19,
+    QCOM_SCM_ICE_DEV_ID    = 20,
+};
+
 extern bool qcom_scm_restore_sec_config_available(void);
-extern int qcom_scm_restore_sec_config(unsigned sec_id);
+extern int qcom_scm_restore_sec_config(enum qcom_scm_sec_dev_id sec_id);
----------------

The thing I am unsure about is whether the device-id's are always stable across different parts. From what I can tell from dumpster-diving the downstream kernel, there is a mix of hard-coding dev-id in code, vs taking it out of devicetree. But in cases where it comes from devicetree, it seems like it is always using the same values across different SoCs. But I may be missing something.. and since downstream kernel branches tend to shed support for older generations I may not be going far enough back in time..

BR,
-R

Quoted 118 lines
 drivers/firmware/qcom_scm-32.c | 20 ++++++++++++++++++++
 drivers/firmware/qcom_scm-64.c |  5 +++++
 drivers/firmware/qcom_scm.c    | 22 ++++++++++++++++++++++
 drivers/firmware/qcom_scm.h    |  5 +++++
 include/linux/qcom_scm.h       |  3 +++
 5 files changed, 55 insertions(+)
drivers/firmware/qcom_scm-32.c +20 -0
index c1e4325..a7bf6d4 100644
@@ -500,6 +500,26 @@ int __qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp)
                req, req_cnt * sizeof(*req), resp, sizeof(*resp));
 }
 
+int __qcom_scm_restore_sec_config(u32 sec_id, u32 ctx_bank_num)
+{
+       int ret, scm_ret = 0;
+       struct msm_scm_sec_cfg {
+               __le32 id;
+               __le32 ctx_bank_num;
+       } cfg;
+
+       cfg.id = cpu_to_le32(sec_id);
+       cfg.ctx_bank_num = cpu_to_le32(sec_id);
+
+       ret = qcom_scm_call(QCOM_SCM_MP_SVC, QCOM_SCM_MP_RESTORE_SEC_CFG,
+                       &cfg, sizeof(cfg), &scm_ret, sizeof(scm_ret));
+
+       if (ret || scm_ret)
+               return ret ? ret : -EINVAL;
+
+       return 0;
+}
+
 bool __qcom_scm_pas_supported(u32 peripheral)
 {
        __le32 out;
drivers/firmware/qcom_scm-64.c +5 -0
index e64fd92..7329cf0f 100644
@@ -62,6 +62,11 @@ int __qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp)
        return -ENOTSUPP;
 }
 
+int __qcom_scm_restore_sec_config(u32 sec_id, u32 ctx_bank_num)
+{
+       return -ENOTSUPP;
+}
+
 bool __qcom_scm_pas_supported(u32 peripheral)
 {
        return false;
drivers/firmware/qcom_scm.c +22 -0
index 39082c1..8f43c0b 100644
@@ -154,6 +154,28 @@ int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp)
 EXPORT_SYMBOL(qcom_scm_hdcp_req);
 
 /**
+ * qcom_scm_restore_sec_config_available() - Check if secure environment
+ * supports restore security config interface.
+ *
+ * Return true if restore-cfg interface is supported, false if not.
+ */
+bool qcom_scm_restore_sec_config_available(void)
+{
+       return __qcom_scm_is_call_available(QCOM_SCM_MP_SVC,
+                       QCOM_SCM_MP_RESTORE_SEC_CFG);
+}
+EXPORT_SYMBOL(qcom_scm_restore_sec_config_available);
+
+/**
+ * qcom_scm_restore_sec_config() - call restore-cfg interface
+ */
+int qcom_scm_restore_sec_config(unsigned sec_id)
+{
+       return __qcom_scm_restore_sec_config(sec_id, 0);
+}
+EXPORT_SYMBOL(qcom_scm_restore_sec_config);
+
+/**
  * qcom_scm_pas_supported() - Check if the peripheral authentication service is
  *                           available for the given peripherial
  * @peripheral:        peripheral id
drivers/firmware/qcom_scm.h +5 -0
index 220d19c..3085616 100644
@@ -36,6 +36,11 @@ extern int __qcom_scm_is_call_available(u32 svc_id, u32 cmd_id);
 extern int __qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
                u32 *resp);
 
+#define QCOM_SCM_MP_SVC                        0xc
+#define QCOM_SCM_MP_RESTORE_SEC_CFG            0x2
+
+extern int __qcom_scm_restore_sec_config(u32 sec_id, u32 ctx_bank_num);
+
 #define QCOM_SCM_SVC_PIL               0x2
 #define QCOM_SCM_PAS_INIT_IMAGE_CMD    0x1
 #define QCOM_SCM_PAS_MEM_SETUP_CMD     0x2
include/linux/qcom_scm.h +3 -1
index e407c0a..7be3d91 100644
@@ -32,6 +32,9 @@ extern bool qcom_scm_hdcp_available(void);
 extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
                u32 *resp);
 
+extern bool qcom_scm_restore_sec_config_available(void);
+extern int qcom_scm_restore_sec_config(unsigned sec_id);
+
 extern bool qcom_scm_pas_supported(u32 peripheral);
 extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size);
 extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size);
--
Quoted 2 lines

2.4.3

_______________________________________________
dri-devel mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/dri-devel

author
#6 lore raw

PATCH 1/1 qcom-scm: add support to restore secure config

Needed by OCMEM driver.

Signed-off-by Rob Clark <[email protected]>

---
Note: no objections to the device-id enum on mailing list and positive feedback on ##linux-msm so squashing that part in and re-sending

 drivers/firmware/qcom_scm-32.c | 20 ++++++++++++++++++++
 drivers/firmware/qcom_scm-64.c |  5 +++++
 drivers/firmware/qcom_scm.c    | 22 ++++++++++++++++++++++
 drivers/firmware/qcom_scm.h    |  5 +++++
 include/linux/qcom_scm.h       | 13 +++++++++++++
 5 files changed, 65 insertions(+)
drivers/firmware/qcom_scm-32.c +20 -0
index c1e4325..a7bf6d4 100644
@@ -500,6 +500,26 @@ int __qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp)
 		req, req_cnt * sizeof(*req), resp, sizeof(*resp));
 }
 
+int __qcom_scm_restore_sec_config(u32 sec_id, u32 ctx_bank_num)
+{
+	int ret, scm_ret = 0;
+	struct msm_scm_sec_cfg {
+		__le32 id;
+		__le32 ctx_bank_num;
+	} cfg;
+
+	cfg.id = cpu_to_le32(sec_id);
+	cfg.ctx_bank_num = cpu_to_le32(sec_id);
+
+	ret = qcom_scm_call(QCOM_SCM_MP_SVC, QCOM_SCM_MP_RESTORE_SEC_CFG,
+			&cfg, sizeof(cfg), &scm_ret, sizeof(scm_ret));
+
+	if (ret || scm_ret)
+		return ret ? ret : -EINVAL;
+
+	return 0;
+}
+
 bool __qcom_scm_pas_supported(u32 peripheral)
 {
 	__le32 out;
drivers/firmware/qcom_scm-64.c +5 -0
index e64fd92..7329cf0f 100644
@@ -62,6 +62,11 @@ int __qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp)
 	return -ENOTSUPP;
 }
 
+int __qcom_scm_restore_sec_config(u32 sec_id, u32 ctx_bank_num)
+{
+	return -ENOTSUPP;
+}
+
 bool __qcom_scm_pas_supported(u32 peripheral)
 {
 	return false;
drivers/firmware/qcom_scm.c +22 -0
index 39082c1..c9c99a3 100644
@@ -154,6 +154,28 @@ int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp)
 EXPORT_SYMBOL(qcom_scm_hdcp_req);
 
 /**
+ * qcom_scm_restore_sec_config_available() - Check if secure environment
+ * supports restore security config interface.
+ *
+ * Return true if restore-cfg interface is supported, false if not.
+ */
+bool qcom_scm_restore_sec_config_available(void)
+{
+	return __qcom_scm_is_call_available(QCOM_SCM_MP_SVC,
+			QCOM_SCM_MP_RESTORE_SEC_CFG);
+}
+EXPORT_SYMBOL(qcom_scm_restore_sec_config_available);
+
+/**
+ * qcom_scm_restore_sec_config() - call restore-cfg interface
+ */
+int qcom_scm_restore_sec_config(enum qcom_scm_sec_dev_id sec_id)
+{
+	return __qcom_scm_restore_sec_config(sec_id, 0);
+}
+EXPORT_SYMBOL(qcom_scm_restore_sec_config);
+
+/**
  * qcom_scm_pas_supported() - Check if the peripheral authentication service is
  *			      available for the given peripherial
  * @peripheral:	peripheral id
drivers/firmware/qcom_scm.h +5 -0
index 220d19c..3085616 100644
@@ -36,6 +36,11 @@ extern int __qcom_scm_is_call_available(u32 svc_id, u32 cmd_id);
 extern int __qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
 		u32 *resp);
 
+#define QCOM_SCM_MP_SVC			0xc
+#define QCOM_SCM_MP_RESTORE_SEC_CFG		0x2
+
+extern int __qcom_scm_restore_sec_config(u32 sec_id, u32 ctx_bank_num);
+
 #define QCOM_SCM_SVC_PIL		0x2
 #define QCOM_SCM_PAS_INIT_IMAGE_CMD	0x1
 #define QCOM_SCM_PAS_MEM_SETUP_CMD	0x2
include/linux/qcom_scm.h +13 -0
index e407c0a..ee31eec 100644
@@ -32,6 +32,19 @@ extern bool qcom_scm_hdcp_available(void);
 extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
 		u32 *resp);
 
+enum qcom_scm_sec_dev_id {
+	QCOM_SCM_MDSS_DEV_ID	= 1,
+	QCOM_SCM_OCMEM_DEV_ID	= 5,
+	QCOM_SCM_PCIE0_DEV_ID	= 11,
+	QCOM_SCM_PCIE1_DEV_ID	= 12,
+	QCOM_SCM_GFX_DEV_ID	= 18,
+	QCOM_SCM_UFS_DEV_ID	= 19,
+	QCOM_SCM_ICE_DEV_ID	= 20,
+};
+
+extern bool qcom_scm_restore_sec_config_available(void);
+extern int qcom_scm_restore_sec_config(enum qcom_scm_sec_dev_id sec_id);
+
 extern bool qcom_scm_pas_supported(u32 peripheral);
 extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size);
 extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size);
Signature · 1 line
2.4.3
author
#7 lore raw

PATCH 5/5 qcom-scm: add OCMEM lock/unlock interface

In reply to Rob Clark

Needed to enable device access to OCMEM.

Signed-off-by Rob Clark <[email protected]>
---
 drivers/firmware/qcom_scm-32.c | 34 ++++++++++++++++++++++++++++++++++
 drivers/firmware/qcom_scm-64.c | 11 +++++++++++
 drivers/firmware/qcom_scm.c    | 39 +++++++++++++++++++++++++++++++++++++++
 drivers/firmware/qcom_scm.h    |  7 +++++++
 include/linux/qcom_scm.h       |  4 ++++
 5 files changed, 95 insertions(+)
drivers/firmware/qcom_scm-32.c +34 -0
index a7bf6d4..dc84771b 100644
@@ -520,6 +520,40 @@ int __qcom_scm_restore_sec_config(u32 sec_id, u32 ctx_bank_num)
 	return 0;
 }
 
+int __qcom_scm_ocmem_lock(u32 id, u32 offset, u32 size, u32 mode)
+{
+	struct ocmem_tz_lock {
+		__le32 id;
+		__le32 offset;
+		__le32 size;
+		__le32 mode;
+	} request;
+
+	request.id     = cpu_to_le32(id);
+	request.offset = cpu_to_le32(offset);
+	request.size   = cpu_to_le32(size);
+	request.mode   = cpu_to_le32(mode);
+
+	return qcom_scm_call(QCOM_SCM_OCMEM_SVC, QCOM_SCM_OCMEM_LOCK_CMD,
+			&request, sizeof(request), NULL, 0);
+}
+
+int __qcom_scm_ocmem_unlock(u32 id, u32 offset, u32 size)
+{
+	struct ocmem_tz_unlock {
+		__le32 id;
+		__le32 offset;
+		__le32 size;
+	} request;
+
+	request.id     = cpu_to_le32(id);
+	request.offset = cpu_to_le32(offset);
+	request.size   = cpu_to_le32(size);
+
+	return qcom_scm_call(QCOM_SCM_OCMEM_SVC, QCOM_SCM_OCMEM_UNLOCK_CMD,
+			&request, sizeof(request), NULL, 0);
+}
+
 bool __qcom_scm_pas_supported(u32 peripheral)
 {
 	__le32 out;
drivers/firmware/qcom_scm-64.c +11 -0
index 7329cf0f..0ca20a3 100644
@@ -67,6 +67,17 @@ int __qcom_scm_restore_sec_config(u32 sec_id, u32 ctx_bank_num)
 	return -ENOTSUPP;
 }
 
+int __qcom_scm_ocmem_lock(uint32_t id, uint32_t offset, uint32_t size,
+		uint32_t mode)
+{
+	return -ENOTSUPP;
+}
+
+int __qcom_scm_ocmem_unlock(uint32_t id, uint32_t offset, uint32_t size)
+{
+	return -ENOTSUPP;
+}
+
 bool __qcom_scm_pas_supported(u32 peripheral)
 {
 	return false;
drivers/firmware/qcom_scm.c +39 -0
index 8f43c0b..0e7ce42 100644
@@ -176,6 +176,45 @@ int qcom_scm_restore_sec_config(unsigned sec_id)
 EXPORT_SYMBOL(qcom_scm_restore_sec_config);
 
 /**
+ * qcom_scm_ocmem_lock_available() - is OCMEM lock/unlock interface available
+ */
+bool qcom_scm_ocmem_lock_available(void)
+{
+	return __qcom_scm_is_call_available(QCOM_SCM_OCMEM_SVC,
+			QCOM_SCM_OCMEM_LOCK_CMD);
+}
+EXPORT_SYMBOL(qcom_scm_ocmem_lock_available);
+
+/**
+ * qcom_scm_ocmem_lock() - call OCMEM lock interface to assign an OCMEM
+ * region to the specified initiator
+ *
+ * @id:     tz initiator id
+ * @offset: OCMEM offset
+ * @size:   OCMEM size
+ * @mode:   access mode (WIDE/NARROW)
+ */
+int qcom_scm_ocmem_lock(u32 id, u32 offset, u32 size, u32 mode)
+{
+	return __qcom_scm_ocmem_lock(id, offset, size, mode);
+}
+EXPORT_SYMBOL(qcom_scm_ocmem_lock);
+
+/**
+ * qcom_scm_ocmem_unlock() - call OCMEM unlock interface to release an OCMEM
+ * region from the specified initiator
+ *
+ * @id:     tz initiator id
+ * @offset: OCMEM offset
+ * @size:   OCMEM size
+ */
+int qcom_scm_ocmem_unlock(u32 id, u32 offset, u32 size)
+{
+	return __qcom_scm_ocmem_unlock(id, offset, size);
+}
+EXPORT_SYMBOL(qcom_scm_ocmem_unlock);
+
+/**
  * qcom_scm_pas_supported() - Check if the peripheral authentication service is
  *			      available for the given peripherial
  * @peripheral:	peripheral id
drivers/firmware/qcom_scm.h +7 -0
index 3085616..ec3435e 100644
@@ -41,6 +41,13 @@ extern int __qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
 
 extern int __qcom_scm_restore_sec_config(u32 sec_id, u32 ctx_bank_num);
 
+#define QCOM_SCM_OCMEM_SVC			0xf
+#define QCOM_SCM_OCMEM_LOCK_CMD		0x1
+#define QCOM_SCM_OCMEM_UNLOCK_CMD		0x2
+
+extern int __qcom_scm_ocmem_lock(u32 id, u32 offset, u32 size, u32 mode);
+extern int __qcom_scm_ocmem_unlock(u32 id, u32 offset, u32 size);
+
 #define QCOM_SCM_SVC_PIL		0x2
 #define QCOM_SCM_PAS_INIT_IMAGE_CMD	0x1
 #define QCOM_SCM_PAS_MEM_SETUP_CMD	0x2
include/linux/qcom_scm.h +4 -0
index 7be3d91..beadca4 100644
@@ -35,6 +35,10 @@ extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
 extern bool qcom_scm_restore_sec_config_available(void);
 extern int qcom_scm_restore_sec_config(unsigned sec_id);
 
+extern bool qcom_scm_ocmem_lock_available(void);
+extern int qcom_scm_ocmem_lock(u32 id, u32 offset, u32 size, u32 mode);
+extern int qcom_scm_ocmem_unlock(u32 id, u32 offset, u32 size);
+
 extern bool qcom_scm_pas_supported(u32 peripheral);
 extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size);
 extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size);
Signature · 1 line
2.4.3
author
#8 lore raw

Re: [PATCH 5/5] qcom-scm: add OCMEM lock/unlock interface

Quoted 4 lines · Rob Clark

Needed to enable device access to OCMEM.

Signed-off-by Rob Clark <[email protected]>

---

and similar to the previous patch, considering squashing in:

-----------

include/linux/qcom_scm.h +11 -2
index d3f209d..41ad996 100644
@@ -45,9 +45,19 @@ enum qcom_scm_sec_dev_id {
 extern bool qcom_scm_restore_sec_config_available(void);
 extern int qcom_scm_restore_sec_config(enum qcom_scm_sec_dev_id sec_id);
 
+enum qcom_scm_ocmem_client {
+    QCOM_SCM_OCMEM_UNUSED_ID = 0x0,
+    QCOM_SCM_OCMEM_GRAPHICS_ID,
+    QCOM_SCM_OCMEM_VIDEO_ID,
+    QCOM_SCM_OCMEM_LP_AUDIO_ID,
+    QCOM_SCM_OCMEM_SENSORS_ID,
+    QCOM_SCM_OCMEM_OTHER_OS_ID,
+    QCOM_SCM_OCMEM_DEBUG_ID,
+};
+
 extern bool qcom_scm_ocmem_lock_available(void);
-extern int qcom_scm_ocmem_lock(u32 id, u32 offset, u32 size, u32 mode);
-extern int qcom_scm_ocmem_unlock(u32 id, u32 offset, u32 size);
+extern int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32

offset, u32 size, u32 mode);
+extern int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset, u32 size);
-----------

BR,
-R

Quoted 160 lines
 drivers/firmware/qcom_scm-32.c | 34 ++++++++++++++++++++++++++++++++++
 drivers/firmware/qcom_scm-64.c | 11 +++++++++++
 drivers/firmware/qcom_scm.c    | 39 +++++++++++++++++++++++++++++++++++++++
 drivers/firmware/qcom_scm.h    |  7 +++++++
 include/linux/qcom_scm.h       |  4 ++++
 5 files changed, 95 insertions(+)
drivers/firmware/qcom_scm-32.c +34 -0
index a7bf6d4..dc84771b 100644
@@ -520,6 +520,40 @@ int __qcom_scm_restore_sec_config(u32 sec_id, u32 ctx_bank_num)
        return 0;
 }
 
+int __qcom_scm_ocmem_lock(u32 id, u32 offset, u32 size, u32 mode)
+{
+       struct ocmem_tz_lock {
+               __le32 id;
+               __le32 offset;
+               __le32 size;
+               __le32 mode;
+       } request;
+
+       request.id     = cpu_to_le32(id);
+       request.offset = cpu_to_le32(offset);
+       request.size   = cpu_to_le32(size);
+       request.mode   = cpu_to_le32(mode);
+
+       return qcom_scm_call(QCOM_SCM_OCMEM_SVC, QCOM_SCM_OCMEM_LOCK_CMD,
+                       &request, sizeof(request), NULL, 0);
+}
+
+int __qcom_scm_ocmem_unlock(u32 id, u32 offset, u32 size)
+{
+       struct ocmem_tz_unlock {
+               __le32 id;
+               __le32 offset;
+               __le32 size;
+       } request;
+
+       request.id     = cpu_to_le32(id);
+       request.offset = cpu_to_le32(offset);
+       request.size   = cpu_to_le32(size);
+
+       return qcom_scm_call(QCOM_SCM_OCMEM_SVC, QCOM_SCM_OCMEM_UNLOCK_CMD,
+                       &request, sizeof(request), NULL, 0);
+}
+
 bool __qcom_scm_pas_supported(u32 peripheral)
 {
        __le32 out;
drivers/firmware/qcom_scm-64.c +11 -0
index 7329cf0f..0ca20a3 100644
@@ -67,6 +67,17 @@ int __qcom_scm_restore_sec_config(u32 sec_id, u32 ctx_bank_num)
        return -ENOTSUPP;
 }
 
+int __qcom_scm_ocmem_lock(uint32_t id, uint32_t offset, uint32_t size,
+               uint32_t mode)
+{
+       return -ENOTSUPP;
+}
+
+int __qcom_scm_ocmem_unlock(uint32_t id, uint32_t offset, uint32_t size)
+{
+       return -ENOTSUPP;
+}
+
 bool __qcom_scm_pas_supported(u32 peripheral)
 {
        return false;
drivers/firmware/qcom_scm.c +39 -0
index 8f43c0b..0e7ce42 100644
@@ -176,6 +176,45 @@ int qcom_scm_restore_sec_config(unsigned sec_id)
 EXPORT_SYMBOL(qcom_scm_restore_sec_config);
 
 /**
+ * qcom_scm_ocmem_lock_available() - is OCMEM lock/unlock interface available
+ */
+bool qcom_scm_ocmem_lock_available(void)
+{
+       return __qcom_scm_is_call_available(QCOM_SCM_OCMEM_SVC,
+                       QCOM_SCM_OCMEM_LOCK_CMD);
+}
+EXPORT_SYMBOL(qcom_scm_ocmem_lock_available);
+
+/**
+ * qcom_scm_ocmem_lock() - call OCMEM lock interface to assign an OCMEM
+ * region to the specified initiator
+ *
+ * @id:     tz initiator id
+ * @offset: OCMEM offset
+ * @size:   OCMEM size
+ * @mode:   access mode (WIDE/NARROW)
+ */
+int qcom_scm_ocmem_lock(u32 id, u32 offset, u32 size, u32 mode)
+{
+       return __qcom_scm_ocmem_lock(id, offset, size, mode);
+}
+EXPORT_SYMBOL(qcom_scm_ocmem_lock);
+
+/**
+ * qcom_scm_ocmem_unlock() - call OCMEM unlock interface to release an OCMEM
+ * region from the specified initiator
+ *
+ * @id:     tz initiator id
+ * @offset: OCMEM offset
+ * @size:   OCMEM size
+ */
+int qcom_scm_ocmem_unlock(u32 id, u32 offset, u32 size)
+{
+       return __qcom_scm_ocmem_unlock(id, offset, size);
+}
+EXPORT_SYMBOL(qcom_scm_ocmem_unlock);
+
+/**
  * qcom_scm_pas_supported() - Check if the peripheral authentication service is
  *                           available for the given peripherial
  * @peripheral:        peripheral id
drivers/firmware/qcom_scm.h +7 -0
index 3085616..ec3435e 100644
@@ -41,6 +41,13 @@ extern int __qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
 
 extern int __qcom_scm_restore_sec_config(u32 sec_id, u32 ctx_bank_num);
 
+#define QCOM_SCM_OCMEM_SVC                     0xf
+#define QCOM_SCM_OCMEM_LOCK_CMD                0x1
+#define QCOM_SCM_OCMEM_UNLOCK_CMD              0x2
+
+extern int __qcom_scm_ocmem_lock(u32 id, u32 offset, u32 size, u32 mode);
+extern int __qcom_scm_ocmem_unlock(u32 id, u32 offset, u32 size);
+
 #define QCOM_SCM_SVC_PIL               0x2
 #define QCOM_SCM_PAS_INIT_IMAGE_CMD    0x1
 #define QCOM_SCM_PAS_MEM_SETUP_CMD     0x2
include/linux/qcom_scm.h +4 -1
index 7be3d91..beadca4 100644
@@ -35,6 +35,10 @@ extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
 extern bool qcom_scm_restore_sec_config_available(void);
 extern int qcom_scm_restore_sec_config(unsigned sec_id);
 
+extern bool qcom_scm_ocmem_lock_available(void);
+extern int qcom_scm_ocmem_lock(u32 id, u32 offset, u32 size, u32 mode);
+extern int qcom_scm_ocmem_unlock(u32 id, u32 offset, u32 size);
+
 extern bool qcom_scm_pas_supported(u32 peripheral);
 extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size);
 extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size);
--

2.4.3

author
#9 lore raw

PATCH 1/1 qcom-scm: add OCMEM lock/unlock interface

Needed to enable device access to OCMEM.

Signed-off-by Rob Clark <[email protected]>

---
Note: no objections to the client-id enum on mailing list and positive feedback on ##linux-msm so squashing that part in and re-sending

 drivers/firmware/qcom_scm-32.c | 34 ++++++++++++++++++++++++++++++++++
 drivers/firmware/qcom_scm-64.c | 11 +++++++++++
 drivers/firmware/qcom_scm.c    | 39 +++++++++++++++++++++++++++++++++++++++
 drivers/firmware/qcom_scm.h    |  7 +++++++
 include/linux/qcom_scm.h       | 14 ++++++++++++++
 5 files changed, 105 insertions(+)
drivers/firmware/qcom_scm-32.c +34 -0
index a7bf6d4..dc84771b 100644
@@ -520,6 +520,40 @@ int __qcom_scm_restore_sec_config(u32 sec_id, u32 ctx_bank_num)
 	return 0;
 }
 
+int __qcom_scm_ocmem_lock(u32 id, u32 offset, u32 size, u32 mode)
+{
+	struct ocmem_tz_lock {
+		__le32 id;
+		__le32 offset;
+		__le32 size;
+		__le32 mode;
+	} request;
+
+	request.id     = cpu_to_le32(id);
+	request.offset = cpu_to_le32(offset);
+	request.size   = cpu_to_le32(size);
+	request.mode   = cpu_to_le32(mode);
+
+	return qcom_scm_call(QCOM_SCM_OCMEM_SVC, QCOM_SCM_OCMEM_LOCK_CMD,
+			&request, sizeof(request), NULL, 0);
+}
+
+int __qcom_scm_ocmem_unlock(u32 id, u32 offset, u32 size)
+{
+	struct ocmem_tz_unlock {
+		__le32 id;
+		__le32 offset;
+		__le32 size;
+	} request;
+
+	request.id     = cpu_to_le32(id);
+	request.offset = cpu_to_le32(offset);
+	request.size   = cpu_to_le32(size);
+
+	return qcom_scm_call(QCOM_SCM_OCMEM_SVC, QCOM_SCM_OCMEM_UNLOCK_CMD,
+			&request, sizeof(request), NULL, 0);
+}
+
 bool __qcom_scm_pas_supported(u32 peripheral)
 {
 	__le32 out;
drivers/firmware/qcom_scm-64.c +11 -0
index 7329cf0f..0ca20a3 100644
@@ -67,6 +67,17 @@ int __qcom_scm_restore_sec_config(u32 sec_id, u32 ctx_bank_num)
 	return -ENOTSUPP;
 }
 
+int __qcom_scm_ocmem_lock(uint32_t id, uint32_t offset, uint32_t size,
+		uint32_t mode)
+{
+	return -ENOTSUPP;
+}
+
+int __qcom_scm_ocmem_unlock(uint32_t id, uint32_t offset, uint32_t size)
+{
+	return -ENOTSUPP;
+}
+
 bool __qcom_scm_pas_supported(u32 peripheral)
 {
 	return false;
drivers/firmware/qcom_scm.c +39 -0
index c9c99a3..5c5841d 100644
@@ -176,6 +176,45 @@ int qcom_scm_restore_sec_config(enum qcom_scm_sec_dev_id sec_id)
 EXPORT_SYMBOL(qcom_scm_restore_sec_config);
 
 /**
+ * qcom_scm_ocmem_lock_available() - is OCMEM lock/unlock interface available
+ */
+bool qcom_scm_ocmem_lock_available(void)
+{
+	return __qcom_scm_is_call_available(QCOM_SCM_OCMEM_SVC,
+			QCOM_SCM_OCMEM_LOCK_CMD);
+}
+EXPORT_SYMBOL(qcom_scm_ocmem_lock_available);
+
+/**
+ * qcom_scm_ocmem_lock() - call OCMEM lock interface to assign an OCMEM
+ * region to the specified initiator
+ *
+ * @id:     tz initiator id
+ * @offset: OCMEM offset
+ * @size:   OCMEM size
+ * @mode:   access mode (WIDE/NARROW)
+ */
+int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset, u32 size, u32 mode)
+{
+	return __qcom_scm_ocmem_lock(id, offset, size, mode);
+}
+EXPORT_SYMBOL(qcom_scm_ocmem_lock);
+
+/**
+ * qcom_scm_ocmem_unlock() - call OCMEM unlock interface to release an OCMEM
+ * region from the specified initiator
+ *
+ * @id:     tz initiator id
+ * @offset: OCMEM offset
+ * @size:   OCMEM size
+ */
+int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset, u32 size)
+{
+	return __qcom_scm_ocmem_unlock(id, offset, size);
+}
+EXPORT_SYMBOL(qcom_scm_ocmem_unlock);
+
+/**
  * qcom_scm_pas_supported() - Check if the peripheral authentication service is
  *			      available for the given peripherial
  * @peripheral:	peripheral id
drivers/firmware/qcom_scm.h +7 -0
index 3085616..ec3435e 100644
@@ -41,6 +41,13 @@ extern int __qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
 
 extern int __qcom_scm_restore_sec_config(u32 sec_id, u32 ctx_bank_num);
 
+#define QCOM_SCM_OCMEM_SVC			0xf
+#define QCOM_SCM_OCMEM_LOCK_CMD		0x1
+#define QCOM_SCM_OCMEM_UNLOCK_CMD		0x2
+
+extern int __qcom_scm_ocmem_lock(u32 id, u32 offset, u32 size, u32 mode);
+extern int __qcom_scm_ocmem_unlock(u32 id, u32 offset, u32 size);
+
 #define QCOM_SCM_SVC_PIL		0x2
 #define QCOM_SCM_PAS_INIT_IMAGE_CMD	0x1
 #define QCOM_SCM_PAS_MEM_SETUP_CMD	0x2
include/linux/qcom_scm.h +14 -0
index ee31eec..41ad996 100644
@@ -45,6 +45,20 @@ enum qcom_scm_sec_dev_id {
 extern bool qcom_scm_restore_sec_config_available(void);
 extern int qcom_scm_restore_sec_config(enum qcom_scm_sec_dev_id sec_id);
 
+enum qcom_scm_ocmem_client {
+	QCOM_SCM_OCMEM_UNUSED_ID = 0x0,
+	QCOM_SCM_OCMEM_GRAPHICS_ID,
+	QCOM_SCM_OCMEM_VIDEO_ID,
+	QCOM_SCM_OCMEM_LP_AUDIO_ID,
+	QCOM_SCM_OCMEM_SENSORS_ID,
+	QCOM_SCM_OCMEM_OTHER_OS_ID,
+	QCOM_SCM_OCMEM_DEBUG_ID,
+};
+
+extern bool qcom_scm_ocmem_lock_available(void);
+extern int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset, u32 size, u32 mode);
+extern int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset, u32 size);
+
 extern bool qcom_scm_pas_supported(u32 peripheral);
 extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size);
 extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size);
Signature · 1 line
2.4.3