x86/cpu/intel: enable X86_FEATURE_NONSTOP_TSC_S3 for Merrifield
PATCH 1/1 x86/cpu/intel: enable X86_FEATURE_NONSTOP_TSC_S3 for Merrifield
The Intel Merrifield SoC is a successor of the Intel MID line of SoCs. Let's set the neccessary capability for that chip. See commit c54fdbb2823d (x86: Add cpu capability flag X86_FEATURE_NONSTOP_TSC_S3) for the details.
--- arch/x86/kernel/cpu/intel.c | 1 + 1 file changed, 1 insertion(+)
arch/x86/kernel/cpu/intel.c +1 -0
@@ -97,6 +97,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)switch (c->x86_model) {case 0x27 :/* Penwell */ case 0x35 :/* Cloverview */ +case 0x4a :/* Merrifield */ set_cpu_cap (c,X86_FEATURE_NONSTOP_TSC_S3 );break ;default :
Signature · 1 line
2.5.3
tip-bot for Andy Shevchenko
merge bot[tip:x86/cpufeature] x86/cpu/intel: Enable X86_FEATURE_NONSTOP_TSC_S3 for Merrifield
x86/cpu/intel: Enable X86_FEATURE_NONSTOP_TSC_S3 for Merrifield
Commit-ID: 1cc0166752d598a69f6bb99381d828cbfb5fa9a5 Gitweb: http://git.kernel.org/tip/1cc0166752d598a69f6bb99381d828cbfb5fa9a5 Author: Andy Shevchenko <[email protected]> AuthorDate: Thu, 8 Oct 2015 18:56:26 +0300 Committer: Thomas Gleixner <[email protected]> CommitDate: Sun, 11 Oct 2015 21:07:26 +0200
x86/cpu/intel: Enable X86_FEATURE_NONSTOP_TSC_S3 for Merrifield
The Intel Merrifield SoC is a successor of the Intel MID line of SoCs. Let's set the neccessary capability for that chip. See commit c54fdbb2823d (x86: Add cpu capability flag X86_FEATURE_NONSTOP_TSC_S3) for the details.
--- arch/x86/kernel/cpu/intel.c | 1 + 1 file changed, 1 insertion(+)
arch/x86/kernel/cpu/intel.c +1 -0
@@ -97,6 +97,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)switch (c->x86_model) {case 0x27 :/* Penwell */ case 0x35 :/* Cloverview */ +case 0x4a :/* Merrifield */ set_cpu_cap (c,X86_FEATURE_NONSTOP_TSC_S3 );break ;default :
tip-bot for Andy Shevchenko
merge bot[tip:x86/urgent] x86/cpu/intel: Enable X86_FEATURE_NONSTOP_TSC_S3 for Merrifield
In reply to Andy Shevchenkox86/cpu/intel: Enable X86_FEATURE_NONSTOP_TSC_S3 for Merrifield
Commit-ID: 354dbaa7ff5b53a0ed1c0f7a9773d5953b3a1bb9 Gitweb: http://git.kernel.org/tip/354dbaa7ff5b53a0ed1c0f7a9773d5953b3a1bb9 Author: Andy Shevchenko <[email protected]> AuthorDate: Thu, 8 Oct 2015 18:56:26 +0300 Committer: Thomas Gleixner <[email protected]> CommitDate: Sat, 7 Nov 2015 10:37:30 +0100
x86/cpu/intel: Enable X86_FEATURE_NONSTOP_TSC_S3 for Merrifield
The Intel Merrifield SoC is a successor of the Intel MID line of SoCs. Let's set the neccessary capability for that chip. See commit c54fdbb2823d (x86: Add cpu capability flag X86_FEATURE_NONSTOP_TSC_S3) for the details.
--- arch/x86/kernel/cpu/intel.c | 1 + 1 file changed, 1 insertion(+)
arch/x86/kernel/cpu/intel.c +1 -0
@@ -97,6 +97,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)switch (c->x86_model) {case 0x27 :/* Penwell */ case 0x35 :/* Cloverview */ +case 0x4a :/* Merrifield */ set_cpu_cap (c,X86_FEATURE_NONSTOP_TSC_S3 );break ;default :