clk: iproc: add support for BCM NS, NSP, and NS2
Subsystems (6)
v3 cover clk: iproc: add support for BCM NS, NSP, and NS2
v3 - Added a patch to fix cygnus clk link failures, and added back the DT documentation patches that were removed from v2.
v2 - Added a patch to change the Cygnus clk macros to uppercase, removed the device tree changes from the series (will send out those as an RFC), and other minor changes that Stephen Boyd requested.
This patch series adds support for the Broadcom Northstar, Northstar Plus, and Northstar 2 clocks. Some slight modifications were necessary to clk-iproc-pll to get Northstar and Northstar Plus working, due to differences in register layout. This is the reason why the first patch is necessary. Some more modifications were necessary to clk-iproc-pll to get Northstar 2 working, due to differences in register layout (and resulting fallout in Cygnus and NSP). This is the reason why the sixth and seventh patches are necessary. The fifth patch is clean-up to prevent accidentally forgetting to adjust for the base write errata (which happened a few times, but was caught in internal review).
Thanks,
Jon
PATCH v3 1/10 ARM: cygnus: fix link failures when CONFIG_COMMON_CLK_IPROC is disabled
From: Arnd Bergmann <[email protected]>
When CONFIG_CYGNUS is set but CONFIG_COMMON_CLK_IPROC is disabled, the following link failures are caused:
drivers/built-in.o: In function `cygnus_armpll_init':
:(.init.text+0x1d290): undefined reference to iproc_armpll_setup' drivers/built-in.o: In function cygnus_genpll_clk_init':
:(.init.text+0x1d2c4): undefined reference to iproc_pll_clk_setup' drivers/built-in.o: In function cygnus_lcpll0_clk_init':
:(.init.text+0x1d304): undefined reference to iproc_pll_clk_setup' drivers/built-in.o: In function cygnus_mipipll_clk_init':
:(.init.text+0x1d344): undefined reference to iproc_pll_clk_setup' drivers/built-in.o: In function cygnus_asiu_init':
:(.init.text+0x1d370): undefined reference to `iproc_asiu_setup'
It is fixed it by always selecting COMMON_CLK_IPROC from ARCH_BCM_IPROC, and making COMMON_CLK_IPROC a silent option (thus preventing it from being erroneously disabled by a user).
--- arch/arm/mach-bcm/Kconfig | 2 +- drivers/clk/bcm/Kconfig | 4 +--- 2 files changed, 2 insertions(+), 4 deletions(-)
arch/arm/mach-bcm/Kconfig +1 -1
@@ -14,7 +14,7 @@ config ARCH_BCM_IPROC select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP select ARM_GLOBAL_TIMER - + select COMMON_CLK_IPROC select CLKSRC_MMIO select ARCH_REQUIRE_GPIOLIB select ARM_AMBA
drivers/clk/bcm/Kconfig +1 -3
@@ -9,10 +9,8 @@ config CLK_BCM_KONA in the BCM281xx and BCM21664 families. config COMMON_CLK_IPROC - bool "Broadcom iProc clock support" - depends on ARCH_BCM_IPROC + bool depends on COMMON_CLK - default ARCH_BCM_IPROC help Enable common clock framework support for Broadcom SoCs based on the iProc architecture
Signature · 1 line
1.9.1
Scott Branden
maintainerRe: [PATCH v3 01/10] ARM: cygnus: fix link failures when CONFIG_COMMON_CLK_IPROC is disabled
Jon,
One question below for others to comment on.
Quoted 45 lines · Jon Mason
From: Arnd Bergmann <[email protected]>
When
CONFIG_CYGNUSis set butCONFIG_COMMON_CLK_IPROCis disabled, the following link failures are caused:
drivers/built-in.o: In function `cygnus_armpll_init':
:(.init.text+0x1d290): undefined reference toiproc_armpll_setup' drivers/built-in.o: In functioncygnus_genpll_clk_init':
:(.init.text+0x1d2c4): undefined reference toiproc_pll_clk_setup' drivers/built-in.o: In functioncygnus_lcpll0_clk_init':
:(.init.text+0x1d304): undefined reference toiproc_pll_clk_setup' drivers/built-in.o: In functioncygnus_mipipll_clk_init':
:(.init.text+0x1d344): undefined reference toiproc_pll_clk_setup' drivers/built-in.o: In functioncygnus_asiu_init':
:(.init.text+0x1d370): undefined reference to `iproc_asiu_setup'It is fixed it by always selecting
COMMON_CLK_IPROCfromARCH_BCM_IPROC, and makingCOMMON_CLK_IPROCa silent option (thus preventing it from being erroneously disabled by a user).Signed-off-by Arnd Bergmann <[email protected]>Signed-off-by Jon Mason <[email protected]>--- arch/arm/mach-bcm/Kconfig | 2 +- drivers/clk/bcm/Kconfig | 4 +--- 2 files changed, 2 insertions(+), 4 deletions(-)arch/arm/mach-bcm/Kconfig +1
-1@@ -14,7 +14,7 @@ config ARCH_BCM_IPROC select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP select ARM_GLOBAL_TIMER - + select COMMON_CLK_IPROC select CLKSRC_MMIO select ARCH_REQUIRE_GPIOLIB select ARM_AMBAdrivers/clk/bcm/Kconfig +0
-0
drivers/clk/bcm/Kconfig config CLK_BCM_KONA · line 13
Quoted 7 lines
drivers/clk/bcm/Kconfig +1
-2@@ -9,10 +9,8 @@ config CLK_BCM_KONA in the BCM281xx and BCM21664 families. config COMMON_CLK_IPROC - bool "Broadcom iProc clock support" - depends on ARCH_BCM_IPROC + bool depends on COMMON_CLK
Should these depends on remain? I think COMMON_CLK_IPROC won't work without them.
Quoted 5 lines
drivers/clk/bcm/Kconfig +0
-1- default ARCH_BCM_IPROC help Enable common clock framework support for Broadcom SoCs based on the iProc architecture
Re: [PATCH v3 01/10] ARM: cygnus: fix link failures when CONFIG_COMMON_CLK_IPROC is disabled
Quoted 52 lines · Scott Branden
Jon,
One question below for others to comment on.
Quoted 47 lines · Jon Mason
From: Arnd Bergmann <[email protected]>
When
CONFIG_CYGNUSis set butCONFIG_COMMON_CLK_IPROCis disabled, the following link failures are caused:
drivers/built-in.o: In function `cygnus_armpll_init':
:(.init.text+0x1d290): undefined reference toiproc_armpll_setup' drivers/built-in.o: In functioncygnus_genpll_clk_init':
:(.init.text+0x1d2c4): undefined reference toiproc_pll_clk_setup' drivers/built-in.o: In functioncygnus_lcpll0_clk_init':
:(.init.text+0x1d304): undefined reference toiproc_pll_clk_setup' drivers/built-in.o: In functioncygnus_mipipll_clk_init':
:(.init.text+0x1d344): undefined reference toiproc_pll_clk_setup' drivers/built-in.o: In functioncygnus_asiu_init':
:(.init.text+0x1d370): undefined reference to `iproc_asiu_setup'It is fixed it by always selecting
COMMON_CLK_IPROCfromARCH_BCM_IPROC, and makingCOMMON_CLK_IPROCa silent option (thus preventing it from being erroneously disabled by a user).Signed-off-by Arnd Bergmann <[email protected]>Signed-off-by Jon Mason <[email protected]>--- arch/arm/mach-bcm/Kconfig | 2 +- drivers/clk/bcm/Kconfig | 4 +--- 2 files changed, 2 insertions(+), 4 deletions(-)arch/arm/mach-bcm/Kconfig +1
-1@@ -14,7 +14,7 @@ config ARCH_BCM_IPROC select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP select ARM_GLOBAL_TIMER - + select COMMON_CLK_IPROC select CLKSRC_MMIO select ARCH_REQUIRE_GPIOLIB select ARM_AMBAdrivers/clk/bcm/Kconfig +0
-0@@ -9,10 +9,8 @@ config CLK_BCM_KONA in the BCM281xx and BCM21664 families.
Quoted 7 lines
drivers/clk/bcm/Kconfig config CLK_BCM_KONA · line 13
Quoted 5 lines
drivers/clk/bcm/Kconfig +1
-2config COMMON_CLK_IPROC - bool "Broadcom iProc clock support" - depends on ARCH_BCM_IPROC + bool depends on COMMON_CLKShould these depends on remain? I think
COMMON_CLK_IPROCwon't work without them.
The ones that were removed were not necessary (as ARCH_BCM_IPROC now selects it). I left the "depends on COMMON_CLK" in the off chance that the dependency chain gets broken some how (as ARCH_BCM_IPROC is not selecting COMMON_CLK directly, but it is being selected by ARCH_MULTIPLATFORM).
Thanks,
Jon
Quoted 6 lines
Quoted 5 lines
drivers/clk/bcm/Kconfig +0
-1- default ARCH_BCM_IPROC help Enable common clock framework support for Broadcom SoCs based on the iProc architecture
Re: [PATCH v3 01/10] ARM: cygnus: fix link failures when CONFIG_COMMON_CLK_IPROC is disabled
In reply to Jon MasonQuoted 46 lines · Jon Mason
From: Arnd Bergmann <[email protected]>
When
CONFIG_CYGNUSis set butCONFIG_COMMON_CLK_IPROCis disabled, the following link failures are caused:
drivers/built-in.o: In function `cygnus_armpll_init':
:(.init.text+0x1d290): undefined reference toiproc_armpll_setup' drivers/built-in.o: In functioncygnus_genpll_clk_init':
:(.init.text+0x1d2c4): undefined reference toiproc_pll_clk_setup' drivers/built-in.o: In functioncygnus_lcpll0_clk_init':
:(.init.text+0x1d304): undefined reference toiproc_pll_clk_setup' drivers/built-in.o: In functioncygnus_mipipll_clk_init':
:(.init.text+0x1d344): undefined reference toiproc_pll_clk_setup' drivers/built-in.o: In functioncygnus_asiu_init':
:(.init.text+0x1d370): undefined reference to `iproc_asiu_setup'It is fixed it by always selecting
COMMON_CLK_IPROCfromARCH_BCM_IPROC, and makingCOMMON_CLK_IPROCa silent option (thus preventing it from being erroneously disabled by a user).Signed-off-by Arnd Bergmann <[email protected]>Signed-off-by Jon Mason <[email protected]>--- arch/arm/mach-bcm/Kconfig | 2 +- drivers/clk/bcm/Kconfig | 4 +--- 2 files changed, 2 insertions(+), 4 deletions(-)arch/arm/mach-bcm/Kconfig +1
-1@@ -14,7 +14,7 @@ config ARCH_BCM_IPROC select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP select ARM_GLOBAL_TIMER - + select COMMON_CLK_IPROC select CLKSRC_MMIO select ARCH_REQUIRE_GPIOLIB select ARM_AMBAdrivers/clk/bcm/Kconfig +0
-0@@ -9,10 +9,8 @@ config CLK_BCM_KONA in the BCM281xx and BCM21664 families.
drivers/clk/bcm/Kconfig config CLK_BCM_KONA · line 16
Quoted 10 lines
drivers/clk/bcm/Kconfig +1
-3config COMMON_CLK_IPROC - bool "Broadcom iProc clock support" - depends on ARCH_BCM_IPROC + bool depends on COMMON_CLK - default ARCH_BCM_IPROC help Enable common clock framework support for Broadcom SoCs based on the iProc architecture
A help text is not needed for a silent option.
Hauke
Stephen Boyd
AppliedRe: [PATCH v3 01/10] ARM: cygnus: fix link failures when CONFIG_COMMON_CLK_IPROC is disabled
In reply to Jon Masondrivers/clk/bcm/Kconfig config CLK_BCM_KONA · line 13
Quoted 10 lines · Jon Mason
drivers/clk/bcm/Kconfig +0
-2@@ -9,10 +9,8 @@ config CLK_BCM_KONA in the BCM281xx and BCM21664 families. config COMMON_CLK_IPROC - bool "Broadcom iProc clock support" - depends on ARCH_BCM_IPROC
Another patch added COMPILE_TEST here, so I've removed COMPILE_TEST now.
Applied to clk-next.
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH v3 2/10 clk: cygnus: Convert all macros to all caps
In reply to Jon MasonThe macros that are being used to initialize the values of the clk structures should be all caps. Find and replace all of them with their relevant counterparts.
--- drivers/clk/bcm/clk-cygnus.c | 146 +++++++++++++++++++++---------------------- 1 file changed, 73 insertions(+), 73 deletions(-)
drivers/clk/bcm/clk-cygnus.c +73 -73
@@ -23,28 +23,28 @@#include <dt-bindings/clock/bcm-cygnus.h> #include "clk-iproc.h" -#define reg_val (o, s, w) { .offset = o, .shift = s, .width = w, } +#define REG_VAL (o, s, w) { .offset = o, .shift = s, .width = w, } -#define aon_val (o, pw, ps, is) { .offset = o, .pwr_width = pw, \ +#define AON_VAL (o, pw, ps, is) { .offset = o, .pwr_width = pw, \ .pwr_shift = ps, .iso_shift = is } -#define sw_ctrl_val (o, s) { .offset = o, .shift = s, } +#define SW_CTRL_VAL (o, s) { .offset = o, .shift = s, } -#define asiu_div_val (o, es, hs, hw, ls, lw) \ +#define ASIU_DIV_VAL (o, es, hs, hw, ls, lw) \ { .offset = o, .en_shift = es, .high_shift = hs, \ .high_width = hw, .low_shift = ls, .low_width = lw } -#define reset_val (o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \ +#define RESET_VAL (o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \ .reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \ .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \ .ka_width = kaw } -#define vco_ctrl_val (uo, lo) { .u_offset = uo, .l_offset = lo } +#define VCO_CTRL_VAL (uo, lo) { .u_offset = uo, .l_offset = lo } -#define enable_val (o, es, hs, bs) { .offset = o, .enable_shift = es, \ +#define ENABLE_VAL (o, es, hs, bs) { .offset = o, .enable_shift = es, \ .hold_shift = hs, .bypass_shift = bs } -#define asiu_gate_val (o, es) { .offset = o, .en_shift = es } +#define ASIU_GATE_VAL (o, es) { .offset = o, .en_shift = es }static void __init cygnus_armpll_init (struct device_node *node) {
@@ -55,52 +55,52 @@ CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init);static const struct iproc_pll_ctrl genpll = { .flags =IPROC_CLK_AON |IPROC_CLK_PLL_HAS_NDIV_FRAC |IPROC_CLK_PLL_NEEDS_SW_CFG , - .aon =aon_val (0x0 ,2 ,1 ,0 ), - .reset =reset_val (0x0 ,11 ,10 ,4 ,3 ,0 ,4 ,7 ,3 ), - .sw_ctrl =sw_ctrl_val (0x10 ,31 ), - .ndiv_int =reg_val (0x10 ,20 ,10 ), - .ndiv_frac =reg_val (0x10 ,0 ,20 ), - .pdiv =reg_val (0x14 ,0 ,4 ), - .vco_ctrl =vco_ctrl_val (0x18 ,0x1c ), - .status =reg_val (0x28 ,12 ,1 ), + .aon =AON_VAL (0x0 ,2 ,1 ,0 ), + .reset =RESET_VAL (0x0 ,11 ,10 ,4 ,3 ,0 ,4 ,7 ,3 ), + .sw_ctrl =SW_CTRL_VAL (0x10 ,31 ), + .ndiv_int =REG_VAL (0x10 ,20 ,10 ), + .ndiv_frac =REG_VAL (0x10 ,0 ,20 ), + .pdiv =REG_VAL (0x14 ,0 ,4 ), + .vco_ctrl =VCO_CTRL_VAL (0x18 ,0x1c ), + .status =REG_VAL (0x28 ,12 ,1 ), };static const struct iproc_clk_ctrl genpll_clk[] = { [BCM_CYGNUS_GENPLL_AXI21_CLK ] = { .channel =BCM_CYGNUS_GENPLL_AXI21_CLK , .flags =IPROC_CLK_AON , - .enable =enable_val (0x4 ,6 ,0 ,12 ), - .mdiv =reg_val (0x20 ,0 ,8 ), + .enable =ENABLE_VAL (0x4 ,6 ,0 ,12 ), + .mdiv =REG_VAL (0x20 ,0 ,8 ), }, [BCM_CYGNUS_GENPLL_250MHZ_CLK ] = { .channel =BCM_CYGNUS_GENPLL_250MHZ_CLK , .flags =IPROC_CLK_AON , - .enable =enable_val (0x4 ,7 ,1 ,13 ), - .mdiv =reg_val (0x20 ,10 ,8 ), + .enable =ENABLE_VAL (0x4 ,7 ,1 ,13 ), + .mdiv =REG_VAL (0x20 ,10 ,8 ), }, [BCM_CYGNUS_GENPLL_IHOST_SYS_CLK ] = { .channel =BCM_CYGNUS_GENPLL_IHOST_SYS_CLK , .flags =IPROC_CLK_AON , - .enable =enable_val (0x4 ,8 ,2 ,14 ), - .mdiv =reg_val (0x20 ,20 ,8 ), + .enable =ENABLE_VAL (0x4 ,8 ,2 ,14 ), + .mdiv =REG_VAL (0x20 ,20 ,8 ), }, [BCM_CYGNUS_GENPLL_ENET_SW_CLK ] = { .channel =BCM_CYGNUS_GENPLL_ENET_SW_CLK , .flags =IPROC_CLK_AON , - .enable =enable_val (0x4 ,9 ,3 ,15 ), - .mdiv =reg_val (0x24 ,0 ,8 ), + .enable =ENABLE_VAL (0x4 ,9 ,3 ,15 ), + .mdiv =REG_VAL (0x24 ,0 ,8 ), }, [BCM_CYGNUS_GENPLL_AUDIO_125_CLK ] = { .channel =BCM_CYGNUS_GENPLL_AUDIO_125_CLK , .flags =IPROC_CLK_AON , - .enable =enable_val (0x4 ,10 ,4 ,16 ), - .mdiv =reg_val (0x24 ,10 ,8 ), + .enable =ENABLE_VAL (0x4 ,10 ,4 ,16 ), + .mdiv =REG_VAL (0x24 ,10 ,8 ), }, [BCM_CYGNUS_GENPLL_CAN_CLK ] = { .channel =BCM_CYGNUS_GENPLL_CAN_CLK , .flags =IPROC_CLK_AON , - .enable =enable_val (0x4 ,11 ,5 ,17 ), - .mdiv =reg_val (0x24 ,20 ,8 ), + .enable =ENABLE_VAL (0x4 ,11 ,5 ,17 ), + .mdiv =REG_VAL (0x24 ,20 ,8 ), }, };
@@ -113,51 +113,51 @@ CLK_OF_DECLARE(cygnus_genpll, "brcm,cygnus-genpll", cygnus_genpll_clk_init);static const struct iproc_pll_ctrl lcpll0 = { .flags =IPROC_CLK_AON |IPROC_CLK_PLL_NEEDS_SW_CFG , - .aon =aon_val (0x0 ,2 ,5 ,4 ), - .reset =reset_val (0x0 ,31 ,30 ,27 ,3 ,23 ,4 ,19 ,4 ), - .sw_ctrl =sw_ctrl_val (0x4 ,31 ), - .ndiv_int =reg_val (0x4 ,16 ,10 ), - .pdiv =reg_val (0x4 ,26 ,4 ), - .vco_ctrl =vco_ctrl_val (0x10 ,0x14 ), - .status =reg_val (0x18 ,12 ,1 ), + .aon =AON_VAL (0x0 ,2 ,5 ,4 ), + .reset =RESET_VAL (0x0 ,31 ,30 ,27 ,3 ,23 ,4 ,19 ,4 ), + .sw_ctrl =SW_CTRL_VAL (0x4 ,31 ), + .ndiv_int =REG_VAL (0x4 ,16 ,10 ), + .pdiv =REG_VAL (0x4 ,26 ,4 ), + .vco_ctrl =VCO_CTRL_VAL (0x10 ,0x14 ), + .status =REG_VAL (0x18 ,12 ,1 ), };static const struct iproc_clk_ctrl lcpll0_clk[] = { [BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK ] = { .channel =BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK , .flags =IPROC_CLK_AON , - .enable =enable_val (0x0 ,7 ,1 ,13 ), - .mdiv =reg_val (0x8 ,0 ,8 ), + .enable =ENABLE_VAL (0x0 ,7 ,1 ,13 ), + .mdiv =REG_VAL (0x8 ,0 ,8 ), }, [BCM_CYGNUS_LCPLL0_DDR_PHY_CLK ] = { .channel =BCM_CYGNUS_LCPLL0_DDR_PHY_CLK , .flags =IPROC_CLK_AON , - .enable =enable_val (0x0 ,8 ,2 ,14 ), - .mdiv =reg_val (0x8 ,10 ,8 ), + .enable =ENABLE_VAL (0x0 ,8 ,2 ,14 ), + .mdiv =REG_VAL (0x8 ,10 ,8 ), }, [BCM_CYGNUS_LCPLL0_SDIO_CLK ] = { .channel =BCM_CYGNUS_LCPLL0_SDIO_CLK , .flags =IPROC_CLK_AON , - .enable =enable_val (0x0 ,9 ,3 ,15 ), - .mdiv =reg_val (0x8 ,20 ,8 ), + .enable =ENABLE_VAL (0x0 ,9 ,3 ,15 ), + .mdiv =REG_VAL (0x8 ,20 ,8 ), }, [BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK ] = { .channel =BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK , .flags =IPROC_CLK_AON , - .enable =enable_val (0x0 ,10 ,4 ,16 ), - .mdiv =reg_val (0xc ,0 ,8 ), + .enable =ENABLE_VAL (0x0 ,10 ,4 ,16 ), + .mdiv =REG_VAL (0xc ,0 ,8 ), }, [BCM_CYGNUS_LCPLL0_SMART_CARD_CLK ] = { .channel =BCM_CYGNUS_LCPLL0_SMART_CARD_CLK , .flags =IPROC_CLK_AON , - .enable =enable_val (0x0 ,11 ,5 ,17 ), - .mdiv =reg_val (0xc ,10 ,8 ), + .enable =ENABLE_VAL (0x0 ,11 ,5 ,17 ), + .mdiv =REG_VAL (0xc ,10 ,8 ), }, [BCM_CYGNUS_LCPLL0_CH5_UNUSED ] = { .channel =BCM_CYGNUS_LCPLL0_CH5_UNUSED , .flags =IPROC_CLK_AON , - .enable =enable_val (0x0 ,12 ,6 ,18 ), - .mdiv =reg_val (0xc ,20 ,8 ), + .enable =ENABLE_VAL (0x0 ,12 ,6 ,18 ), + .mdiv =REG_VAL (0xc ,20 ,8 ), }, };
@@ -189,52 +189,52 @@ static const struct iproc_pll_vco_param mipipll_vco_params[] = {static const struct iproc_pll_ctrl mipipll = { .flags =IPROC_CLK_PLL_ASIU |IPROC_CLK_PLL_HAS_NDIV_FRAC |IPROC_CLK_NEEDS_READ_BACK , - .aon =aon_val (0x0 ,4 ,17 ,16 ), - .asiu =asiu_gate_val (0x0 ,3 ), - .reset =reset_val (0x0 ,11 ,10 ,4 ,3 ,0 ,4 ,7 ,4 ), - .ndiv_int =reg_val (0x10 ,20 ,10 ), - .ndiv_frac =reg_val (0x10 ,0 ,20 ), - .pdiv =reg_val (0x14 ,0 ,4 ), - .vco_ctrl =vco_ctrl_val (0x18 ,0x1c ), - .status =reg_val (0x28 ,12 ,1 ), + .aon =AON_VAL (0x0 ,4 ,17 ,16 ), + .asiu =ASIU_GATE_VAL (0x0 ,3 ), + .reset =RESET_VAL (0x0 ,11 ,10 ,4 ,3 ,0 ,4 ,7 ,4 ), + .ndiv_int =REG_VAL (0x10 ,20 ,10 ), + .ndiv_frac =REG_VAL (0x10 ,0 ,20 ), + .pdiv =REG_VAL (0x14 ,0 ,4 ), + .vco_ctrl =VCO_CTRL_VAL (0x18 ,0x1c ), + .status =REG_VAL (0x28 ,12 ,1 ), };static const struct iproc_clk_ctrl mipipll_clk[] = { [BCM_CYGNUS_MIPIPLL_CH0_UNUSED ] = { .channel =BCM_CYGNUS_MIPIPLL_CH0_UNUSED , .flags =IPROC_CLK_NEEDS_READ_BACK , - .enable =enable_val (0x4 ,12 ,6 ,18 ), - .mdiv =reg_val (0x20 ,0 ,8 ), + .enable =ENABLE_VAL (0x4 ,12 ,6 ,18 ), + .mdiv =REG_VAL (0x20 ,0 ,8 ), }, [BCM_CYGNUS_MIPIPLL_CH1_LCD ] = { .channel =BCM_CYGNUS_MIPIPLL_CH1_LCD , .flags =IPROC_CLK_NEEDS_READ_BACK , - .enable =enable_val (0x4 ,13 ,7 ,19 ), - .mdiv =reg_val (0x20 ,10 ,8 ), + .enable =ENABLE_VAL (0x4 ,13 ,7 ,19 ), + .mdiv =REG_VAL (0x20 ,10 ,8 ), }, [BCM_CYGNUS_MIPIPLL_CH2_V3D ] = { .channel =BCM_CYGNUS_MIPIPLL_CH2_V3D , .flags =IPROC_CLK_NEEDS_READ_BACK , - .enable =enable_val (0x4 ,14 ,8 ,20 ), - .mdiv =reg_val (0x20 ,20 ,8 ), + .enable =ENABLE_VAL (0x4 ,14 ,8 ,20 ), + .mdiv =REG_VAL (0x20 ,20 ,8 ), }, [BCM_CYGNUS_MIPIPLL_CH3_UNUSED ] = { .channel =BCM_CYGNUS_MIPIPLL_CH3_UNUSED , .flags =IPROC_CLK_NEEDS_READ_BACK , - .enable =enable_val (0x4 ,15 ,9 ,21 ), - .mdiv =reg_val (0x24 ,0 ,8 ), + .enable =ENABLE_VAL (0x4 ,15 ,9 ,21 ), + .mdiv =REG_VAL (0x24 ,0 ,8 ), }, [BCM_CYGNUS_MIPIPLL_CH4_UNUSED ] = { .channel =BCM_CYGNUS_MIPIPLL_CH4_UNUSED , .flags =IPROC_CLK_NEEDS_READ_BACK , - .enable =enable_val (0x4 ,16 ,10 ,22 ), - .mdiv =reg_val (0x24 ,10 ,8 ), + .enable =ENABLE_VAL (0x4 ,16 ,10 ,22 ), + .mdiv =REG_VAL (0x24 ,10 ,8 ), }, [BCM_CYGNUS_MIPIPLL_CH5_UNUSED ] = { .channel =BCM_CYGNUS_MIPIPLL_CH5_UNUSED , .flags =IPROC_CLK_NEEDS_READ_BACK , - .enable =enable_val (0x4 ,17 ,11 ,23 ), - .mdiv =reg_val (0x24 ,20 ,8 ), + .enable =ENABLE_VAL (0x4 ,17 ,11 ,23 ), + .mdiv =REG_VAL (0x24 ,20 ,8 ), }, };
@@ -247,15 +247,15 @@ static void __init cygnus_mipipll_clk_init(struct device_node *node)CLK_OF_DECLARE (cygnus_mipipll,"brcm,cygnus-mipipll" , cygnus_mipipll_clk_init);static const struct iproc_asiu_div asiu_div[] = { - [BCM_CYGNUS_ASIU_KEYPAD_CLK ] =asiu_div_val (0x0 ,31 ,16 ,10 ,0 ,10 ), - [BCM_CYGNUS_ASIU_ADC_CLK ] =asiu_div_val (0x4 ,31 ,16 ,10 ,0 ,10 ), - [BCM_CYGNUS_ASIU_PWM_CLK ] =asiu_div_val (0x8 ,31 ,16 ,10 ,0 ,10 ), + [BCM_CYGNUS_ASIU_KEYPAD_CLK ] =ASIU_DIV_VAL (0x0 ,31 ,16 ,10 ,0 ,10 ), + [BCM_CYGNUS_ASIU_ADC_CLK ] =ASIU_DIV_VAL (0x4 ,31 ,16 ,10 ,0 ,10 ), + [BCM_CYGNUS_ASIU_PWM_CLK ] =ASIU_DIV_VAL (0x8 ,31 ,16 ,10 ,0 ,10 ), };static const struct iproc_asiu_gate asiu_gate[] = { - [BCM_CYGNUS_ASIU_KEYPAD_CLK ] =asiu_gate_val (0x0 ,7 ), - [BCM_CYGNUS_ASIU_ADC_CLK ] =asiu_gate_val (0x0 ,9 ), - [BCM_CYGNUS_ASIU_PWM_CLK ] =asiu_gate_val (IPROC_CLK_INVALID_OFFSET ,0 ), + [BCM_CYGNUS_ASIU_KEYPAD_CLK ] =ASIU_GATE_VAL (0x0 ,7 ), + [BCM_CYGNUS_ASIU_ADC_CLK ] =ASIU_GATE_VAL (0x0 ,9 ), + [BCM_CYGNUS_ASIU_PWM_CLK ] =ASIU_GATE_VAL (IPROC_CLK_INVALID_OFFSET ,0 ), };static void __init cygnus_asiu_init (struct device_node *node)
Signature · 1 line
1.9.1
Stephen Boyd
AppliedRe: [PATCH v3 02/10] clk: cygnus: Convert all macros to all caps
Quoted 6 lines · Jon Mason
The macros that are being used to initialize the values of the clk structures should be all caps. Find and replace all of them with their relevant counterparts.
Signed-off-by Jon Mason <[email protected]>---
Applied to clk-next
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH v3 3/10 clk: iproc: Add PWRCTRL support
In reply to Jon MasonSome iProc SoC clocks use a different way to control clock power, via the PWRDWN bit in the PLL control register. Since the PLL control register is used to access the PWRDWN bit, there is no need for the pwr_base when this is being used. A new flag, IPROC_CLK_EMBED_PWRCTRL, has been added to identify this usage. We can use the AON interface to write the values to enable/disable PWRDOWN.
--- drivers/clk/bcm/clk-iproc-pll.c | 55 ++++++++++++++++++++++++++++------------- drivers/clk/bcm/clk-iproc.h | 6 +++++ 2 files changed, 44 insertions(+), 17 deletions(-)
drivers/clk/bcm/clk-iproc-pll.c +38 -17
@@ -148,14 +148,25 @@ static void __pll_disable(struct iproc_pll *pll)writel (val, pll->asiu_base + ctrl->asiu.offset); } -/* latch input value so core power can be shut down */ - val =readl (pll->pwr_base + ctrl->aon.offset); - val |= (1 << ctrl->aon.iso_shift); -writel (val, pll->pwr_base + ctrl->aon.offset); - -/* power down the core */ - val &= ~(bit_mask (ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); -writel (val, pll->pwr_base + ctrl->aon.offset); +if (ctrl->flags &IPROC_CLK_EMBED_PWRCTRL ) { + val =readl (pll->pll_base + ctrl->aon.offset); + val |= (bit_mask (ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); +writel (val, pll->pll_base + ctrl->aon.offset); + +if (unlikely (ctrl->flags &IPROC_CLK_NEEDS_READ_BACK )) +readl (pll->pll_base + ctrl->aon.offset); + } + +if (pll->pwr_base) { +/* latch input value so core power can be shut down */ + val =readl (pll->pwr_base + ctrl->aon.offset); + val |= (1 << ctrl->aon.iso_shift); +writel (val, pll->pwr_base + ctrl->aon.offset); + +/* power down the core */ + val &= ~(bit_mask (ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); +writel (val, pll->pwr_base + ctrl->aon.offset); + } }static int __pll_enable (struct iproc_pll *pll)
@@ -163,11 +174,22 @@ static int __pll_enable(struct iproc_pll *pll)const struct iproc_pll_ctrl *ctrl = pll->ctrl;u32 val; -/* power up the PLL and make sure it's not latched */ - val =readl (pll->pwr_base + ctrl->aon.offset); - val |=bit_mask (ctrl->aon.pwr_width) << ctrl->aon.pwr_shift; - val &= ~(1 << ctrl->aon.iso_shift); -writel (val, pll->pwr_base + ctrl->aon.offset); +if (ctrl->flags &IPROC_CLK_EMBED_PWRCTRL ) { + val =readl (pll->pll_base + ctrl->aon.offset); + val &= ~(bit_mask (ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); +writel (val, pll->pll_base + ctrl->aon.offset); + +if (unlikely (ctrl->flags &IPROC_CLK_NEEDS_READ_BACK )) +readl (pll->pll_base + ctrl->aon.offset); + } + +if (pll->pwr_base) { +/* power up the PLL and make sure it's not latched */ + val =readl (pll->pwr_base + ctrl->aon.offset); + val |=bit_mask (ctrl->aon.pwr_width) << ctrl->aon.pwr_shift; + val &= ~(1 << ctrl->aon.iso_shift); +writel (val, pll->pwr_base + ctrl->aon.offset); + }/* certain PLLs also need to be ungated from the ASIU top level */ if (ctrl->flags &IPROC_CLK_PLL_ASIU ) {
@@ -610,9 +632,8 @@ void __init iproc_pll_clk_setup(struct device_node *node,if (WARN_ON (!pll->pll_base)) goto err_pll_iomap; +/* Some SoCs do not require the pwr_base, thus failing is not fatal */ pll->pwr_base =of_iomap (node,1 ); -if (WARN_ON (!pll->pwr_base)) - goto err_pwr_iomap;/* some PLLs require gating control at the top ASIU level */ if (pll_ctrl->flags &IPROC_CLK_PLL_ASIU ) {
@@ -695,9 +716,9 @@ err_pll_register:iounmap (pll->asiu_base); err_asiu_iomap: -iounmap (pll->pwr_base); +if (pll->pwr_base) +iounmap (pll->pwr_base); -err_pwr_iomap:iounmap (pll->pll_base); err_pll_iomap:
drivers/clk/bcm/clk-iproc.h +6 -0
@@ -49,6 +49,12 @@#define IPROC_CLK_PLL_NEEDS_SW_CFG BIT(4)/* +* Some PLLs use a different way to control clock power, via the PWRDWN bit in +* the PLL control register +*/ +#define IPROC_CLK_EMBED_PWRCTRL BIT(5) + +/* * Parameters for VCO frequency configuration * * VCO frequency =
Signature · 1 line
1.9.1
Stephen Boyd
AppliedRe: [PATCH v3 03/10] clk: iproc: Add PWRCTRL support
Quoted 9 lines · Jon Mason
Some iProc SoC clocks use a different way to control clock power, via the PWRDWN bit in the PLL control register. Since the PLL control register is used to access the PWRDWN bit, there is no need for the
pwr_basewhen this is being used. A new flag,IPROC_CLK_EMBED_PWRCTRL, has been added to identify this usage. We can use the AON interface to write the values to enable/disable PWRDOWN.Signed-off-by Jon Mason <[email protected]>---
Applied to clk-next +
---8<----
drivers/clk/bcm/clk-iproc-pll.c +2 -2
@@ -150,7 +150,7 @@ static void __pll_disable(struct iproc_pll *pll)if (ctrl->flags &IPROC_CLK_EMBED_PWRCTRL ) { val =readl (pll->pll_base + ctrl->aon.offset); - val |= (bit_mask (ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); + val |=bit_mask (ctrl->aon.pwr_width) << ctrl->aon.pwr_shift;writel (val, pll->pll_base + ctrl->aon.offset);if (unlikely (ctrl->flags &IPROC_CLK_NEEDS_READ_BACK ))
@@ -160,7 +160,7 @@ static void __pll_disable(struct iproc_pll *pll)if (pll->pwr_base) {/* latch input value so core power can be shut down */ val =readl (pll->pwr_base + ctrl->aon.offset); - val |= (1 << ctrl->aon.iso_shift); + val |=1 << ctrl->aon.iso_shift;writel (val, pll->pwr_base + ctrl->aon.offset);/* power down the core */
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH v3 4/10 clk: nsp: add clock support for Broadcom Northstar Plus SoC
In reply to Jon MasonThe Broadcom Northstar Plus SoC is architected under the iProc architecture. It has the following PLLs: ARMPLL, GENPLL, LCPLL0, all derived from an onboard crystal.
--- drivers/clk/bcm/Makefile | 2 + drivers/clk/bcm/clk-nsp.c | 135 ++++++++++++++++++++++++++++++++++++ include/dt-bindings/clock/bcm-nsp.h | 51 ++++++++++++++ 3 files changed, 188 insertions(+) create mode 100644 drivers/clk/bcm/clk-nsp.c create mode 100644 include/dt-bindings/clock/bcm-nsp.h
drivers/clk/bcm/Makefile +2 -0
@@ -4,3 +4,5 @@ obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o clk-iproc-asiu.o obj-$(CONFIG_ARCH_BCM_CYGNUS) += clk-cygnus.o +obj-$(CONFIG_ARCH_BCM_NSP) += clk-nsp.o +obj-$(CONFIG_ARCH_BCM_5301X) += clk-nsp.o
drivers/clk/bcm/clk-nsp.c new file +135 -0
135 lines not on this page · raw message
include/dt-bindings/clock/bcm-nsp.h new file +51 -0
51 lines not on this page · raw message
Signature · 1 line
1.9.1
Scott Branden
maintainerRe: [PATCH v3 04/10] clk: nsp: add clock support for Broadcom Northstar Plus SoC
Jon,
Review below.
Quoted 1 line · Jon Mason
The Broadcom Northstar Plus SoC is architected under the iProc
Based on changes in Makefile below - should this be for Northstar and Northstar Plus?
Quoted 22 lines
architecture. It has the following PLLs: ARMPLL, GENPLL, LCPLL0, all derived from an onboard crystal.
Signed-off-by Jon Mason <[email protected]>--- drivers/clk/bcm/Makefile | 2 + drivers/clk/bcm/clk-nsp.c | 135 ++++++++++++++++++++++++++++++++++++ include/dt-bindings/clock/bcm-nsp.h | 51 ++++++++++++++ 3 files changed, 188 insertions(+)create mode 100644
drivers/clk/bcm/clk-nsp.ccreate mode 100644include/dt-bindings/clock/bcm-nsp.hdrivers/clk/bcm/Makefile +2
-0@@ -4,3 +4,5 @@ obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o clk-iproc-asiu.o obj-$(CONFIG_ARCH_BCM_CYGNUS) += clk-cygnus.o +obj-$(CONFIG_ARCH_BCM_NSP) += clk-nsp.o +obj-$(CONFIG_ARCH_BCM_5301X) += clk-nsp.o
Re: [PATCH v3 04/10] clk: nsp: add clock support for Broadcom Northstar Plus SoC
Quoted 9 lines · Scott Branden
Jon,
Review below.
Quoted 1 line · Jon Mason
The Broadcom Northstar Plus SoC is architected under the iProc
Based on changes in
Makefilebelow - should this be for Northstar and Northstar Plus?
Yes, that would be more accurate (or the 5301x/4708 verbage we are using now in Linux for that SoC family). If there is the need for another version of this patch, I'll fix it up.
Thanks,
Jon
Quoted 24 lines
Quoted 23 lines
architecture. It has the following PLLs: ARMPLL, GENPLL, LCPLL0, all derived from an onboard crystal.
Signed-off-by Jon Mason <[email protected]>--- drivers/clk/bcm/Makefile | 2 + drivers/clk/bcm/clk-nsp.c | 135 ++++++++++++++++++++++++++++++++++++ include/dt-bindings/clock/bcm-nsp.h | 51 ++++++++++++++ 3 files changed, 188 insertions(+) create mode 100644 drivers/clk/bcm/clk-nsp.c create mode 100644 include/dt-bindings/clock/bcm-nsp.hdrivers/clk/bcm/Makefile +2
-0@@ -4,3 +4,5 @@ obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o clk-iproc-asiu.o obj-$(CONFIG_ARCH_BCM_CYGNUS) += clk-cygnus.o +obj-$(CONFIG_ARCH_BCM_NSP) += clk-nsp.o +obj-$(CONFIG_ARCH_BCM_5301X) += clk-nsp.o
Stephen Boyd
AppliedRe: [PATCH v3 04/10] clk: nsp: add clock support for Broadcom Northstar Plus SoC
In reply to Jon MasonQuoted 6 lines · Jon Mason
The Broadcom Northstar Plus SoC is architected under the iProc architecture. It has the following PLLs: ARMPLL, GENPLL, LCPLL0, all derived from an onboard crystal.
Signed-off-by Jon Mason <[email protected]>---
Applied to clk-iproc
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH v3 5/10 clk: iproc: Add PLL base write function
In reply to Jon MasonAll writes to the PLL base address must be flushed if the IPROC_CLK_NEEDS_READ_BACK flag is set. If we add a function to make the necessary write and reads, we can make sure that any future code which makes PLL base writes will do the correct thing.
--- drivers/clk/bcm/clk-iproc-pll.c | 80 +++++++++++++++++------------------------ 1 file changed, 33 insertions(+), 47 deletions(-)
drivers/clk/bcm/clk-iproc-pll.c +33 -47
@@ -137,6 +137,18 @@ static int pll_wait_for_lock(struct iproc_pll *pll)return -EIO ; } +static void iproc_pll_write (const struct iproc_pll *pll,void __iomem *base, +const u32 offset,u32 val) +{ +const struct iproc_pll_ctrl *ctrl = pll->ctrl; + +writel (val, base + offset); + +if (unlikely (ctrl->flags &IPROC_CLK_NEEDS_READ_BACK && + base == pll->pll_base)) + val =readl (base + offset); +} +static void __pll_disable (struct iproc_pll *pll) {const struct iproc_pll_ctrl *ctrl = pll->ctrl;
@@ -145,27 +157,24 @@ static void __pll_disable(struct iproc_pll *pll)if (ctrl->flags &IPROC_CLK_PLL_ASIU ) { val =readl (pll->asiu_base + ctrl->asiu.offset); val &= ~(1 << ctrl->asiu.en_shift); -writel (val, pll->asiu_base + ctrl->asiu.offset); +iproc_pll_write (pll, pll->asiu_base, ctrl->asiu.offset, val); }if (ctrl->flags &IPROC_CLK_EMBED_PWRCTRL ) { val =readl (pll->pll_base + ctrl->aon.offset); val |= (bit_mask (ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); -writel (val, pll->pll_base + ctrl->aon.offset); - -if (unlikely (ctrl->flags &IPROC_CLK_NEEDS_READ_BACK )) -readl (pll->pll_base + ctrl->aon.offset); +iproc_pll_write (pll, pll->pll_base, ctrl->aon.offset, val); }if (pll->pwr_base) {/* latch input value so core power can be shut down */ val =readl (pll->pwr_base + ctrl->aon.offset); val |= (1 << ctrl->aon.iso_shift); -writel (val, pll->pwr_base + ctrl->aon.offset); +iproc_pll_write (pll, pll->pwr_base, ctrl->aon.offset, val);/* power down the core */ val &= ~(bit_mask (ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); -writel (val, pll->pwr_base + ctrl->aon.offset); +iproc_pll_write (pll, pll->pwr_base, ctrl->aon.offset, val); } }
@@ -177,10 +186,7 @@ static int __pll_enable(struct iproc_pll *pll)if (ctrl->flags &IPROC_CLK_EMBED_PWRCTRL ) { val =readl (pll->pll_base + ctrl->aon.offset); val &= ~(bit_mask (ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); -writel (val, pll->pll_base + ctrl->aon.offset); - -if (unlikely (ctrl->flags &IPROC_CLK_NEEDS_READ_BACK )) -readl (pll->pll_base + ctrl->aon.offset); +iproc_pll_write (pll, pll->pll_base, ctrl->aon.offset, val); }if (pll->pwr_base) {
@@ -188,14 +194,14 @@ static int __pll_enable(struct iproc_pll *pll) val =readl (pll->pwr_base + ctrl->aon.offset); val |=bit_mask (ctrl->aon.pwr_width) << ctrl->aon.pwr_shift; val &= ~(1 << ctrl->aon.iso_shift); -writel (val, pll->pwr_base + ctrl->aon.offset); +iproc_pll_write (pll, pll->pwr_base, ctrl->aon.offset, val); }/* certain PLLs also need to be ungated from the ASIU top level */ if (ctrl->flags &IPROC_CLK_PLL_ASIU ) { val =readl (pll->asiu_base + ctrl->asiu.offset); val |= (1 << ctrl->asiu.en_shift); -writel (val, pll->asiu_base + ctrl->asiu.offset); +iproc_pll_write (pll, pll->asiu_base, ctrl->asiu.offset, val); }return 0 ;
@@ -209,9 +215,7 @@ static void __pll_put_in_reset(struct iproc_pll *pll) val =readl (pll->pll_base + reset->offset); val &= ~(1 << reset->reset_shift |1 << reset->p_reset_shift); -writel (val, pll->pll_base + reset->offset); -if (unlikely (ctrl->flags &IPROC_CLK_NEEDS_READ_BACK )) -readl (pll->pll_base + reset->offset); +iproc_pll_write (pll, pll->pll_base, reset->offset, val); } static void __pll_bring_out_reset(struct iproc_pll *pll, unsigned int kp,
@@ -228,9 +232,7 @@ static void __pll_bring_out_reset(struct iproc_pll *pll, unsigned int kp, val |= ki << reset->ki_shift | kp << reset->kp_shift | ka << reset->ka_shift; val |=1 << reset->reset_shift |1 << reset->p_reset_shift; -writel (val, pll->pll_base + reset->offset); -if (unlikely (ctrl->flags &IPROC_CLK_NEEDS_READ_BACK )) -readl (pll->pll_base + reset->offset); +iproc_pll_write (pll, pll->pll_base, reset->offset, val); } static int pll_set_rate(struct iproc_clk *clk, unsigned int rate_index,
@@ -285,9 +287,8 @@ static int pll_set_rate(struct iproc_clk *clk, unsigned int rate_index,/* put PLL in reset */ __pll_put_in_reset (pll); -writel (0 , pll->pll_base + ctrl->vco_ctrl.u_offset); -if (unlikely (ctrl->flags &IPROC_CLK_NEEDS_READ_BACK )) -readl (pll->pll_base + ctrl->vco_ctrl.u_offset); +iproc_pll_write (pll, pll->pll_base, ctrl->vco_ctrl.u_offset,0 ); + val =readl (pll->pll_base + ctrl->vco_ctrl.l_offset);if (rate >=VCO_LOW && rate <VCO_MID )
@@ -298,17 +299,13 @@ static int pll_set_rate(struct iproc_clk *clk, unsigned int rate_index,else val |= (1 <<PLL_VCO_HIGH_SHIFT ); -writel (val, pll->pll_base + ctrl->vco_ctrl.l_offset); -if (unlikely (ctrl->flags &IPROC_CLK_NEEDS_READ_BACK )) -readl (pll->pll_base + ctrl->vco_ctrl.l_offset); +iproc_pll_write (pll, pll->pll_base, ctrl->vco_ctrl.l_offset, val);/* program integer part of NDIV */ val =readl (pll->pll_base + ctrl->ndiv_int.offset); val &= ~(bit_mask (ctrl->ndiv_int.width) << ctrl->ndiv_int.shift); val |= vco->ndiv_int << ctrl->ndiv_int.shift; -writel (val, pll->pll_base + ctrl->ndiv_int.offset); -if (unlikely (ctrl->flags &IPROC_CLK_NEEDS_READ_BACK )) -readl (pll->pll_base + ctrl->ndiv_int.offset); +iproc_pll_write (pll, pll->pll_base, ctrl->ndiv_int.offset, val);/* program fractional part of NDIV */ if (ctrl->flags &IPROC_CLK_PLL_HAS_NDIV_FRAC ) {
@@ -316,18 +313,15 @@ static int pll_set_rate(struct iproc_clk *clk, unsigned int rate_index, val &= ~(bit_mask (ctrl->ndiv_frac.width) << ctrl->ndiv_frac.shift); val |= vco->ndiv_frac << ctrl->ndiv_frac.shift; -writel (val, pll->pll_base + ctrl->ndiv_frac.offset); -if (unlikely (ctrl->flags &IPROC_CLK_NEEDS_READ_BACK )) -readl (pll->pll_base + ctrl->ndiv_frac.offset); +iproc_pll_write (pll, pll->pll_base, ctrl->ndiv_frac.offset, + val); }/* program PDIV */ val =readl (pll->pll_base + ctrl->pdiv.offset); val &= ~(bit_mask (ctrl->pdiv.width) << ctrl->pdiv.shift); val |= vco->pdiv << ctrl->pdiv.shift; -writel (val, pll->pll_base + ctrl->pdiv.offset); -if (unlikely (ctrl->flags &IPROC_CLK_NEEDS_READ_BACK )) -readl (pll->pll_base + ctrl->pdiv.offset); +iproc_pll_write (pll, pll->pll_base, ctrl->pdiv.offset, val);__pll_bring_out_reset (pll, kp, ka, ki);
@@ -467,14 +461,12 @@ static int iproc_clk_enable(struct clk_hw *hw)/* channel enable is active low */ val =readl (pll->pll_base + ctrl->enable.offset); val &= ~(1 << ctrl->enable.enable_shift); -writel (val, pll->pll_base + ctrl->enable.offset); +iproc_pll_write (pll, pll->pll_base, ctrl->enable.offset, val);/* also make sure channel is not held */ val =readl (pll->pll_base + ctrl->enable.offset); val &= ~(1 << ctrl->enable.hold_shift); -writel (val, pll->pll_base + ctrl->enable.offset); -if (unlikely (ctrl->flags &IPROC_CLK_NEEDS_READ_BACK )) -readl (pll->pll_base + ctrl->enable.offset); +iproc_pll_write (pll, pll->pll_base, ctrl->enable.offset, val);return 0 ; }
@@ -491,9 +483,7 @@ static void iproc_clk_disable(struct clk_hw *hw) val =readl (pll->pll_base + ctrl->enable.offset); val |=1 << ctrl->enable.enable_shift; -writel (val, pll->pll_base + ctrl->enable.offset); -if (unlikely (ctrl->flags &IPROC_CLK_NEEDS_READ_BACK )) -readl (pll->pll_base + ctrl->enable.offset); +iproc_pll_write (pll, pll->pll_base, ctrl->enable.offset, val); } static unsigned long iproc_clk_recalc_rate(struct clk_hw *hw,
@@ -562,9 +552,7 @@ static int iproc_clk_set_rate(struct clk_hw *hw, unsigned long rate, val &= ~(bit_mask (ctrl->mdiv.width) << ctrl->mdiv.shift); val |= div << ctrl->mdiv.shift; } -writel (val, pll->pll_base + ctrl->mdiv.offset); -if (unlikely (ctrl->flags &IPROC_CLK_NEEDS_READ_BACK )) -readl (pll->pll_base + ctrl->mdiv.offset); +iproc_pll_write (pll, pll->pll_base, ctrl->mdiv.offset, val); clk->rate = parent_rate / div;return 0 ;
@@ -591,9 +579,7 @@ static void iproc_pll_sw_cfg(struct iproc_pll *pll) val =readl (pll->pll_base + ctrl->sw_ctrl.offset); val |=BIT (ctrl->sw_ctrl.shift); -writel (val, pll->pll_base + ctrl->sw_ctrl.offset); -if (unlikely (ctrl->flags &IPROC_CLK_NEEDS_READ_BACK )) -readl (pll->pll_base + ctrl->sw_ctrl.offset); +iproc_pll_write (pll, pll->pll_base, ctrl->sw_ctrl.offset, val); } }
Signature · 1 line
1.9.1
spamassassin system account
AppliedRe: [PATCH v3 05/10] clk: iproc: Add PLL base write function
Quoted 7 lines · Jon Mason
All writes to the PLL base address must be flushed if the
IPROC_CLK_NEEDS_READ_BACKflag is set. If we add a function to make the necessary write and reads, we can make sure that any future code which makes PLL base writes will do the correct thing.Signed-off-by Jon Mason <[email protected]>---
Applied to clk-iproc
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH v3 6/10 clk: iproc: Split off dig_filter
In reply to Jon MasonThe PLL loop filter/gain can be located in a separate register on some SoCs. Split these off into a separate variable, so that an offset can be added if necessary. Also, make the necessary modifications to the Cygnus and NSP drivers for this change.
--- drivers/clk/bcm/clk-cygnus.c | 17 +++++++++++------ drivers/clk/bcm/clk-iproc-pll.c | 14 +++++++++----- drivers/clk/bcm/clk-iproc.h | 10 +++++++++- drivers/clk/bcm/clk-nsp.c | 14 +++++++++----- 4 files changed, 38 insertions(+), 17 deletions(-)
drivers/clk/bcm/clk-cygnus.c +11 -6
@@ -34,9 +34,11 @@ { .offset = o, .en_shift = es, .high_shift = hs, \ .high_width = hw, .low_shift = ls, .low_width = lw } -#define RESET_VAL (o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \ - .reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \ - .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \ +#define RESET_VAL (o, rs, prs) { .offset = o, .reset_shift = rs, \ + .p_reset_shift = prs } + +#define DF_VAL (o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, .ki_shift = kis,\ + .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \ .ka_width = kaw }#define VCO_CTRL_VAL (uo, lo) { .u_offset = uo, .l_offset = lo }
@@ -56,7 +58,8 @@ static const struct iproc_pll_ctrl genpll = { .flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_PLL_NEEDS_SW_CFG, .aon = AON_VAL(0x0, 2, 1, 0), - .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 3), + .reset = RESET_VAL(0x0, 11, 10), + .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3), .sw_ctrl = SW_CTRL_VAL(0x10, 31), .ndiv_int = REG_VAL(0x10, 20, 10), .ndiv_frac = REG_VAL(0x10, 0, 20),
@@ -114,7 +117,8 @@ CLK_OF_DECLARE(cygnus_genpll, "brcm,cygnus-genpll", cygnus_genpll_clk_init);static const struct iproc_pll_ctrl lcpll0 = { .flags =IPROC_CLK_AON |IPROC_CLK_PLL_NEEDS_SW_CFG , .aon =AON_VAL (0x0 ,2 ,5 ,4 ), - .reset =RESET_VAL (0x0 ,31 ,30 ,27 ,3 ,23 ,4 ,19 ,4 ), + .reset =RESET_VAL (0x0 ,31 ,30 ), + .dig_filter =DF_VAL (0x0 ,27 ,3 ,23 ,4 ,19 ,4 ), .sw_ctrl =SW_CTRL_VAL (0x4 ,31 ), .ndiv_int =REG_VAL (0x4 ,16 ,10 ), .pdiv =REG_VAL (0x4 ,26 ,4 ),
@@ -191,7 +195,8 @@ static const struct iproc_pll_ctrl mipipll = { IPROC_CLK_NEEDS_READ_BACK, .aon = AON_VAL(0x0, 4, 17, 16), .asiu = ASIU_GATE_VAL(0x0, 3), - .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 4), + .reset = RESET_VAL(0x0, 11, 10), + .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 4), .ndiv_int = REG_VAL(0x10, 20, 10), .ndiv_frac = REG_VAL(0x10, 0, 20), .pdiv = REG_VAL(0x14, 0, 4),
drivers/clk/bcm/clk-iproc-pll.c +9 -5
@@ -224,13 +224,17 @@ static void __pll_bring_out_reset(struct iproc_pll *pll, unsigned int kp,u32 val;const struct iproc_pll_ctrl *ctrl = pll->ctrl;const struct iproc_pll_reset_ctrl *reset = &ctrl->reset; +const struct iproc_pll_dig_filter_ctrl *dig_filter = &ctrl->dig_filter; + + val =readl (pll->pll_base + dig_filter->offset); + val &= ~(bit_mask (dig_filter->ki_width) << dig_filter->ki_shift | +bit_mask (dig_filter->kp_width) << dig_filter->kp_shift | +bit_mask (dig_filter->ka_width) << dig_filter->ka_shift); + val |= ki << dig_filter->ki_shift | kp << dig_filter->kp_shift | + ka << dig_filter->ka_shift; +iproc_pll_write (pll, pll->pll_base, dig_filter->offset, val); val =readl (pll->pll_base + reset->offset); - val &= ~(bit_mask (reset->ki_width) << reset->ki_shift | -bit_mask (reset->kp_width) << reset->kp_shift | -bit_mask (reset->ka_width) << reset->ka_shift); - val |= ki << reset->ki_shift | kp << reset->kp_shift | - ka << reset->ka_shift; val |=1 << reset->reset_shift |1 << reset->p_reset_shift;iproc_pll_write (pll, pll->pll_base, reset->offset, val); }
drivers/clk/bcm/clk-iproc.h +9 -1
@@ -94,12 +94,19 @@ struct iproc_pll_aon_pwr_ctrl { };/* -* Control of the PLL reset, with Ki, Kp, and Ka parameters +* Control of the PLL reset */ struct iproc_pll_reset_ctrl {unsigned int offset;unsigned int reset_shift;unsigned int p_reset_shift; +}; + +/* +* Control of the Ki, Kp, and Ka parameters +*/ +struct iproc_pll_dig_filter_ctrl { +unsigned int offset;unsigned int ki_shift;unsigned int ki_width;unsigned int kp_shift;
@@ -129,6 +136,7 @@ struct iproc_pll_ctrl {struct iproc_pll_aon_pwr_ctrl aon;struct iproc_asiu_gate asiu;struct iproc_pll_reset_ctrl reset; +struct iproc_pll_dig_filter_ctrl dig_filter;struct iproc_pll_sw_ctrl sw_ctrl;struct iproc_clk_reg_op ndiv_int;struct iproc_clk_reg_op ndiv_frac;
drivers/clk/bcm/clk-nsp.c +9 -5
@@ -26,9 +26,11 @@#define AON_VAL (o, pw, ps, is) { .offset = o, .pwr_width = pw, \ .pwr_shift = ps, .iso_shift = is } -#define RESET_VAL (o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \ - .reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \ - .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \ +#define RESET_VAL (o, rs, prs) { .offset = o, .reset_shift = rs, \ + .p_reset_shift = prs } + +#define DF_VAL (o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, .ki_shift = kis,\ + .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \ .ka_width = kaw }#define ENABLE_VAL (o, es, hs, bs) { .offset = o, .enable_shift = es, \
@@ -43,7 +45,8 @@ CLK_OF_DECLARE(nsp_armpll, "brcm,nsp-armpll", nsp_armpll_init);static const struct iproc_pll_ctrl genpll = { .flags =IPROC_CLK_PLL_HAS_NDIV_FRAC |IPROC_CLK_EMBED_PWRCTRL , .aon =AON_VAL (0x0 ,1 ,12 ,0 ), - .reset =RESET_VAL (0x0 ,11 ,10 ,4 ,3 ,0 ,4 ,7 ,3 ), + .reset =RESET_VAL (0x0 ,11 ,10 ), + .dig_filter =DF_VAL (0x0 ,4 ,3 ,0 ,4 ,7 ,3 ), .ndiv_int =REG_VAL (0x14 ,20 ,10 ), .ndiv_frac =REG_VAL (0x14 ,0 ,20 ), .pdiv =REG_VAL (0x18 ,24 ,3 ),
@@ -99,7 +102,8 @@ CLK_OF_DECLARE(nsp_genpll_clk, "brcm,nsp-genpll", nsp_genpll_clk_init);static const struct iproc_pll_ctrl lcpll0 = { .flags =IPROC_CLK_PLL_HAS_NDIV_FRAC |IPROC_CLK_EMBED_PWRCTRL , .aon =AON_VAL (0x0 ,1 ,24 ,0 ), - .reset =RESET_VAL (0x0 ,23 ,22 ,16 ,3 ,12 ,4 ,19 ,4 ), + .reset =RESET_VAL (0x0 ,23 ,22 ), + .dig_filter =DF_VAL (0x0 ,16 ,3 ,12 ,4 ,19 ,4 ), .ndiv_int =REG_VAL (0x4 ,20 ,8 ), .ndiv_frac =REG_VAL (0x4 ,0 ,20 ), .pdiv =REG_VAL (0x4 ,28 ,3 ),
Signature · 1 line
1.9.1
Stephen Boyd
AppliedRe: [PATCH v3 06/10] clk: iproc: Split off dig_filter
Quoted 7 lines · Jon Mason
The PLL loop filter/gain can be located in a separate register on some SoCs. Split these off into a separate variable, so that an offset can be added if necessary. Also, make the necessary modifications to the Cygnus and NSP drivers for this change.
Signed-off-by Jon Mason <[email protected]>---
Applied to clk-iproc
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH v3 7/10 clk: iproc: Separate status and control variables
In reply to Jon MasonSome PLLs have separate registers for Status and Control. The means the pll_base needs to be split into 2 new variables, so that those PLLs can specify device tree registers for those independently. Also, add a new driver flag to identify this presence of the split, and let the driver know that additional registers need to be used.
--- drivers/clk/bcm/clk-iproc-pll.c | 96 ++++++++++++++++++++++++----------------- drivers/clk/bcm/clk-iproc.h | 6 +++ 2 files changed, 62 insertions(+), 40 deletions(-)
drivers/clk/bcm/clk-iproc-pll.c +56 -40
@@ -74,7 +74,8 @@ struct iproc_clk { };struct iproc_pll { -void __iomem *pll_base; +void __iomem *status_base; +void __iomem *control_base;void __iomem *pwr_base;void __iomem *asiu_base;
@@ -127,7 +128,7 @@ static int pll_wait_for_lock(struct iproc_pll *pll)const struct iproc_pll_ctrl *ctrl = pll->ctrl;for (i =0 ; i <LOCK_DELAY ; i++) { -u32 val =readl (pll->pll_base + ctrl->status.offset); +u32 val =readl (pll->status_base + ctrl->status.offset);if (val & (1 << ctrl->status.shift))return 0 ;
@@ -145,7 +146,7 @@ static void iproc_pll_write(const struct iproc_pll *pll, void __iomem *base,writel (val, base + offset);if (unlikely (ctrl->flags &IPROC_CLK_NEEDS_READ_BACK && - base == pll->pll_base)) + (base == pll->status_base || base == pll->control_base))) val =readl (base + offset); }
@@ -161,9 +162,9 @@ static void __pll_disable(struct iproc_pll *pll) }if (ctrl->flags &IPROC_CLK_EMBED_PWRCTRL ) { - val =readl (pll->pll_base + ctrl->aon.offset); + val =readl (pll->control_base + ctrl->aon.offset); val |= (bit_mask (ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); -iproc_pll_write (pll, pll->pll_base, ctrl->aon.offset, val); +iproc_pll_write (pll, pll->control_base, ctrl->aon.offset, val); }if (pll->pwr_base) {
@@ -184,9 +185,9 @@ static int __pll_enable(struct iproc_pll *pll)u32 val;if (ctrl->flags &IPROC_CLK_EMBED_PWRCTRL ) { - val =readl (pll->pll_base + ctrl->aon.offset); + val =readl (pll->control_base + ctrl->aon.offset); val &= ~(bit_mask (ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); -iproc_pll_write (pll, pll->pll_base, ctrl->aon.offset, val); +iproc_pll_write (pll, pll->control_base, ctrl->aon.offset, val); }if (pll->pwr_base) {
@@ -213,9 +214,9 @@ static void __pll_put_in_reset(struct iproc_pll *pll)const struct iproc_pll_ctrl *ctrl = pll->ctrl;const struct iproc_pll_reset_ctrl *reset = &ctrl->reset; - val =readl (pll->pll_base + reset->offset); + val =readl (pll->control_base + reset->offset); val &= ~(1 << reset->reset_shift |1 << reset->p_reset_shift); -iproc_pll_write (pll, pll->pll_base, reset->offset, val); +iproc_pll_write (pll, pll->control_base, reset->offset, val); } static void __pll_bring_out_reset(struct iproc_pll *pll, unsigned int kp,
@@ -226,17 +227,17 @@ static void __pll_bring_out_reset(struct iproc_pll *pll, unsigned int kp,const struct iproc_pll_reset_ctrl *reset = &ctrl->reset;const struct iproc_pll_dig_filter_ctrl *dig_filter = &ctrl->dig_filter; - val =readl (pll->pll_base + dig_filter->offset); + val =readl (pll->control_base + dig_filter->offset); val &= ~(bit_mask (dig_filter->ki_width) << dig_filter->ki_shift |bit_mask (dig_filter->kp_width) << dig_filter->kp_shift |bit_mask (dig_filter->ka_width) << dig_filter->ka_shift); val |= ki << dig_filter->ki_shift | kp << dig_filter->kp_shift | ka << dig_filter->ka_shift; -iproc_pll_write (pll, pll->pll_base, dig_filter->offset, val); +iproc_pll_write (pll, pll->control_base, dig_filter->offset, val); - val =readl (pll->pll_base + reset->offset); + val =readl (pll->control_base + reset->offset); val |=1 << reset->reset_shift |1 << reset->p_reset_shift; -iproc_pll_write (pll, pll->pll_base, reset->offset, val); +iproc_pll_write (pll, pll->control_base, reset->offset, val); } static int pll_set_rate(struct iproc_clk *clk, unsigned int rate_index,
@@ -291,9 +292,9 @@ static int pll_set_rate(struct iproc_clk *clk, unsigned int rate_index,/* put PLL in reset */ __pll_put_in_reset (pll); -iproc_pll_write (pll, pll->pll_base, ctrl->vco_ctrl.u_offset,0 ); +iproc_pll_write (pll, pll->control_base, ctrl->vco_ctrl.u_offset,0 ); - val =readl (pll->pll_base + ctrl->vco_ctrl.l_offset); + val =readl (pll->control_base + ctrl->vco_ctrl.l_offset);if (rate >=VCO_LOW && rate <VCO_MID ) val |= (1 <<PLL_VCO_LOW_SHIFT );
@@ -303,29 +304,29 @@ static int pll_set_rate(struct iproc_clk *clk, unsigned int rate_index,else val |= (1 <<PLL_VCO_HIGH_SHIFT ); -iproc_pll_write (pll, pll->pll_base, ctrl->vco_ctrl.l_offset, val); +iproc_pll_write (pll, pll->control_base, ctrl->vco_ctrl.l_offset, val);/* program integer part of NDIV */ - val =readl (pll->pll_base + ctrl->ndiv_int.offset); + val =readl (pll->control_base + ctrl->ndiv_int.offset); val &= ~(bit_mask (ctrl->ndiv_int.width) << ctrl->ndiv_int.shift); val |= vco->ndiv_int << ctrl->ndiv_int.shift; -iproc_pll_write (pll, pll->pll_base, ctrl->ndiv_int.offset, val); +iproc_pll_write (pll, pll->control_base, ctrl->ndiv_int.offset, val);/* program fractional part of NDIV */ if (ctrl->flags &IPROC_CLK_PLL_HAS_NDIV_FRAC ) { - val =readl (pll->pll_base + ctrl->ndiv_frac.offset); + val =readl (pll->control_base + ctrl->ndiv_frac.offset); val &= ~(bit_mask (ctrl->ndiv_frac.width) << ctrl->ndiv_frac.shift); val |= vco->ndiv_frac << ctrl->ndiv_frac.shift; -iproc_pll_write (pll, pll->pll_base, ctrl->ndiv_frac.offset, +iproc_pll_write (pll, pll->control_base, ctrl->ndiv_frac.offset, val); }/* program PDIV */ - val =readl (pll->pll_base + ctrl->pdiv.offset); + val =readl (pll->control_base + ctrl->pdiv.offset); val &= ~(bit_mask (ctrl->pdiv.width) << ctrl->pdiv.shift); val |= vco->pdiv << ctrl->pdiv.shift; -iproc_pll_write (pll, pll->pll_base, ctrl->pdiv.offset, val); +iproc_pll_write (pll, pll->control_base, ctrl->pdiv.offset, val);__pll_bring_out_reset (pll, kp, ka, ki);
@@ -372,7 +373,7 @@ static unsigned long iproc_pll_recalc_rate(struct clk_hw *hw,return 0 ;/* PLL needs to be locked */ - val =readl (pll->pll_base + ctrl->status.offset); + val =readl (pll->status_base + ctrl->status.offset);if ((val & (1 << ctrl->status.shift)) ==0 ) { clk->rate =0 ;return 0 ;
@@ -383,13 +384,13 @@ static unsigned long iproc_pll_recalc_rate(struct clk_hw *hw,* * ((ndiv_int + ndiv_frac / 2^20) * (parent clock rate / pdiv) */ - val =readl (pll->pll_base + ctrl->ndiv_int.offset); + val =readl (pll->control_base + ctrl->ndiv_int.offset); ndiv_int = (val >> ctrl->ndiv_int.shift) &bit_mask (ctrl->ndiv_int.width); ndiv = (u64 )ndiv_int << ctrl->ndiv_int.shift;if (ctrl->flags &IPROC_CLK_PLL_HAS_NDIV_FRAC ) { - val =readl (pll->pll_base + ctrl->ndiv_frac.offset); + val =readl (pll->control_base + ctrl->ndiv_frac.offset); ndiv_frac = (val >> ctrl->ndiv_frac.shift) &bit_mask (ctrl->ndiv_frac.width);
@@ -398,7 +399,7 @@ static unsigned long iproc_pll_recalc_rate(struct clk_hw *hw, ndiv_frac; } - val =readl (pll->pll_base + ctrl->pdiv.offset); + val =readl (pll->control_base + ctrl->pdiv.offset); pdiv = (val >> ctrl->pdiv.shift) &bit_mask (ctrl->pdiv.width); clk->rate = (ndiv * parent_rate) >> ctrl->ndiv_int.shift;
@@ -463,14 +464,14 @@ static int iproc_clk_enable(struct clk_hw *hw)u32 val;/* channel enable is active low */ - val =readl (pll->pll_base + ctrl->enable.offset); + val =readl (pll->control_base + ctrl->enable.offset); val &= ~(1 << ctrl->enable.enable_shift); -iproc_pll_write (pll, pll->pll_base, ctrl->enable.offset, val); +iproc_pll_write (pll, pll->control_base, ctrl->enable.offset, val);/* also make sure channel is not held */ - val =readl (pll->pll_base + ctrl->enable.offset); + val =readl (pll->control_base + ctrl->enable.offset); val &= ~(1 << ctrl->enable.hold_shift); -iproc_pll_write (pll, pll->pll_base, ctrl->enable.offset, val); +iproc_pll_write (pll, pll->control_base, ctrl->enable.offset, val);return 0 ; }
@@ -485,9 +486,9 @@ static void iproc_clk_disable(struct clk_hw *hw)if (ctrl->flags &IPROC_CLK_AON )return ; - val =readl (pll->pll_base + ctrl->enable.offset); + val =readl (pll->control_base + ctrl->enable.offset); val |=1 << ctrl->enable.enable_shift; -iproc_pll_write (pll, pll->pll_base, ctrl->enable.offset, val); +iproc_pll_write (pll, pll->control_base, ctrl->enable.offset, val); } static unsigned long iproc_clk_recalc_rate(struct clk_hw *hw,
@@ -502,7 +503,7 @@ static unsigned long iproc_clk_recalc_rate(struct clk_hw *hw,if (parent_rate ==0 )return 0 ; - val =readl (pll->pll_base + ctrl->mdiv.offset); + val =readl (pll->control_base + ctrl->mdiv.offset); mdiv = (val >> ctrl->mdiv.shift) &bit_mask (ctrl->mdiv.width);if (mdiv ==0 ) mdiv =256 ;
@@ -549,14 +550,14 @@ static int iproc_clk_set_rate(struct clk_hw *hw, unsigned long rate,if (div >256 )return -EINVAL ; - val =readl (pll->pll_base + ctrl->mdiv.offset); + val =readl (pll->control_base + ctrl->mdiv.offset);if (div ==256 ) { val &= ~(bit_mask (ctrl->mdiv.width) << ctrl->mdiv.shift); }else { val &= ~(bit_mask (ctrl->mdiv.width) << ctrl->mdiv.shift); val |= div << ctrl->mdiv.shift; } -iproc_pll_write (pll, pll->pll_base, ctrl->mdiv.offset, val); +iproc_pll_write (pll, pll->control_base, ctrl->mdiv.offset, val); clk->rate = parent_rate / div;return 0 ;
@@ -581,9 +582,10 @@ static void iproc_pll_sw_cfg(struct iproc_pll *pll)if (ctrl->flags &IPROC_CLK_PLL_NEEDS_SW_CFG ) {u32 val; - val =readl (pll->pll_base + ctrl->sw_ctrl.offset); + val =readl (pll->control_base + ctrl->sw_ctrl.offset); val |=BIT (ctrl->sw_ctrl.shift); -iproc_pll_write (pll, pll->pll_base, ctrl->sw_ctrl.offset, val); +iproc_pll_write (pll, pll->control_base, ctrl->sw_ctrl.offset, + val); } }
@@ -618,8 +620,8 @@ void __init iproc_pll_clk_setup(struct device_node *node,if (WARN_ON (!pll->clks)) goto err_clks; - pll->pll_base =of_iomap (node,0 ); -if (WARN_ON (!pll->pll_base)) + pll->control_base =of_iomap (node,0 ); +if (WARN_ON (!pll->control_base)) goto err_pll_iomap;/* Some SoCs do not require the pwr_base, thus failing is not fatal */
@@ -632,6 +634,16 @@ void __init iproc_pll_clk_setup(struct device_node *node, goto err_asiu_iomap; } +if (pll_ctrl->flags &IPROC_CLK_PLL_SPLIT_STAT_CTRL ) { +/* Some SoCs have a split status/control. If this does not +* exist, assume they are unified. +*/ + pll->status_base =of_iomap (node,2 ); +if (!pll->status_base) + goto err_status_iomap; + }else + pll->status_base = pll->control_base; +/* initialize and register the PLL itself */ pll->ctrl = pll_ctrl;
@@ -702,6 +714,10 @@ err_clk_register:clk_unregister (pll->clk_data.clks[i]); err_pll_register: +if (pll->status_base != pll->control_base) +iounmap (pll->status_base); + +err_status_iomap:if (pll->asiu_base)iounmap (pll->asiu_base);
@@ -709,7 +725,7 @@ err_asiu_iomap:if (pll->pwr_base)iounmap (pll->pwr_base); -iounmap (pll->pll_base); +iounmap (pll->control_base); err_pll_iomap:kfree (pll->clks);
drivers/clk/bcm/clk-iproc.h +6 -0
@@ -55,6 +55,12 @@#define IPROC_CLK_EMBED_PWRCTRL BIT(5)/* +* Some PLLs have separate registers for Status and Control. Identify this to +* let the driver know if additional registers need to be used +*/ +#define IPROC_CLK_PLL_SPLIT_STAT_CTRL BIT(6) + +/* * Parameters for VCO frequency configuration * * VCO frequency =
Signature · 1 line
1.9.1
Stephen Boyd
AppliedRe: [PATCH v3 07/10] clk: iproc: Separate status and control variables
Quoted 8 lines · Jon Mason
Some PLLs have separate registers for Status and Control. The means the
pll_baseneeds to be split into 2 new variables, so that those PLLs can specify device tree registers for those independently. Also, add a new driver flag to identify this presence of the split, and let the driver know that additional registers need to be used.Signed-off-by Jon Mason <[email protected]>---
Applied to clk-iproc
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH v3 8/10 clk: ns2: add clock support for Broadcom Northstar 2 SoC
In reply to Jon MasonThe Broadcom Northstar 2 SoC is architected under the iProc architecture. It has the following PLLs: GENPLL SCR, GENPLL SW, LCPLL DDR, LCPLL Ports, all derived from an onboard crystal.
--- drivers/clk/Makefile | 2 +- drivers/clk/bcm/Makefile | 1 + drivers/clk/bcm/clk-ns2.c | 288 ++++++++++++++++++++++++++++++++++++ include/dt-bindings/clock/bcm-ns2.h | 72 +++++++++ 4 files changed, 362 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/bcm/clk-ns2.c create mode 100644 include/dt-bindings/clock/bcm-ns2.h
drivers/clk/Makefile +1 -1
@@ -47,7 +47,7 @@ obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o obj-$(CONFIG_COMMON_CLK_AT91) += at91/ -obj-$(CONFIG_ARCH_BCM) += bcm/ +obj-y += bcm/ obj-$(CONFIG_ARCH_BERLIN) += berlin/ obj-$(CONFIG_ARCH_HISI) += hisilicon/ obj-$(CONFIG_ARCH_MXC) += imx/
drivers/clk/bcm/Makefile +1 -0
@@ -3,6 +3,7 @@ obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o clk-iproc-asiu.o +obj-$(CONFIG_COMMON_CLK_IPROC) += clk-ns2.o obj-$(CONFIG_ARCH_BCM_CYGNUS) += clk-cygnus.o obj-$(CONFIG_ARCH_BCM_NSP) += clk-nsp.o obj-$(CONFIG_ARCH_BCM_5301X) += clk-nsp.o
drivers/clk/bcm/clk-ns2.c new file +288 -0
288 lines not on this page · raw message
include/dt-bindings/clock/bcm-ns2.h new file +72 -0
72 lines not on this page · raw message
Signature · 1 line
1.9.1
Scott Branden
maintainerRe: [PATCH v3 08/10] clk: ns2: add clock support for Broadcom Northstar 2 SoC
We need some sort of kconfig option to differentiate NS2 clock driver from being pulled in all the time.
Quoted 32 lines · Jon Mason
The Broadcom Northstar 2 SoC is architected under the iProc architecture. It has the following PLLs: GENPLL SCR, GENPLL SW, LCPLL DDR, LCPLL Ports, all derived from an onboard crystal.
Signed-off-by Jon Mason <[email protected]>--- drivers/clk/Makefile | 2 +- drivers/clk/bcm/Makefile | 1 + drivers/clk/bcm/clk-ns2.c | 288 ++++++++++++++++++++++++++++++++++++ include/dt-bindings/clock/bcm-ns2.h | 72 +++++++++ 4 files changed, 362 insertions(+), 1 deletion(-)create mode 100644
drivers/clk/bcm/clk-ns2.ccreate mode 100644include/dt-bindings/clock/bcm-ns2.hdrivers/clk/Makefile +1
-1@@ -47,7 +47,7 @@ obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o obj-$(CONFIG_COMMON_CLK_AT91) += at91/ -obj-$(CONFIG_ARCH_BCM) += bcm/ +obj-y += bcm/ obj-$(CONFIG_ARCH_BERLIN) += berlin/ obj-$(CONFIG_ARCH_HISI) += hisilicon/ obj-$(CONFIG_ARCH_MXC) += imx/drivers/clk/bcm/Makefile +0
-0
drivers/clk/bcm/Makefile obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o · line 6
Quoted 4 lines
drivers/clk/bcm/Makefile +1
-0@@ -3,6 +3,7 @@ obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o clk-iproc-asiu.o +obj-$(CONFIG_COMMON_CLK_IPROC) += clk-ns2.o
NS2 code is dragged in for all IPROC SoCs. We need a config option for NS2 (CONFIG_ARCH_BCM_NS2) to avoid this (if Arnd allows this for ARMv8 processors... ?).
You can see below ARMv7 processors don't have this problem.
If not we need to add CONFIG_CLK_NS2.
Ray Jui
maintainerRe: [PATCH v3 08/10] clk: ns2: add clock support for Broadcom Northstar 2 SoC
Quoted 47 lines · Scott Branden
We need some sort of kconfig option to differentiate NS2 clock driver from being pulled in all the time.
Quoted 36 lines · Jon Mason
The Broadcom Northstar 2 SoC is architected under the iProc architecture. It has the following PLLs: GENPLL SCR, GENPLL SW, LCPLL DDR, LCPLL Ports, all derived from an onboard crystal.
Signed-off-by Jon Mason <[email protected]>--- drivers/clk/Makefile | 2 +- drivers/clk/bcm/Makefile | 1 + drivers/clk/bcm/clk-ns2.c | 288 ++++++++++++++++++++++++++++++++++++ include/dt-bindings/clock/bcm-ns2.h | 72 +++++++++ 4 files changed, 362 insertions(+), 1 deletion(-)create mode 100644
drivers/clk/bcm/clk-ns2.ccreate mode 100644include/dt-bindings/clock/bcm-ns2.hdrivers/clk/Makefile +1
-1@@ -47,7 +47,7 @@ obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o obj-$(CONFIG_COMMON_CLK_AT91) += at91/ -obj-$(CONFIG_ARCH_BCM) += bcm/ +obj-y += bcm/ obj-$(CONFIG_ARCH_BERLIN) += berlin/ obj-$(CONFIG_ARCH_HISI) += hisilicon/ obj-$(CONFIG_ARCH_MXC) += imx/drivers/clk/bcm/Makefile +0
-0@@ -3,6 +3,7 @@ obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.oQuoted 2 lines
clk-iproc-pll.o clk-iproc-asiu.o
+obj-$(CONFIG_COMMON_CLK_IPROC) += clk-ns2.oNS2 code is dragged in for all IPROC SoCs. We need a config option for NS2 (
CONFIG_ARCH_BCM_NS2) to avoid this (if Arnd allows this for ARMv8 processors... ?).
Quoted 2 lines
You can see below ARMv7 processors don't have this problem.
The arm64 maintainers (Catalin, Mark, and etc.) stated they only want one ARCH options per chip family.
Quoted 1 line
If not we need to add
CONFIG_CLK_NS2.
If using CONFIG_CLK_NS2, how is it going to be enabled/selected?
Ray
Scott Branden
maintainerRe: [PATCH v3 08/10] clk: ns2: add clock support for Broadcom Northstar 2 SoC
Hi Ray,
Comment at near end.
Quoted 53 lines · Ray Jui
Quoted 47 lines · Scott Branden
We need some sort of kconfig option to differentiate NS2 clock driver from being pulled in all the time.
Quoted 36 lines · Jon Mason
The Broadcom Northstar 2 SoC is architected under the iProc architecture. It has the following PLLs: GENPLL SCR, GENPLL SW, LCPLL DDR, LCPLL Ports, all derived from an onboard crystal.
Signed-off-by Jon Mason <[email protected]>--- drivers/clk/Makefile | 2 +- drivers/clk/bcm/Makefile | 1 + drivers/clk/bcm/clk-ns2.c | 288 ++++++++++++++++++++++++++++++++++++ include/dt-bindings/clock/bcm-ns2.h | 72 +++++++++ 4 files changed, 362 insertions(+), 1 deletion(-)create mode 100644
drivers/clk/bcm/clk-ns2.ccreate mode 100644include/dt-bindings/clock/bcm-ns2.hdrivers/clk/Makefile +1
-1@@ -47,7 +47,7 @@ obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o obj-$(CONFIG_COMMON_CLK_AT91) += at91/ -obj-$(CONFIG_ARCH_BCM) += bcm/ +obj-y += bcm/ obj-$(CONFIG_ARCH_BERLIN) += berlin/ obj-$(CONFIG_ARCH_HISI) += hisilicon/ obj-$(CONFIG_ARCH_MXC) += imx/drivers/clk/bcm/Makefile +0
-0@@ -3,6 +3,7 @@ obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.oQuoted 2 lines
clk-iproc-pll.o clk-iproc-asiu.o
+obj-$(CONFIG_COMMON_CLK_IPROC) += clk-ns2.oNS2 code is dragged in for all IPROC SoCs. We need a config option for NS2 (
CONFIG_ARCH_BCM_NS2) to avoid this (if Arnd allows this for ARMv8 processors... ?).Quoted 2 lines
You can see below ARMv7 processors don't have this problem.
Quoted 6 lines
The arm64 maintainers (Catalin, Mark, and etc.) stated they only want one ARCH options per chip family.
Quoted 1 line
If not we need to add
CONFIG_CLK_NS2.If using
CONFIG_CLK_NS2, how is it going to be enabled/selected?
Since CONFIG_ARCH_BCM_NS2 isn't "allowed" to be introduced we will need to create and select a CONFIG_CLK_BCM_NS2 in the defconfig instead.
Quoted 3 lines
Ray
Regards,
Scott
Re: [PATCH v3 08/10] clk: ns2: add clock support for Broadcom Northstar 2 SoC
Quoted 61 lines · Scott Branden
Hi Ray,
Comment at near end.
Quoted 56 lines · Ray Jui
Quoted 47 lines · Scott Branden
We need some sort of kconfig option to differentiate NS2 clock driver from being pulled in all the time.
Quoted 36 lines · Jon Mason
The Broadcom Northstar 2 SoC is architected under the iProc architecture. It has the following PLLs: GENPLL SCR, GENPLL SW, LCPLL DDR, LCPLL Ports, all derived from an onboard crystal.
Signed-off-by Jon Mason <[email protected]>--- drivers/clk/Makefile | 2 +- drivers/clk/bcm/Makefile | 1 + drivers/clk/bcm/clk-ns2.c | 288 ++++++++++++++++++++++++++++++++++++ include/dt-bindings/clock/bcm-ns2.h | 72 +++++++++ 4 files changed, 362 insertions(+), 1 deletion(-)create mode 100644
drivers/clk/bcm/clk-ns2.ccreate mode 100644include/dt-bindings/clock/bcm-ns2.hdrivers/clk/Makefile +1
-1@@ -47,7 +47,7 @@ obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o obj-$(CONFIG_COMMON_CLK_AT91) += at91/ -obj-$(CONFIG_ARCH_BCM) += bcm/ +obj-y += bcm/ obj-$(CONFIG_ARCH_BERLIN) += berlin/ obj-$(CONFIG_ARCH_HISI) += hisilicon/ obj-$(CONFIG_ARCH_MXC) += imx/drivers/clk/bcm/Makefile +0
-0@@ -3,6 +3,7 @@ obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.oQuoted 2 lines
clk-iproc-pll.o clk-iproc-asiu.o
+obj-$(CONFIG_COMMON_CLK_IPROC) += clk-ns2.oNS2 code is dragged in for all IPROC SoCs. We need a config option for NS2 (
CONFIG_ARCH_BCM_NS2) to avoid this (if Arnd allows this for ARMv8 processors... ?).Quoted 2 lines
You can see below ARMv7 processors don't have this problem.
The arm64 maintainers (Catalin, Mark, and etc.) stated they only want one ARCH options per chip family.
Quoted 7 lines
Quoted 3 lines
Quoted 1 line
If not we need to add
CONFIG_CLK_NS2.If using
CONFIG_CLK_NS2, how is it going to be enabled/selected?Since
CONFIG_ARCH_BCM_NS2isn't "allowed" to be introduced we will need to create and select aCONFIG_CLK_BCM_NS2in the defconfig instead.
Is this better than the binary becoming slightly bigger? I thought the extra complexity was worse than having an unused chunk of clk code (and Kona is already doing the same thing above). I believe Ray was in agreement with me during the internal review of this code.
Thanks,
Jon
Quoted 6 lines
Quoted 3 lines
Ray
Regards,
Scott
Ray Jui
maintainerRe: [PATCH v3 08/10] clk: ns2: add clock support for Broadcom Northstar 2 SoC
Quoted 70 lines · Jon Mason
Quoted 61 lines · Scott Branden
Hi Ray,
Comment at near end.
Quoted 56 lines · Ray Jui
Quoted 47 lines · Scott Branden
We need some sort of kconfig option to differentiate NS2 clock driver from being pulled in all the time.
Quoted 36 lines · Jon Mason
The Broadcom Northstar 2 SoC is architected under the iProc architecture. It has the following PLLs: GENPLL SCR, GENPLL SW, LCPLL DDR, LCPLL Ports, all derived from an onboard crystal.
Signed-off-by Jon Mason <[email protected]>--- drivers/clk/Makefile | 2 +- drivers/clk/bcm/Makefile | 1 + drivers/clk/bcm/clk-ns2.c | 288 ++++++++++++++++++++++++++++++++++++ include/dt-bindings/clock/bcm-ns2.h | 72 +++++++++ 4 files changed, 362 insertions(+), 1 deletion(-)create mode 100644
drivers/clk/bcm/clk-ns2.ccreate mode 100644include/dt-bindings/clock/bcm-ns2.hdrivers/clk/Makefile +1
-1@@ -47,7 +47,7 @@ obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o obj-$(CONFIG_COMMON_CLK_AT91) += at91/ -obj-$(CONFIG_ARCH_BCM) += bcm/ +obj-y += bcm/ obj-$(CONFIG_ARCH_BERLIN) += berlin/ obj-$(CONFIG_ARCH_HISI) += hisilicon/ obj-$(CONFIG_ARCH_MXC) += imx/drivers/clk/bcm/Makefile +0
-0@@ -3,6 +3,7 @@ obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.oQuoted 2 lines
clk-iproc-pll.o clk-iproc-asiu.o
+obj-$(CONFIG_COMMON_CLK_IPROC) += clk-ns2.oNS2 code is dragged in for all IPROC SoCs. We need a config option for NS2 (
CONFIG_ARCH_BCM_NS2) to avoid this (if Arnd allows this for ARMv8 processors... ?).Quoted 2 lines
You can see below ARMv7 processors don't have this problem.
The arm64 maintainers (Catalin, Mark, and etc.) stated they only want one ARCH options per chip family.
Quoted 7 lines
Quoted 3 lines
Quoted 1 line
If not we need to add
CONFIG_CLK_NS2.If using
CONFIG_CLK_NS2, how is it going to be enabled/selected?Since
CONFIG_ARCH_BCM_NS2isn't "allowed" to be introduced we will need to create and select aCONFIG_CLK_BCM_NS2in the defconfig instead.
Quoted 8 lines
Is this better than the binary becoming slightly bigger? I thought the extra complexity was worse than having an unused chunk of clk code (and Kona is already doing the same thing above). I believe Ray was in agreement with me during the internal review of this code.
Thanks,
Jon
Yes, I'm okay with leaving it as it is. I even prefer changing the current Makefile to make all iProc based core clock drivers and SoC specific clock tables under CONFIG_COMMON_CLK_IPROC, which is what some of the other vendors do.
Quoted 6 lines
Quoted 6 lines
Quoted 3 lines
Ray
Regards,
Scott
Scott Branden
maintainerRe: [PATCH v3 08/10] clk: ns2: add clock support for Broadcom Northstar 2 SoC
Quoted 78 lines · Ray Jui
Quoted 75 lines · Jon Mason
Quoted 61 lines · Scott Branden
Hi Ray,
Comment at near end.
Quoted 56 lines · Ray Jui
Quoted 47 lines · Scott Branden
We need some sort of kconfig option to differentiate NS2 clock driver from being pulled in all the time.
Quoted 36 lines · Jon Mason
The Broadcom Northstar 2 SoC is architected under the iProc architecture. It has the following PLLs: GENPLL SCR, GENPLL SW, LCPLL DDR, LCPLL Ports, all derived from an onboard crystal.
Signed-off-by Jon Mason <[email protected]>--- drivers/clk/Makefile | 2 +- drivers/clk/bcm/Makefile | 1 + drivers/clk/bcm/clk-ns2.c | 288 ++++++++++++++++++++++++++++++++++++ include/dt-bindings/clock/bcm-ns2.h | 72 +++++++++ 4 files changed, 362 insertions(+), 1 deletion(-)create mode 100644
drivers/clk/bcm/clk-ns2.ccreate mode 100644include/dt-bindings/clock/bcm-ns2.hdrivers/clk/Makefile +1
-1@@ -47,7 +47,7 @@ obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o obj-$(CONFIG_COMMON_CLK_AT91) += at91/ -obj-$(CONFIG_ARCH_BCM) += bcm/ +obj-y += bcm/ obj-$(CONFIG_ARCH_BERLIN) += berlin/ obj-$(CONFIG_ARCH_HISI) += hisilicon/ obj-$(CONFIG_ARCH_MXC) += imx/drivers/clk/bcm/Makefile +0
-0@@ -3,6 +3,7 @@ obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.oQuoted 2 lines
clk-iproc-pll.o clk-iproc-asiu.o
+obj-$(CONFIG_COMMON_CLK_IPROC) += clk-ns2.oNS2 code is dragged in for all IPROC SoCs. We need a config option for NS2 (
CONFIG_ARCH_BCM_NS2) to avoid this (if Arnd allows this for ARMv8 processors... ?).Quoted 2 lines
You can see below ARMv7 processors don't have this problem.
The arm64 maintainers (Catalin, Mark, and etc.) stated they only want one ARCH options per chip family.
Quoted 7 lines
Quoted 3 lines
Quoted 1 line
If not we need to add
CONFIG_CLK_NS2.If using
CONFIG_CLK_NS2, how is it going to be enabled/selected?Since
CONFIG_ARCH_BCM_NS2isn't "allowed" to be introduced we will need to create and select aCONFIG_CLK_BCM_NS2in the defconfig instead.Is this better than the binary becoming slightly bigger? I thought the extra complexity was worse than having an unused chunk of clk code (and Kona is already doing the same thing above). I believe Ray was in agreement with me during the internal review of this code.
Quoted 9 lines
Quoted 3 lines
Thanks,
JonYes, I'm okay with leaving it as it is. I even prefer changing the current
Makefileto make all iProc based core clock drivers and SoC specific clock tables underCONFIG_COMMON_CLK_IPROC, which is what some of the other vendors do.
I'd leave it exactly as is then rather than pulling in more dead code when not needed. This ns2 clock code is very minor compared to other code bloat in the kernel and drivers.
Quoted 6 lines
Quoted 6 lines
Quoted 6 lines
Quoted 3 lines
Ray
Regards,
Scott
Re: [PATCH v3 08/10] clk: ns2: add clock support for Broadcom Northstar 2 SoC
Quoted 21 lines · Scott Branden
Quoted 20 lines · Ray Jui
Quoted 18 lines · Jon Mason
Quoted 8 lines · Scott Branden
Quoted 3 lines · Ray Jui
On 10/15/2015 1:40 PM, Scott Branden wrote:
If using
CONFIG_CLK_NS2, how is it going to be enabled/selected?Since
CONFIG_ARCH_BCM_NS2isn't "allowed" to be introduced we will need to create and select aCONFIG_CLK_BCM_NS2in the defconfig instead.Is this better than the binary becoming slightly bigger? I thought the extra complexity was worse than having an unused chunk of clk code (and Kona is already doing the same thing above). I believe Ray was in agreement with me during the internal review of this code.
Thanks,
Jon
Quoted 8 lines
Quoted 5 lines
Yes, I'm okay with leaving it as it is. I even prefer changing the current
Makefileto make all iProc based core clock drivers and SoC specific clock tables underCONFIG_COMMON_CLK_IPROC, which is what some of the other vendors do.I'd leave it exactly as is then rather than pulling in more dead code when not needed. This ns2 clock code is very minor compared to other code bloat in the kernel and drivers.
We should really make these visible options that can be selected by anyone. Having selects in the ARCH config area is simple, but also has some downsides:
1) select is a reverse dependency and is hard for people to understand and can sometimes be a pain to track down
2) build coverage goes down because configs are hidden
3) we get code bloat like is being discussed here
So I'd really like to see someone take a good look at this whole Makefile situation that's going on and clean it up so that they're user visible options and then throw the config options into the defconfig. It isn't going to block this series, but it would be nice to do at some later point.
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH v3 08/10] clk: ns2: add clock support for Broadcom Northstar 2 SoC
Quoted 40 lines · Stephen Boyd
Quoted 21 lines · Scott Branden
Quoted 20 lines · Ray Jui
Quoted 18 lines · Jon Mason
Quoted 8 lines · Scott Branden
Quoted 3 lines · Ray Jui
On 10/15/2015 1:40 PM, Scott Branden wrote:
If using
CONFIG_CLK_NS2, how is it going to be enabled/selected?Since
CONFIG_ARCH_BCM_NS2isn't "allowed" to be introduced we will need to create and select aCONFIG_CLK_BCM_NS2in the defconfig instead.Is this better than the binary becoming slightly bigger? I thought the extra complexity was worse than having an unused chunk of clk code (and Kona is already doing the same thing above). I believe Ray was in agreement with me during the internal review of this code.
Thanks,
JonQuoted 8 lines
Quoted 5 lines
Yes, I'm okay with leaving it as it is. I even prefer changing the current
Makefileto make all iProc based core clock drivers and SoC specific clock tables underCONFIG_COMMON_CLK_IPROC, which is what some of the other vendors do.I'd leave it exactly as is then rather than pulling in more dead code when not needed. This ns2 clock code is very minor compared to other code bloat in the kernel and drivers.
We should really make these visible options that can be selected by anyone. Having selects in the ARCH config area is simple, but also has some downsides:
1) select is a reverse dependency and is hard for people to understand and can sometimes be a pain to track down
2) build coverage goes down because configs are hidden
Quoted 7 lines
3) we get code bloat like is being discussed here
So I'd really like to see someone take a good look at this whole
Makefilesituation that's going on and clean it up so that they're user visible options and then throw the config options into the defconfig. It isn't going to block this series, but it would be nice to do at some later point.
I'll do a pass at this today and send it out for review.
Thanks,
Jon
Quoted 4 lines
Signature · 3 lines
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Stephen Boyd
AppliedRe: [PATCH v3 08/10] clk: ns2: add clock support for Broadcom Northstar 2 SoC
In reply to Jon MasonQuoted 6 lines · Jon Mason
The Broadcom Northstar 2 SoC is architected under the iProc architecture. It has the following PLLs: GENPLL SCR, GENPLL SW, LCPLL DDR, LCPLL Ports, all derived from an onboard crystal.
Signed-off-by Jon Mason <[email protected]>---
Applied to clk-iproc
Signature · 2 lines
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PATCH v3 9/10 clk: iproc: define Broadcom NSP iProc clock binding
In reply to Jon MasonDocument the device tree bindings for Broadcom Northstar Plus architecture based clock controller
--- .../bindings/clock/brcm,iproc-clocks.txt | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+)
Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt +30 -0
@@ -130,3 +130,33 @@ These clock IDs are defined in: ch3_unused mipipll 4 BCM_CYGNUS_MIPIPLL_CH3_UNUSED ch4_unused mipipll 5 BCM_CYGNUS_MIPIPLL_CH4_UNUSED ch5_unused mipipll 6 BCM_CYGNUS_MIPIPLL_CH5_UNUSED + +Northstar and Northstar Plus +------ +PLL and leaf clock compatible strings for Northstar and Northstar Plus are: + "brcm,nsp-armpll" + "brcm,nsp-genpll" + "brcm,nsp-lcpll0" + +The following table defines the set of PLL/clock index and ID for Northstar and +Northstar Plus. These clock IDs are defined in: + "include/dt-bindings/clock/bcm-nsp.h" + + Clock Source Index ID + --- ----- ----- --------- + crystal N/A N/A N/A + + armpll crystal N/A N/A + + genpll crystal 0 BCM_NSP_GENPLL + phy genpll 1 BCM_NSP_GENPLL_PHY_CLK + ethernetclk genpll 2 BCM_NSP_GENPLL_ENET_SW_CLK + usbclk genpll 3 BCM_NSP_GENPLL_USB_PHY_REF_CLK + iprocfast genpll 4 BCM_NSP_GENPLL_IPROCFAST_CLK + sata1 genpll 5 BCM_NSP_GENPLL_SATA1_CLK + sata2 genpll 6 BCM_NSP_GENPLL_SATA2_CLK + + lcpll0 crystal 0 BCM_NSP_LCPLL0 + pcie_phy lcpll0 1 BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK + sdio lcpll0 2 BCM_NSP_LCPLL0_SDIO_CLK + ddr_phy lcpll0 3 BCM_NSP_LCPLL0_DDR_PHY_CLK
Signature · 1 line
1.9.1
Stephen Boyd
AppliedRe: [PATCH v3 09/10] clk: iproc: define Broadcom NSP iProc clock binding
Quoted 5 lines · Jon Mason
Document the device tree bindings for Broadcom Northstar Plus architecture based clock controller
Signed-off-by Jon Mason <[email protected]>---
Applied to clk-iproc
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH v3 10/10 clk: iproc: define Broadcom NS2 iProc clock binding
In reply to Jon MasonDocument the device tree bindings for Broadcom Northstar 2 architecture based clock controller
--- .../bindings/clock/brcm,iproc-clocks.txt | 48 ++++++++++++++++++++++ 1 file changed, 48 insertions(+)
Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt +48 -0
@@ -160,3 +160,51 @@ Northstar Plus. These clock IDs are defined in: pcie_phy lcpll0 1 BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK sdio lcpll0 2 BCM_NSP_LCPLL0_SDIO_CLK ddr_phy lcpll0 3 BCM_NSP_LCPLL0_DDR_PHY_CLK + +Northstar 2 +----------- +PLL and leaf clock compatible strings for Northstar 2 are: + "brcm,ns2-genpll-scr" + "brcm,ns2-genpll-sw" + "brcm,ns2-lcpll-ddr" + "brcm,ns2-lcpll-ports" + +The following table defines the set of PLL/clock index and ID for Northstar 2. +These clock IDs are defined in: + "include/dt-bindings/clock/bcm-ns2.h" + + Clock Source Index ID + --- ----- ----- --------- + crystal N/A N/A N/A + + genpll_scr crystal 0 BCM_NS2_GENPLL_SCR + scr genpll_scr 1 BCM_NS2_GENPLL_SCR_SCR_CLK + fs genpll_scr 2 BCM_NS2_GENPLL_SCR_FS_CLK + audio_ref genpll_scr 3 BCM_NS2_GENPLL_SCR_AUDIO_CLK + ch3_unused genpll_scr 4 BCM_NS2_GENPLL_SCR_CH3_UNUSED + ch4_unused genpll_scr 5 BCM_NS2_GENPLL_SCR_CH4_UNUSED + ch5_unused genpll_scr 6 BCM_NS2_GENPLL_SCR_CH5_UNUSED + + genpll_sw crystal 0 BCM_NS2_GENPLL_SW + rpe genpll_sw 1 BCM_NS2_GENPLL_SW_RPE_CLK + 250 genpll_sw 2 BCM_NS2_GENPLL_SW_250_CLK + nic genpll_sw 3 BCM_NS2_GENPLL_SW_NIC_CLK + chimp genpll_sw 4 BCM_NS2_GENPLL_SW_CHIMP_CLK + port genpll_sw 5 BCM_NS2_GENPLL_SW_PORT_CLK + sdio genpll_sw 6 BCM_NS2_GENPLL_SW_SDIO_CLK + + lcpll_ddr crystal 0 BCM_NS2_LCPLL_DDR + pcie_sata_usb lcpll_ddr 1 BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK + ddr lcpll_ddr 2 BCM_NS2_LCPLL_DDR_DDR_CLK + ch2_unused lcpll_ddr 3 BCM_NS2_LCPLL_DDR_CH2_UNUSED + ch3_unused lcpll_ddr 4 BCM_NS2_LCPLL_DDR_CH3_UNUSED + ch4_unused lcpll_ddr 5 BCM_NS2_LCPLL_DDR_CH4_UNUSED + ch5_unused lcpll_ddr 6 BCM_NS2_LCPLL_DDR_CH5_UNUSED + + lcpll_ports crystal 0 BCM_NS2_LCPLL_PORTS + wan lcpll_ports 1 BCM_NS2_LCPLL_PORTS_WAN_CLK + rgmii lcpll_ports 2 BCM_NS2_LCPLL_PORTS_RGMII_CLK + ch2_unused lcpll_ports 3 BCM_NS2_LCPLL_PORTS_CH2_UNUSED + ch3_unused lcpll_ports 4 BCM_NS2_LCPLL_PORTS_CH3_UNUSED + ch4_unused lcpll_ports 5 BCM_NS2_LCPLL_PORTS_CH4_UNUSED + ch5_unused lcpll_ports 6 BCM_NS2_LCPLL_PORTS_CH5_UNUSED
Signature · 1 line
1.9.1
Stephen Boyd
AppliedRe: [PATCH v3 10/10] clk: iproc: define Broadcom NS2 iProc clock binding
Quoted 5 lines · Jon Mason
Document the device tree bindings for Broadcom Northstar 2 architecture based clock controller
Signed-off-by Jon Mason <[email protected]>---
Applied to clk-iproc
Signature · 2 lines
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Quoted 8 lines · Jon Mason
v3 - Added a patch to fix cygnus clk link failures, and added back the DT documentation patches that were removed from v2.
v2 - Added a patch to change the Cygnus clk macros to uppercase, removed the device tree changes from the series (will send out those as an RFC), and other minor changes that Stephen Boyd requested.
Quoted 11 lines
This patch series adds support for the Broadcom Northstar, Northstar Plus, and Northstar 2 clocks. Some slight modifications were necessary to clk-iproc-pll to get Northstar and Northstar Plus working, due to differences in register layout. This is the reason why the first patch is necessary. Some more modifications were necessary to clk-iproc-pll to get Northstar 2 working, due to differences in register layout (and resulting fallout in Cygnus and NSP). This is the reason why the sixth and seventh patches are necessary. The fifth patch is clean-up to prevent accidentally forgetting to adjust for the base write errata (which happened a few times, but was caught in internal review).
Can you please use git cover-letter format where the diffstat for the series is shown? Without that information here I started applying patches until I realized this added dt-bindings headers, thus probably needing some stable clk branch to pull into arm-soc.
Signature · 2 lines
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Quoted 21 lines · Stephen Boyd
Quoted 8 lines · Jon Mason
v3 - Added a patch to fix cygnus clk link failures, and added back the DT documentation patches that were removed from v2.
v2 - Added a patch to change the Cygnus clk macros to uppercase, removed the device tree changes from the series (will send out those as an RFC), and other minor changes that Stephen Boyd requested.
Quoted 11 lines
This patch series adds support for the Broadcom Northstar, Northstar Plus, and Northstar 2 clocks. Some slight modifications were necessary to clk-iproc-pll to get Northstar and Northstar Plus working, due to differences in register layout. This is the reason why the first patch is necessary. Some more modifications were necessary to clk-iproc-pll to get Northstar 2 working, due to differences in register layout (and resulting fallout in Cygnus and NSP). This is the reason why the sixth and seventh patches are necessary. The fifth patch is clean-up to prevent accidentally forgetting to adjust for the base write errata (which happened a few times, but was caught in internal review).
Quoted 4 lines
Can you please use git cover-letter format where the diffstat for the series is shown? Without that information here I started applying patches until I realized this added dt-bindings headers, thus probably needing some stable clk branch to pull into arm-soc.
My apologies. I will do so in the future.
Thanks,
Jon
Quoted 4 lines
Signature · 3 lines
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