dt-bindings: drm/msm: Update bindings for MDP5
PATCH 1/2 dt-bindings: drm/msm: Update bindings for MDP5
MDP5 has a different compatible string (which causes checkpatch warnings when we try to add MDP5 device nodes). It also has different list of clocks.
Update the bindings for MDP5.
--- Documentation/devicetree/bindings/drm/msm/mdp.txt | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-)
Documentation/devicetree/bindings/drm/msm/mdp.txt +16 -7
@@ -3,18 +3,27 @@ Qualcomm adreno/snapdragon display controller Required properties: - compatible: * "qcom,mdp" - mdp4 + * "qcom,mdss_mdp" - mdp5 - reg: Physical base address and length of the controller's registers. - interrupts: The interrupt signal from the display controller. - connectors: array of phandles for output device(s) - clocks: device clocks See ../clocks/clock-bindings.txt for details. -- clock-names: the following clocks are required: - * "core_clk" - * "iface_clk" - * "lut_clk" - * "src_clk" - * "hdmi_clk" - * "mpd_clk" +- clock-names: the following clocks are required. + For MDP4: + * "core_clk" + * "iface_clk" + * "lut_clk" + * "src_clk" + * "hdmi_clk" + * "mdp_clk" + For MDP5: + * "bus_clk" + * "iface_clk" + * "core_clk_src" + * "core_clk" + * "lut_clk" (some MDP5 versions may not need this) + * "vsync_clk" Optional properties: - gpus: phandle for gpu device
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PATCH 2/2 arm64: dtsi: Add device nodes for GPU and MDSS on MSM8916
Add device nodes for gpu, mdp and dsi blocks.
The gpu and dsi nodes are missing the 'power-domains' property needed for configuring GDSC. This needs to be added when its available.
--- arch/arm64/boot/dts/qcom/msm8916.dtsi | 105 ++++++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+)
arch/arm64/boot/dts/qcom/msm8916.dtsi +105 -0
@@ -391,6 +391,111 @@ interrupt-controller; #interrupt-cells = <4>; }; + + gpu: qcom,adreno-3xx@01c00000 { + compatible = "qcom,adreno-3xx"; + #stream-id-cells = <16>; + reg = <0x01c00000 0x20000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = <GIC_SPI 33 IRQ_TYPE_NONE>; + interrupt-names = "kgsl_3d0_irq"; + clocks = + <&gcc GCC_OXILI_GFX3D_CLK>, + <&gcc GCC_OXILI_AHB_CLK>, + <&gcc GCC_OXILI_GMEM_CLK>, + <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_BIMC_GPU_CLK>, + <&gcc GFX3D_CLK_SRC>; + clock-names = + "core_clk", + "iface_clk", + "mem_clk", + "mem_iface_clk", + "alt_mem_iface_clk", + "gfx3d_clk_src"; + + qcom,chipid = <0x03000600>; + qcom,gpu-pwrlevels { + compatible = "qcom,gpu-pwrlevels"; + qcom,gpu-pwrlevel@0 { + qcom,gpu-freq = <400000000>; + }; + qcom,gpu-pwrlevel@1 { + qcom,gpu-freq = <19200000>; + }; + }; + }; + + mdss_mdp: qcom,mdss_mdp@1a00000 { + compatible = "qcom,mdss_mdp"; + reg = <0x1a00000 0x90000>, + <0x1ac8000 0x3000>; + reg-names = "mdp_phys", + "vbif_phys"; + interrupts = <GIC_SPI 72 IRQ_TYPE_NONE>; + + interrupt-controller; + #interrupt-cells = <1>; + + connectors = <&mdss_dsi0>; + gpus = <&gpu>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc MDP_CLK_SRC>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names = "iface_clk", + "bus_clk", + "core_clk_src", + "core_clk", + "vsync_clk"; + }; + + mdss_dsi0: qcom,mdss_dsi@1a98000 { + compatible = "qcom,mdss-dsi-ctrl"; + qcom,dsi-host-index = <0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1a98000 0x25c>; + reg-names = "dsi_ctrl"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 IRQ_TYPE_NONE>; + + clocks = <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>, + <&gcc BYTE0_CLK_SRC>, + <&gcc PCLK0_CLK_SRC>; + clock-names = "mdp_core_clk", + "iface_clk", + "bus_clk", + "byte_clk", + "pixel_clk", + "core_clk", + "byte_clk_src", + "pixel_clk_src"; + qcom,dsi-phy = <&mdss_dsi_phy0>; + status = "disabled"; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy@1a98300 { + compatible = "qcom,dsi-phy-28nm-lp"; + qcom,dsi-phy-index = <0>; + reg = <0x1a98300 0xd4>, + <0x1a98500 0x280>, + <0x1a98780 0x30>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + clocks = <&gcc GCC_MDSS_AHB_CLK>; + clock-names = "iface_clk"; + status = "disabled"; + }; }; };
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Quoted 16 lines · Archit Taneja
MDP5 has a different compatible string (which causes checkpatch warnings when we try to add MDP5 device nodes). It also has different list of clocks.
Update the bindings for MDP5.
Signed-off-by Archit Taneja <[email protected]>--- Documentation/devicetree/bindings/drm/msm/mdp.txt | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-)Documentation/devicetree/bindings/drm/msm/mdp.txt +0
-0
Documentation/devicetree/bindings/drm/msm/mdp.txt Qualcomm adreno/snapdragon display controller · line 6
Quoted 4 lines
Documentation/devicetree/bindings/drm/msm/mdp.txt +1
-0@@ -3,18 +3,27 @@ Qualcomm adreno/snapdragon display controller Required properties: - compatible: * "qcom,mdp" - mdp4 + * "qcom,mdss_mdp" - mdp5
Wouldn't it be better to name these "qcom,mdp4" and "qcom,mdp5" so that we don't have to rely on some magic detection mechanism to support future versions?
Regards,
Bjorn
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Quoted 12 lines · Bjorn Andersson
Quoted 11 lines · Archit Taneja
MDP5 has a different compatible string (which causes checkpatch warnings when we try to add MDP5 device nodes). It also has different list of clocks.
Update the bindings for MDP5.
Signed-off-by Archit Taneja <[email protected]>--- Documentation/devicetree/bindings/drm/msm/mdp.txt | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-)
Quoted 13 lines
Documentation/devicetree/bindings/drm/msm/mdp.txt Qualcomm adreno/snapdragon display controller · line 6
Quoted 9 lines
Documentation/devicetree/bindings/drm/msm/mdp.txt +1
-0@@ -3,18 +3,27 @@ Qualcomm adreno/snapdragon display controller Required properties: - compatible: * "qcom,mdp" - mdp4 + * "qcom,mdss_mdp" - mdp5Wouldn't it be better to name these "qcom,mdp4" and "qcom,mdp5" so that we don't have to rely on some magic detection mechanism to support future versions?
My guess is that compatibility string "mdss_mdp" came from the downstream kernels. Chips having MDP4 were supported on downstream kernels that preceded DT.
Since we don't have any MDP DT upstream, I think we could go with the string names you suggested. It might break things for people who might try to use an old downstream dts file with a new kernel. But that doesn't sound like the worst thing.
Archit
Quoted 4 lines
Regards,
Bjorn
Signature · 5 lines
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Quoted 35 lines · Archit Taneja
Quoted 16 lines · Bjorn Andersson
Quoted 13 lines · Archit Taneja
MDP5 has a different compatible string (which causes checkpatch warnings when we try to add MDP5 device nodes). It also has different list of clocks.
Update the bindings for MDP5.
Signed-off-by Archit Taneja <[email protected]>--- Documentation/devicetree/bindings/drm/msm/mdp.txt | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-)Quoted 15 lines
Documentation/devicetree/bindings/drm/msm/mdp.txt Qualcomm adreno/snapdragon display controller · line 6
Quoted 10 lines
Documentation/devicetree/bindings/drm/msm/mdp.txt +1
-0@@ -3,18 +3,27 @@ Qualcomm adreno/snapdragon display controller Required properties: - compatible: * "qcom,mdp" - mdp4 + * "qcom,mdss_mdp" - mdp5Wouldn't it be better to name these "qcom,mdp4" and "qcom,mdp5" so that we don't have to rely on some magic detection mechanism to support future versions?
Quoted 8 lines
My guess is that compatibility string "
mdss_mdp" came from the downstream kernels. Chips having MDP4 were supported on downstream kernels that preceded DT.Since we don't have any MDP DT upstream, I think we could go with the string names you suggested. It might break things for people who might try to use an old downstream dts file with a new kernel. But that doesn't sound like the worst thing.
it would break things for downstream 3.10/mdp5 dt files.. but what I'd suggest is to make the code look for both qcom,mdp5 and qcom,mdss_mdp but only document the former
BR,
-R
Quoted 10 lines
Archit
Quoted 4 lines
Regards,
Bjorn--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation
Quoted 40 lines · Rob Clark
Quoted 39 lines · Archit Taneja
Quoted 16 lines · Bjorn Andersson
Quoted 13 lines · Archit Taneja
MDP5 has a different compatible string (which causes checkpatch warnings when we try to add MDP5 device nodes). It also has different list of clocks.
Update the bindings for MDP5.
Signed-off-by Archit Taneja <[email protected]>--- Documentation/devicetree/bindings/drm/msm/mdp.txt | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-)Quoted 15 lines
Documentation/devicetree/bindings/drm/msm/mdp.txt Qualcomm adreno/snapdragon display controller · line 6
Quoted 10 lines
Documentation/devicetree/bindings/drm/msm/mdp.txt +1
-0@@ -3,18 +3,27 @@ Qualcomm adreno/snapdragon display controller Required properties: - compatible: * "qcom,mdp" - mdp4 + * "qcom,mdss_mdp" - mdp5Wouldn't it be better to name these "qcom,mdp4" and "qcom,mdp5" so that we don't have to rely on some magic detection mechanism to support future versions?
My guess is that compatibility string "
mdss_mdp" came from the downstream kernels. Chips having MDP4 were supported on downstream kernels that preceded DT.
Quoted 8 lines
Quoted 4 lines
Since we don't have any MDP DT upstream, I think we could go with the string names you suggested. It might break things for people who might try to use an old downstream dts file with a new kernel. But that doesn't sound like the worst thing.
it would break things for downstream 3.10/mdp5 dt files.. but what I'd suggest is to make the code look for both qcom,mdp5 and qcom,mdss_mdp but only document the former
That's a good idea. I'll update the patches to do that.
Archit
Quoted 14 lines
BR,
-RQuoted 10 lines
Archit
Quoted 4 lines
Regards,
Bjorn--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation
Signature · 2 lines
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