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Patch "clk: samsung: fix cpu clock's flags checking" has been added to the 4.2-stable tree

PATCH [email protected] 1 participant 1 message Oct 18, 2015

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Stable branch Common clk Samsung SoC clock drivers
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This is a note to let you know that I've just added the patch titled

clk: samsung: fix cpu clock's flags checking

to the 4.2-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
clk-samsung-fix-cpu-clock-s-flags-checking.patch
and it can be found in the queue-4.2 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

Quoted 1 line

From 9e294bf88a583825a413df408b9fe9e658fb93ac Mon Sep 17 00:00:00 2001

From: Bartlomiej Zolnierkiewicz <[email protected]>
Date: Fri, 28 Aug 2015 13:49:35 +0200
Subject: clk: samsung: fix cpu clock's flags checking

From: Bartlomiej Zolnierkiewicz <[email protected]>

commit 9e294bf88a583825a413df408b9fe9e658fb93ac upstream.

CLK_CPU_HAS_DIV1 and CLK_CPU_NEEDS_DEBUG_ALT_DIV masks were incorrectly used as a bit numbers. Fix it.

Tested on Exynos4210 based Origen board and on Exynos5250 based Arndale board.

Cc Tomasz Figa <[email protected]>
Cc Michael Turquette <[email protected]>
Cc Thomas Abraham <[email protected]>
Fixes ddeac8d96 ("clk: samsung: add infrastructure to register cpu clocks")
Reported-by Dan Carpenter <[email protected]>
Reviewed-by Krzysztof Kozlowski <[email protected]>
Reviewed-by Javier Martinez Canillas <[email protected]>
Acked-by Sylwester Nawrocki <[email protected]>
Signed-off-by Bartlomiej Zolnierkiewicz <[email protected]>
Signed-off-by Stephen Boyd <[email protected]>
Signed-off-by Greg Kroah-Hartman <[email protected]>
---
 drivers/clk/samsung/clk-cpu.c |   10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)
drivers/clk/samsung/clk-cpu.c +5 -5
@@ -161,7 +161,7 @@ static int exynos_cpuclk_pre_rate_change
 	 * the values for DIV_COPY and DIV_HPM dividers need not be set.
 	 */
 	div0 = cfg_data->div0;
-	if (test_bit(CLK_CPU_HAS_DIV1, &cpuclk->flags)) {
+	if (cpuclk->flags & CLK_CPU_HAS_DIV1) {
 		div1 = cfg_data->div1;
 		if (readl(base + E4210_SRC_CPU) & E4210_MUX_HPM_MASK)
 			div1 = readl(base + E4210_DIV_CPU1) &

@@ -182,7 +182,7 @@ static int exynos_cpuclk_pre_rate_change
 		alt_div = DIV_ROUND_UP(alt_prate, tmp_rate) - 1;
 		WARN_ON(alt_div >= MAX_DIV);
 
-		if (test_bit(CLK_CPU_NEEDS_DEBUG_ALT_DIV, &cpuclk->flags)) {
+		if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
 			/*
 			 * In Exynos4210, ATB clock parent is also mout_core. So
 			 * ATB clock also needs to be mantained at safe speed.

@@ -203,7 +203,7 @@ static int exynos_cpuclk_pre_rate_change
 	writel(div0, base + E4210_DIV_CPU0);
 	wait_until_divider_stable(base + E4210_DIV_STAT_CPU0, DIV_MASK_ALL);
 
-	if (test_bit(CLK_CPU_HAS_DIV1, &cpuclk->flags)) {
+	if (cpuclk->flags & CLK_CPU_HAS_DIV1) {
 		writel(div1, base + E4210_DIV_CPU1);
 		wait_until_divider_stable(base + E4210_DIV_STAT_CPU1,
 				DIV_MASK_ALL);

@@ -222,7 +222,7 @@ static int exynos_cpuclk_post_rate_chang
 	unsigned long mux_reg;
 
 	/* find out the divider values to use for clock data */
-	if (test_bit(CLK_CPU_NEEDS_DEBUG_ALT_DIV, &cpuclk->flags)) {
+	if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
 		while ((cfg_data->prate * 1000) != ndata->new_rate) {
 			if (cfg_data->prate == 0)
 				return -EINVAL;

@@ -237,7 +237,7 @@ static int exynos_cpuclk_post_rate_chang
 	writel(mux_reg & ~(1 << 16), base + E4210_SRC_CPU);
 	wait_until_mux_stable(base + E4210_STAT_CPU, 16, 1);
 
-	if (test_bit(CLK_CPU_NEEDS_DEBUG_ALT_DIV, &cpuclk->flags)) {
+	if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
 		div |= (cfg_data->div0 & E4210_DIV0_ATB_MASK);
 		div_mask |= E4210_DIV0_ATB_MASK;
 	}

Patches currently in stable-queue which might be from [email protected] are

queue-4.2/clk-samsung-fix-cpu-clock-s-flags-checking.patch