spi: pxa2xx: move debug messages to pump_transfer()

PATCH In review Jarkko Nikula 3 participants 19 messages Oct 22, 2015 – Oct 30, 2015 8 messages not in the archive

Subsystems (3)

SPI PXA2xx/PXA3xx support Intel LPSS (Low Power SubSystem) drivers

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Jarkko Nikula

author

2015-10-22 13:44 UTC #0 lore raw

PATCH 1/7 spi: pxa2xx: move debug messages to pump_transfer()

From: Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/[email protected]>

The speed can be changed from transfer to transfer, that's why the messages do not depict the actual values during ->setup(). Move debug messages from ->setup() to pump_transfers(). Get rid of leftovers as well.

Signed-off-by Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/[email protected]>

Signed-off-by Jarkko Nikula <jarkko.nikula-VuQAYsv1563Yd54FQh9/[email protected]>

---
 drivers/spi/spi-pxa2xx.c | 28 +++++++++++-----------------
 1 file changed, 11 insertions(+), 17 deletions(-)

drivers/spi/spi-pxa2xx.c +11 ~~-17~~

index 82493c26d4e0..573a28b13a09 100644
@@ -959,7 +959,18 @@ static void pump_transfers(unsigned long data)
 					     "pump_transfers: DMA burst size reduced to match bits_per_word\n");
 	}
 
+	/* NOTE:  PXA25x_SSP _could_ use external clocking ... */
 	cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
+	if (!pxa25x_ssp_comp(drv_data))
+		dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
+			drv_data->master->max_speed_hz
+				/ (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
+			chip->enable_dma ? "DMA" : "PIO");
+	else
+		dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
+			drv_data->master->max_speed_hz / 2
+				/ (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
+			chip->enable_dma ? "DMA" : "PIO");
 
 	message->state = RUNNING_STATE;

@@ -1103,9 +1114,7 @@ static int setup(struct spi_device *spi)
 	struct chip_data *chip;
 	const struct lpss_config *config;
 	struct driver_data *drv_data = spi_master_get_devdata(spi->master);
-	unsigned int clk_div;
 	uint tx_thres, tx_hi_thres, rx_thres;
-	u32 cr0;
 
 	switch (drv_data->ssp_type) {
 	case QUARK_X1000_SSP:

@@ -1196,8 +1205,6 @@ static int setup(struct spi_device *spi)
 		}
 	}
 
-	clk_div = pxa2xx_ssp_get_clk_div(drv_data, chip, spi->max_speed_hz);
-
 	switch (drv_data->ssp_type) {
 	case QUARK_X1000_SSP:
 		chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)

@@ -1218,19 +1225,6 @@ static int setup(struct spi_device *spi)
 	if (spi->mode & SPI_LOOP)
 		chip->cr1 |= SSCR1_LBM;
 
-	/* NOTE:  PXA25x_SSP _could_ use external clocking ... */
-	cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, spi->bits_per_word);
-	if (!pxa25x_ssp_comp(drv_data))
-		dev_dbg(&spi->dev, "%u Hz actual, %s\n",
-			drv_data->master->max_speed_hz
-				/ (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
-			chip->enable_dma ? "DMA" : "PIO");
-	else
-		dev_dbg(&spi->dev, "%u Hz actual, %s\n",
-			drv_data->master->max_speed_hz / 2
-				/ (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
-			chip->enable_dma ? "DMA" : "PIO");
-
 	if (spi->bits_per_word <= 8) {
 		chip->n_bytes = 1;
 		chip->read = u8_reader;

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Jarkko Nikula

author

2015-10-22 13:44 UTC #2 lore raw

PATCH 2/7 spi: pxa2xx: derive struct chip_data from struct drv_data

From: Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/[email protected]>

Since we call pxa2xx_ssp_get_clk_div() from pump_transfers() we may derive pointer to struct chip_data from struct drv_data like it's done in the rest of the functions. This will make it less errorprone.

Signed-off-by Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/[email protected]>

Signed-off-by Jarkko Nikula <jarkko.nikula-VuQAYsv1563Yd54FQh9/[email protected]>

---
 drivers/spi/spi-pxa2xx.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

drivers/spi/spi-pxa2xx.c +3 -2

index 573a28b13a09..e02ea46168eb 100644
@@ -818,8 +818,9 @@ static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
 }
 
 static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
-					   struct chip_data *chip, int rate)
+					   int rate)
 {
+	struct chip_data *chip = drv_data->cur_chip;
 	unsigned int clk_div;
 
 	switch (drv_data->ssp_type) {

@@ -925,7 +926,7 @@ static void pump_transfers(unsigned long data)
 	bits = transfer->bits_per_word;
 	speed = transfer->speed_hz;
 
-	clk_div = pxa2xx_ssp_get_clk_div(drv_data, chip, speed);
+	clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
 
 	if (bits <= 8) {
 		drv_data->n_bytes = 1;

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Mark Brown

2015-10-22 23:57 UTC #4 lore raw

Applied "spi: pxa2xx: derive struct chip_data from struct drv_data" to the spi tree

The patch

spi: pxa2xx: derive struct chip_data from struct drv_data

has been applied to the spi tree at

git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git

All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying to this mail.

Thanks,
Mark

Quoted 1 line

From d2c2f6a47633a36bc8db8c802f7c284da36a7a53 Mon Sep 17 00:00:00 2001

From: Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/[email protected]>
Date: Thu, 22 Oct 2015 16:44:40 +0300
Subject: [PATCH] spi: pxa2xx: derive struct chip_data from struct drv_data

Signed-off-by Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/[email protected]>

Signed-off-by Jarkko Nikula <jarkko.nikula-VuQAYsv1563Yd54FQh9/[email protected]>

Signed-off-by Mark Brown <[email protected]>

---
 drivers/spi/spi-pxa2xx.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

drivers/spi/spi-pxa2xx.c +3 -2

index 986a291..4fddc2a 100644
@@ -814,8 +814,9 @@ static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
 }
 
 static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
-					   struct chip_data *chip, int rate)
+					   int rate)
 {
+	struct chip_data *chip = drv_data->cur_chip;
 	unsigned int clk_div;
 
 	switch (drv_data->ssp_type) {

@@ -921,7 +922,7 @@ static void pump_transfers(unsigned long data)
 	bits = transfer->bits_per_word;
 	speed = transfer->speed_hz;
 
-	clk_div = pxa2xx_ssp_get_clk_div(drv_data, chip, speed);
+	clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
 
 	if (bits <= 8) {
 		drv_data->n_bytes = 1;

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Robert Jarzmik

Acked-by

2015-10-25 11:42 UTC #5 lore raw

Re: [PATCH 2/7] spi: pxa2xx: derive struct chip_data from struct drv_data

In reply to a message not in the archive

Quoted 8 lines · Jarkko Nikula

From: Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/[email protected]>
Since we call pxa2xx_ssp_get_clk_div() from pump_transfers() we may derive pointer to struct chip_data from struct drv_data like it's done in the rest of the functions. This will make it less errorprone.
Signed-off-by Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/[email protected]>
Signed-off-by Jarkko Nikula <jarkko.nikula-VuQAYsv1563Yd54FQh9/[email protected]>

Acked-by Robert Jarzmik <[email protected]>

Cheers.

--
Robert
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Jarkko Nikula

author

2015-10-22 13:44 UTC #6 lore raw

PATCH 3/7 spi: pxa2xx: Convert unique ID string of ACPI device as unsigned integer

In reply to a message not in the archive

Andy noticed numeric unique device ID is unsigned integer so convert it using kstrtouint(). Actually integer in ACPI 2.0 and later is 64 bits litte-endian unsigned integer but quite certainly having so big value here would mean something extra than just the SPI bus number so it won't hurt to assume only lower 32 bits carry the bus number for now.

Signed-off-by Jarkko Nikula <jarkko.nikula-VuQAYsv1563Yd54FQh9/[email protected]>

Cc Mika Westerberg <mika.westerberg-VuQAYsv1563Yd54FQh9/[email protected]>

Cc Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/[email protected]>

---
 drivers/spi/spi-pxa2xx.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

drivers/spi/spi-pxa2xx.c +3 -2

index e02ea46168eb..48fdcb6a7f79 100644
@@ -1309,7 +1309,8 @@ pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
 	struct resource *res;
 	const struct acpi_device_id *adev_id = NULL;
 	const struct pci_device_id *pcidev_id = NULL;
-	int devid, type;
+	unsigned int devid;
+	int type;
 
 	adev = ACPI_COMPANION(&pdev->dev);
 	if (!adev)

@@ -1356,7 +1357,7 @@ pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
 	ssp->pdev = pdev;
 
 	ssp->port_id = -1;
-	if (adev->pnp.unique_id && !kstrtoint(adev->pnp.unique_id, 0, &devid))
+	if (adev->pnp.unique_id && !kstrtouint(adev->pnp.unique_id, 0, &devid))
 		ssp->port_id = devid;
 
 	pdata->num_chipselect = 1;

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Mark Brown

2015-10-22 23:57 UTC #8 lore raw

Applied "spi: pxa2xx: Convert unique ID string of ACPI device as unsigned integer" to the spi tree

The patch

spi: pxa2xx: Convert unique ID string of ACPI device as unsigned integer

has been applied to the spi tree at

git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git

If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying to this mail.

Thanks,
Mark

Quoted 1 line

From 3b8b6d05942ef5dd952674e7420600f762166e22 Mon Sep 17 00:00:00 2001

From: Jarkko Nikula <jarkko.nikula-VuQAYsv1563Yd54FQh9/[email protected]>
Date: Thu, 22 Oct 2015 16:44:41 +0300
Subject: [PATCH] spi: pxa2xx: Convert unique ID string of ACPI device as
unsigned integer

Signed-off-by Jarkko Nikula <jarkko.nikula-VuQAYsv1563Yd54FQh9/[email protected]>

Cc Mika Westerberg <mika.westerberg-VuQAYsv1563Yd54FQh9/[email protected]>

Cc Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/[email protected]>

Signed-off-by Mark Brown <[email protected]>

---
 drivers/spi/spi-pxa2xx.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

drivers/spi/spi-pxa2xx.c +3 -2

index 4fddc2a..db9016b 100644
@@ -1305,7 +1305,8 @@ pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
 	struct resource *res;
 	const struct acpi_device_id *adev_id = NULL;
 	const struct pci_device_id *pcidev_id = NULL;
-	int devid, type;
+	unsigned int devid;
+	int type;
 
 	adev = ACPI_COMPANION(&pdev->dev);
 	if (!adev)

@@ -1352,7 +1353,7 @@ pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
 	ssp->pdev = pdev;
 
 	ssp->port_id = -1;
-	if (adev->pnp.unique_id && !kstrtoint(adev->pnp.unique_id, 0, &devid))
+	if (adev->pnp.unique_id && !kstrtouint(adev->pnp.unique_id, 0, &devid))
 		ssp->port_id = devid;
 
 	pdata->num_chipselect = 1;

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Jarkko Nikula

author

2015-10-22 13:44 UTC #9 lore raw

PATCH 4/7 spi: pxa2xx: Save other reg_cs_ctrl bits when configuring chip select

In reply to a message not in the archive

Upcoming Intel platforms use LPSS SPI_CS_CONTROL register bits 15:12 for configuring the chip select polarities. Touch only chip select SW mode and state bits when enabling the software chip select control in order to not clear any other bits in the register.

Signed-off-by Jarkko Nikula <jarkko.nikula-VuQAYsv1563Yd54FQh9/[email protected]>

---
 drivers/spi/spi-pxa2xx.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

drivers/spi/spi-pxa2xx.c +3 -1

index 48fdcb6a7f79..615f6c57a090 100644
@@ -249,7 +249,9 @@ static void lpss_ssp_setup(struct driver_data *drv_data)
 	drv_data->lpss_base = drv_data->ioaddr + config->offset;
 
 	/* Enable software chip select control */
-	value = SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH;
+	value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
+	value &= ~(SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH);
+	value |= SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH;
 	__lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
 
 	/* Enable multiblock DMA transfers */

Signature · 6 lines

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Mark Brown

2015-10-22 23:57 UTC #11 lore raw

Applied "spi: pxa2xx: Save other reg_cs_ctrl bits when configuring chip select" to the spi tree

The patch

spi: pxa2xx: Save other reg_cs_ctrl bits when configuring chip select

has been applied to the spi tree at

git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git

If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying to this mail.

Thanks,
Mark

Quoted 1 line

From 0e8972187971ac6c29a9e5899fa6c555c739237c Mon Sep 17 00:00:00 2001

From: Jarkko Nikula <jarkko.nikula-VuQAYsv1563Yd54FQh9/[email protected]>
Date: Thu, 22 Oct 2015 16:44:42 +0300
Subject: [PATCH] spi: pxa2xx: Save other reg_cs_ctrl bits when configuring
chip select

Signed-off-by Jarkko Nikula <jarkko.nikula-VuQAYsv1563Yd54FQh9/[email protected]>

Signed-off-by Mark Brown <[email protected]>

---
 drivers/spi/spi-pxa2xx.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

drivers/spi/spi-pxa2xx.c +3 -1

index db9016b..4dc5660 100644
@@ -249,7 +249,9 @@ static void lpss_ssp_setup(struct driver_data *drv_data)
 	drv_data->lpss_base = drv_data->ioaddr + config->offset;
 
 	/* Enable software chip select control */
-	value = SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH;
+	value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
+	value &= ~(SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH);
+	value |= SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH;
 	__lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
 
 	/* Enable multiblock DMA transfers */

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Robert Jarzmik

Acked-by

2015-10-25 11:49 UTC #12 lore raw

Re: [PATCH 4/7] spi: pxa2xx: Save other reg_cs_ctrl bits when configuring chip select

In reply to a message not in the archive

Quoted 6 lines · Jarkko Nikula

Upcoming Intel platforms use LPSS SPI_CS_CONTROL register bits 15:12 for configuring the chip select polarities. Touch only chip select SW mode and state bits when enabling the software chip select control in order to not clear any other bits in the register.
Signed-off-by Jarkko Nikula <jarkko.nikula-VuQAYsv1563Yd54FQh9/[email protected]>

Acked-by Robert Jarzmik <[email protected]>

Cheers.

Signature · 5 lines

Robert
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Jarkko Nikula

author

2015-10-22 13:44 UTC #13 lore raw

PATCH 5/7 spi: pxa2xx: Align a few defines

In reply to a message not in the archive

Add more indentation to define lines for making them aligned with the longest one. They would look messy after adding more long defines.

Signed-off-by Jarkko Nikula <jarkko.nikula-VuQAYsv1563Yd54FQh9/[email protected]>

---
 drivers/spi/spi-pxa2xx.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

drivers/spi/spi-pxa2xx.c +3 -3

index 615f6c57a090..672963653d3b 100644
@@ -61,9 +61,9 @@ MODULE_ALIAS("platform:pxa2xx-spi");
 				| QUARK_X1000_SSCR1_TFT		\
 				| SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
 
-#define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
-#define SPI_CS_CONTROL_SW_MODE	BIT(0)
-#define SPI_CS_CONTROL_CS_HIGH	BIT(1)
+#define GENERAL_REG_RXTO_HOLDOFF_DISABLE	BIT(24)
+#define SPI_CS_CONTROL_SW_MODE			BIT(0)
+#define SPI_CS_CONTROL_CS_HIGH			BIT(1)
 
 struct lpss_config {
 	/* LPSS offset from drv_data->ioaddr */

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Mark Brown

2015-10-22 23:57 UTC #15 lore raw

Applied "spi: pxa2xx: Align a few defines" to the spi tree

The patch

spi: pxa2xx: Align a few defines

has been applied to the spi tree at

git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git

If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying to this mail.

Thanks,
Mark

Quoted 1 line

From ceb941afa5c38dae8e273089266c412d362c7963 Mon Sep 17 00:00:00 2001

From: Jarkko Nikula <jarkko.nikula-VuQAYsv1563Yd54FQh9/[email protected]>
Date: Thu, 22 Oct 2015 16:44:43 +0300
Subject: [PATCH] spi: pxa2xx: Align a few defines

Add more indentation to define lines for making them aligned with the longest one. They would look messy after adding more long defines.

Signed-off-by Jarkko Nikula <jarkko.nikula-VuQAYsv1563Yd54FQh9/[email protected]>

Signed-off-by Mark Brown <[email protected]>

---
 drivers/spi/spi-pxa2xx.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

drivers/spi/spi-pxa2xx.c +3 -3

index 4dc5660..0f6a6c8 100644
@@ -61,9 +61,9 @@ MODULE_ALIAS("platform:pxa2xx-spi");
 				| QUARK_X1000_SSCR1_TFT		\
 				| SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
 
-#define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
-#define SPI_CS_CONTROL_SW_MODE	BIT(0)
-#define SPI_CS_CONTROL_CS_HIGH	BIT(1)
+#define GENERAL_REG_RXTO_HOLDOFF_DISABLE	BIT(24)
+#define SPI_CS_CONTROL_SW_MODE			BIT(0)
+#define SPI_CS_CONTROL_CS_HIGH			BIT(1)
 
 struct lpss_config {
 	/* LPSS offset from drv_data->ioaddr */

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Robert Jarzmik

Acked-by

2015-10-25 11:50 UTC #16 lore raw

Re: [PATCH 5/7] spi: pxa2xx: Align a few defines

In reply to a message not in the archive

Quoted 4 lines · Jarkko Nikula

Add more indentation to define lines for making them aligned with the longest one. They would look messy after adding more long defines.
Signed-off-by Jarkko Nikula <jarkko.nikula-VuQAYsv1563Yd54FQh9/[email protected]>

Acked-by Robert Jarzmik <[email protected]>

Cheers.

Signature · 5 lines

Robert
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Jarkko Nikula

author

2015-10-22 13:44 UTC #17 lore raw

PATCH 6/7 spi: pxa2xx: Add support for multiple LPSS chip select signals

In reply to a message not in the archive

LPSS SPI devices in a successor of Intel Sunrisepoint can have up to 4 chip selects per port. SPI capabilities register bits 12:9 tell which are enabled. For simplicity we assume chip selects are enabled one after another without disabled chip selects between. For instance CS0 | CS1 | CS2 but not CS0 | CS1 | CS3.

This patch adds support for detecting the number of enabled chip selects and adds output control to those LPSS SPI ports that have more than one chip select signal.

Signed-off-by Jarkko Nikula <jarkko.nikula-VuQAYsv1563Yd54FQh9/[email protected]>

---
 drivers/spi/spi-pxa2xx.c | 48 +++++++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 43 insertions(+), 5 deletions(-)

drivers/spi/spi-pxa2xx.c +43 -5

index 672963653d3b..6851649d1b15 100644
@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <linux/bitops.h>
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/device.h>

@@ -64,6 +65,10 @@ MODULE_ALIAS("platform:pxa2xx-spi");
 #define GENERAL_REG_RXTO_HOLDOFF_DISABLE	BIT(24)
 #define SPI_CS_CONTROL_SW_MODE			BIT(0)
 #define SPI_CS_CONTROL_CS_HIGH			BIT(1)
+#define SPI_CS_CONTROL_CS_SEL_SHIFT		8
+#define SPI_CS_CONTROL_CS_SEL_MASK		(3 << SPI_CS_CONTROL_CS_SEL_SHIFT)
+#define SPI_CAPS_CS_EN_SHIFT			9
+#define SPI_CAPS_CS_EN_MASK			(0xf << SPI_CAPS_CS_EN_SHIFT)
 
 struct lpss_config {
 	/* LPSS offset from drv_data->ioaddr */

@@ -72,6 +77,7 @@ struct lpss_config {
 	int reg_general;
 	int reg_ssp;
 	int reg_cs_ctrl;
+	int reg_capabilities;
 	/* FIFO thresholds */
 	u32 rx_threshold;
 	u32 tx_threshold_lo;

@@ -85,6 +91,7 @@ static const struct lpss_config lpss_platforms[] = {
 		.reg_general = 0x08,
 		.reg_ssp = 0x0c,
 		.reg_cs_ctrl = 0x18,
+		.reg_capabilities = -1,
 		.rx_threshold = 64,
 		.tx_threshold_lo = 160,
 		.tx_threshold_hi = 224,

@@ -94,6 +101,7 @@ static const struct lpss_config lpss_platforms[] = {
 		.reg_general = 0x08,
 		.reg_ssp = 0x0c,
 		.reg_cs_ctrl = 0x18,
+		.reg_capabilities = -1,
 		.rx_threshold = 64,
 		.tx_threshold_lo = 160,
 		.tx_threshold_hi = 224,

@@ -103,6 +111,7 @@ static const struct lpss_config lpss_platforms[] = {
 		.reg_general = -1,
 		.reg_ssp = 0x20,
 		.reg_cs_ctrl = 0x24,
+		.reg_capabilities = 0xfc,
 		.rx_threshold = 1,
 		.tx_threshold_lo = 32,
 		.tx_threshold_hi = 56,

@@ -271,15 +280,34 @@ static void lpss_ssp_setup(struct driver_data *drv_data)
 static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable)
 {
 	const struct lpss_config *config;
-	u32 value;
+	u32 value, cs;
 
 	config = lpss_get_config(drv_data);
 
 	value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
-	if (enable)
+	if (enable) {
+		cs = drv_data->cur_msg->spi->chip_select;
+		cs <<= SPI_CS_CONTROL_CS_SEL_SHIFT;
+		if (cs != (value & SPI_CS_CONTROL_CS_SEL_MASK)) {
+			/*
+			 * When switching another chip select output active
+			 * the output must be selected first and wait 2 ssp_clk
+			 * cycles before changing state to active. Otherwise
+			 * a short glitch will occur on the previous chip
+			 * select since output select is latched but state
+			 * control is not.
+			 */
+			value &= ~SPI_CS_CONTROL_CS_SEL_MASK;
+			value |= cs;
+			__lpss_ssp_write_priv(drv_data,
+					      config->reg_cs_ctrl, value);
+			ndelay(1000000000 /
+			       (drv_data->master->max_speed_hz / 2));
+		}
 		value &= ~SPI_CS_CONTROL_CS_HIGH;
-	else
+	} else {
 		value |= SPI_CS_CONTROL_CS_HIGH;
+	}
 	__lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
 }

@@ -1383,6 +1411,7 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
 	struct spi_master *master;
 	struct driver_data *drv_data;
 	struct ssp_device *ssp;
+	const struct lpss_config *config;
 	int status;
 	u32 tmp;

@@ -1422,7 +1451,6 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
 	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
 
 	master->bus_num = ssp->port_id;
-	master->num_chipselect = platform_info->num_chipselect;
 	master->dma_alignment = DMA_ALIGNMENT;
 	master->cleanup = cleanup;
 	master->setup = setup;

@@ -1505,8 +1533,18 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
 	if (!is_quark_x1000_ssp(drv_data))
 		pxa2xx_spi_write(drv_data, SSPSP, 0);
 
-	if (is_lpss_ssp(drv_data))
+	if (is_lpss_ssp(drv_data)) {
 		lpss_ssp_setup(drv_data);
+		config = lpss_get_config(drv_data);
+		if (config->reg_capabilities >= 0) {
+			tmp = __lpss_ssp_read_priv(drv_data,
+						   config->reg_capabilities);
+			tmp &= SPI_CAPS_CS_EN_MASK;
+			tmp >>= SPI_CAPS_CS_EN_SHIFT;
+			platform_info->num_chipselect = ffz(tmp);
+		}
+	}
+	master->num_chipselect = platform_info->num_chipselect;
 
 	tasklet_init(&drv_data->pump_transfers, pump_transfers,
 		     (unsigned long)drv_data);

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A message that is not in the archive (sent off-list or not yet received): 1445521485-2029-6-git-send-email-jarkko.nikula-VuQAYsv1563Yd54FQh9/[email protected]

Robert Jarzmik

2015-10-25 12:02 UTC #19 lore raw

Re: [PATCH 6/7] spi: pxa2xx: Add support for multiple LPSS chip select signals

Quoted 1 line · Jarkko Nikula

LPSS SPI devices in a successor of Intel Sunrisepoint can have up to 4 chip

is ?

Quoted 27 lines

selects per port. SPI capabilities register bits 12:9 tell which are enabled. For simplicity we assume chip selects are enabled one after another without disabled chip selects between. For instance CS0 | CS1 | CS2 but not CS0 | CS1 | CS3.
This patch adds support for detecting the number of enabled chip selects and adds output control to those LPSS SPI ports that have more than one chip select signal.
Signed-off-by Jarkko Nikula <jarkko.nikula-VuQAYsv1563Yd54FQh9/[email protected]>
---
 drivers/spi/spi-pxa2xx.c | 48 +++++++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 43 insertions(+), 5 deletions(-)
drivers/spi/spi-pxa2xx.c +1 -0
index 672963653d3b..6851649d1b15 100644
@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <linux/bitops.h>
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/device.h>

drivers/spi/spi-pxa2xx.c MODULE_ALIAS("platform:pxa2xx-spi"); · line 72

Quoted 8 lines

drivers/spi/spi-pxa2xx.c +4 -0

@@ -64,6 +65,10 @@ MODULE_ALIAS("platform:pxa2xx-spi");
 #define GENERAL_REG_RXTO_HOLDOFF_DISABLE	BIT(24)
 #define SPI_CS_CONTROL_SW_MODE			BIT(0)
 #define SPI_CS_CONTROL_CS_HIGH			BIT(1)
 
+#define SPI_CS_CONTROL_CS_SEL_SHIFT		8
+#define SPI_CS_CONTROL_CS_SEL_MASK		(3 << SPI_CS_CONTROL_CS_SEL_SHIFT)
+#define SPI_CAPS_CS_EN_SHIFT			9
+#define SPI_CAPS_CS_EN_MASK			(0xf << SPI_CAPS_CS_EN_SHIFT)

This is intel specific, not pxa oriented, right ?
If so, I'd like to have it namespaced, with LPSS or whatever you see fit.

drivers/spi/spi-pxa2xx.c static const struct lpss_config lpss_platforms[] = { · line 114

Quoted 5 lines

drivers/spi/spi-pxa2xx.c +1 -0

@@ -103,6 +111,7 @@ static const struct lpss_config lpss_platforms[] = {
 		.reg_general = -1,
 		.reg_ssp = 0x20,
 		.reg_cs_ctrl = 0x24,
+		.reg_capabilities = 0xfc,

Immediate value ? I suppose a defines usage was not possible here ?

Quoted 19 lines

drivers/spi/spi-pxa2xx.c +9 -2

@@ -271,15 +280,34 @@ static void lpss_ssp_setup(struct driver_data *drv_data)
 static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable)
 {
 	const struct lpss_config *config;
-	u32 value;
+	u32 value, cs;
 
 	config = lpss_get_config(drv_data);
 
 	value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
-	if (enable)
+	if (enable) {
+		cs = drv_data->cur_msg->spi->chip_select;
+		cs <<= SPI_CS_CONTROL_CS_SEL_SHIFT;
+		if (cs != (value & SPI_CS_CONTROL_CS_SEL_MASK)) {
+			/*
+			 * When switching another chip select output active
+			 * the output must be selected first and wait 2 ssp_clk
+			 * cycles before changing state to active. Otherwise

drivers/spi/spi-pxa2xx.c static void lpss_ssp_setup(struct driver_data *drv_data) · line 305

Quoted 10 lines

drivers/spi/spi-pxa2xx.c +10 -0

+			 * a short glitch will occur on the previous chip
+			 * select since output select is latched but state
+			 * control is not.
+			 */
+			value &= ~SPI_CS_CONTROL_CS_SEL_MASK;
+			value |= cs;
+			__lpss_ssp_write_priv(drv_data,
+					      config->reg_cs_ctrl, value);
+			ndelay(1000000000 /
+			       (drv_data->master->max_speed_hz / 2));

That ndelay() looks weird, why delay and not sleep ?
And wouldn't that be targeted at another patch ? If I got it right, this patch deals with capabilites, not chip select timings, doesn't it ?

Cheers.

Signature · 5 lines

Robert
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A message that is not in the archive (sent off-list or not yet received): [email protected]

Jarkko Nikula

author

2015-10-26 09:35 UTC #21 lore raw

Re: [PATCH 6/7] spi: pxa2xx: Add support for multiple LPSS chip select signals

Quoted 4 lines · Robert Jarzmik

Quoted 1 line · Jarkko Nikula
LPSS SPI devices in a successor of Intel Sunrisepoint can have up to 4 chip
is ?

Intel Low Power Subsystem SPI host controller(s) after Sunrisepoint can have multiple chip selects. I'll clarify this since patch 7/7 outdates the comment by adding support for two variants.

Quoted 5 lines

Quoted 4 lines

drivers/spi/spi-pxa2xx.c +0 -0

@@ -64,6 +65,10 @@ MODULE_ALIAS("platform:pxa2xx-spi");
  #define GENERAL_REG_RXTO_HOLDOFF_DISABLE	BIT(24)
  #define SPI_CS_CONTROL_SW_MODE			BIT(0)
  #define SPI_CS_CONTROL_CS_HIGH			BIT(1)

Quoted 7 lines

drivers/spi/spi-pxa2xx.c MODULE_ALIAS("platform:pxa2xx-spi"); · line 71
Quoted 4 lines
drivers/spi/spi-pxa2xx.c +4 -0
+#define SPI_CS_CONTROL_CS_SEL_SHIFT		8
+#define SPI_CS_CONTROL_CS_SEL_MASK		(3 << SPI_CS_CONTROL_CS_SEL_SHIFT)
+#define SPI_CAPS_CS_EN_SHIFT			9
+#define SPI_CAPS_CS_EN_MASK			(0xf << SPI_CAPS_CS_EN_SHIFT)
This is intel specific, not pxa oriented, right ?
If so, I'd like to have it namespaced, with LPSS or whatever you see fit.

Good point. I'll check also couple other existing defines as they are LPSS specific.

Quoted 7 lines

drivers/spi/spi-pxa2xx.c static const struct lpss_config lpss_platforms[] = { · line 114
Quoted 5 lines
drivers/spi/spi-pxa2xx.c +1 -0
@@ -103,6 +111,7 @@ static const struct lpss_config lpss_platforms[] = {
  		.reg_general = -1,
  		.reg_ssp = 0x20,
  		.reg_cs_ctrl = 0x24,
+		.reg_capabilities = 0xfc,
Immediate value ? I suppose a defines usage was not possible here ?

I removed register defines for these three registers earlier when code started accessing registers using this configuration data. There are differences in these registers between platforms and it didn't look much clearer to have separate defines for them.

Quoted 24 lines

drivers/spi/spi-pxa2xx.c +14 -2

@@ -271,15 +280,34 @@ static void lpss_ssp_setup(struct driver_data *drv_data)
  static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable)
  {
  	const struct lpss_config *config;
-	u32 value;
+	u32 value, cs;
 
  	config = lpss_get_config(drv_data);
 
  	value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
-	if (enable)
+	if (enable) {
+		cs = drv_data->cur_msg->spi->chip_select;
+		cs <<= SPI_CS_CONTROL_CS_SEL_SHIFT;
+		if (cs != (value & SPI_CS_CONTROL_CS_SEL_MASK)) {
+			/*
+			 * When switching another chip select output active
+			 * the output must be selected first and wait 2 ssp_clk
+			 * cycles before changing state to active. Otherwise
+			 * a short glitch will occur on the previous chip
+			 * select since output select is latched but state
+			 * control is not.
+			 */
+			value &= ~SPI_CS_CONTROL_CS_SEL_MASK;

Quoted 9 lines

drivers/spi/spi-pxa2xx.c static void lpss_ssp_setup(struct driver_data *drv_data) · line 305
Quoted 5 lines
drivers/spi/spi-pxa2xx.c +5 -0
+			value |= cs;
+			__lpss_ssp_write_priv(drv_data,
+					      config->reg_cs_ctrl, value);
+			ndelay(1000000000 /
+			       (drv_data->master->max_speed_hz / 2));
That ndelay() looks weird, why delay and not sleep ?
And wouldn't that be targeted at another patch ? If I got it right, this patch deals with capabilites, not chip select timings, doesn't it ?

Typically we are seeing input clock of SSP being around a few or tens of megahertz so sleep instead of <1 us delay would slow down the transfers needlessly.

That said, we may have a need to change this to use delay or sleep conditionally later. Andy has been looking at changing input clock according to transfer speed which means that needed delay can be up to milliseconds if we use really low transfer speed.

Actually this patch deals with output control and number of chip select detection. Maybe it calls for two patches. Output control prepares for multiple chip selects and detection adds actual support for them.

Signature · 5 lines

Jarkko
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Jarkko Nikula

author

2015-10-22 13:44 UTC #22 lore raw

PATCH 7/7 spi: pxa2xx: Add support for Intel Broxton

In reply to a message not in the archive

LPSS SPI in Intel Broxton is otherwise the same than in Intel Sunrisepoint but it supports up to four chip selects per port and has different FIFO thresholds. Patch adds support for two Broxton SoC variants.

Signed-off-by Jarkko Nikula <jarkko.nikula-VuQAYsv1563Yd54FQh9/[email protected]>

---
 drivers/spi/spi-pxa2xx.c   | 20 ++++++++++++++++++++
 include/linux/pxa2xx_ssp.h |  1 +
 2 files changed, 21 insertions(+)

drivers/spi/spi-pxa2xx.c +20 -0

index 6851649d1b15..b2dfc720772f 100644
@@ -116,6 +116,16 @@ static const struct lpss_config lpss_platforms[] = {
 		.tx_threshold_lo = 32,
 		.tx_threshold_hi = 56,
 	},
+	{	/* LPSS_BXT_SSP */
+		.offset = 0x200,
+		.reg_general = -1,
+		.reg_ssp = 0x20,
+		.reg_cs_ctrl = 0x24,
+		.reg_capabilities = 0xfc,
+		.rx_threshold = 1,
+		.tx_threshold_lo = 16,
+		.tx_threshold_hi = 48,
+	},
 };
 
 static inline const struct lpss_config

@@ -130,6 +140,7 @@ static bool is_lpss_ssp(const struct driver_data *drv_data)
 	case LPSS_LPT_SSP:
 	case LPSS_BYT_SSP:
 	case LPSS_SPT_SSP:
+	case LPSS_BXT_SSP:
 		return true;
 	default:
 		return false;

@@ -1156,6 +1167,7 @@ static int setup(struct spi_device *spi)
 	case LPSS_LPT_SSP:
 	case LPSS_BYT_SSP:
 	case LPSS_SPT_SSP:
+	case LPSS_BXT_SSP:
 		config = lpss_get_config(drv_data);
 		tx_thres = config->tx_threshold_lo;
 		tx_hi_thres = config->tx_threshold_hi;

@@ -1317,6 +1329,14 @@ static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
 	/* SPT-H */
 	{ PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
 	{ PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
+	/* BXT */
+	{ PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP },
+	{ PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP },
+	{ PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP },
+	/* APL */
+	{ PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
+	{ PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
+	{ PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP },
 	{ },
 };

include/linux/pxa2xx_ssp.h +1 -0

index 92273776bce6..c2f2574ff61c 100644
@@ -198,6 +198,7 @@ enum pxa_ssp_type {
 	LPSS_LPT_SSP, /* Keep LPSS types sorted with lpss_platforms[] */
 	LPSS_BYT_SSP,
 	LPSS_SPT_SSP,
+	LPSS_BXT_SSP,
 };
 
 struct ssp_device {

Signature · 6 lines

2.6.1

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A message that is not in the archive (sent off-list or not yet received): 1445521485-2029-7-git-send-email-jarkko.nikula-VuQAYsv1563Yd54FQh9/[email protected]

Mark Brown

2015-10-30 02:20 UTC #24 lore raw

Re: [PATCH 7/7] spi: pxa2xx: Add support for Intel Broxton

The patch

spi: pxa2xx: Add support for Intel Broxton

has been applied to the spi tree at

git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git

If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying to this mail.

Thanks,
Mark

Quoted 1 line

From b7c08cf85c9a3a4b05474b7acacc9fbce8fb3eaf Mon Sep 17 00:00:00 2001

From: Jarkko Nikula <jarkko.nikula-VuQAYsv1563Yd54FQh9/[email protected]>
Date: Wed, 28 Oct 2015 15:13:42 +0200
Subject: [PATCH] spi: pxa2xx: Add support for Intel Broxton

Signed-off-by Jarkko Nikula <jarkko.nikula-VuQAYsv1563Yd54FQh9/[email protected]>

Signed-off-by Mark Brown <[email protected]>

---
 drivers/spi/spi-pxa2xx.c   | 20 ++++++++++++++++++++
 include/linux/pxa2xx_ssp.h |  1 +
 2 files changed, 21 insertions(+)

drivers/spi/spi-pxa2xx.c +20 -0

index a5c2dce..f759c08 100644
@@ -116,6 +116,16 @@ static const struct lpss_config lpss_platforms[] = {
 		.tx_threshold_lo = 32,
 		.tx_threshold_hi = 56,
 	},
+	{	/* LPSS_BXT_SSP */
+		.offset = 0x200,
+		.reg_general = -1,
+		.reg_ssp = 0x20,
+		.reg_cs_ctrl = 0x24,
+		.reg_capabilities = 0xfc,
+		.rx_threshold = 1,
+		.tx_threshold_lo = 16,
+		.tx_threshold_hi = 48,
+	},
 };
 
 static inline const struct lpss_config

@@ -130,6 +140,7 @@ static bool is_lpss_ssp(const struct driver_data *drv_data)
 	case LPSS_LPT_SSP:
 	case LPSS_BYT_SSP:
 	case LPSS_SPT_SSP:
+	case LPSS_BXT_SSP:
 		return true;
 	default:
 		return false;

@@ -1152,6 +1163,7 @@ static int setup(struct spi_device *spi)
 	case LPSS_LPT_SSP:
 	case LPSS_BYT_SSP:
 	case LPSS_SPT_SSP:
+	case LPSS_BXT_SSP:
 		config = lpss_get_config(drv_data);
 		tx_thres = config->tx_threshold_lo;
 		tx_hi_thres = config->tx_threshold_hi;

@@ -1313,6 +1325,14 @@ static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
 	/* SPT-H */
 	{ PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
 	{ PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
+	/* BXT */
+	{ PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP },
+	{ PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP },
+	{ PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP },
+	/* APL */
+	{ PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
+	{ PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
+	{ PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP },
 	{ },
 };

include/linux/pxa2xx_ssp.h +1 -0

index 92273776..c2f2574 100644
@@ -198,6 +198,7 @@ enum pxa_ssp_type {
 	LPSS_LPT_SSP, /* Keep LPSS types sorted with lpss_platforms[] */
 	LPSS_BYT_SSP,
 	LPSS_SPT_SSP,
+	LPSS_BXT_SSP,
 };
 
 struct ssp_device {

Signature · 6 lines

2.6.1

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Mark Brown

2015-10-22 23:57 UTC #25 lore raw

Applied "spi: pxa2xx: move debug messages to pump_transfer()" to the spi tree

In reply to a message not in the archive

The patch

spi: pxa2xx: move debug messages to pump_transfer()

has been applied to the spi tree at

git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git

If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying to this mail.

Thanks,
Mark

Quoted 1 line

From d74c4b1c61ecc5ad8158ac649245fdfc9601c1b5 Mon Sep 17 00:00:00 2001

From: Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/[email protected]>
Date: Thu, 22 Oct 2015 16:44:39 +0300
Subject: [PATCH] spi: pxa2xx: move debug messages to pump_transfer()

Signed-off-by Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/[email protected]>

Signed-off-by Jarkko Nikula <jarkko.nikula-VuQAYsv1563Yd54FQh9/[email protected]>

Signed-off-by Mark Brown <[email protected]>

---
 drivers/spi/spi-pxa2xx.c | 28 +++++++++++-----------------
 1 file changed, 11 insertions(+), 17 deletions(-)

drivers/spi/spi-pxa2xx.c +11 ~~-17~~

index 158967a..986a291 100644
@@ -955,7 +955,18 @@ static void pump_transfers(unsigned long data)
 					     "pump_transfers: DMA burst size reduced to match bits_per_word\n");
 	}
 
+	/* NOTE:  PXA25x_SSP _could_ use external clocking ... */
 	cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
+	if (!pxa25x_ssp_comp(drv_data))
+		dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
+			drv_data->master->max_speed_hz
+				/ (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
+			chip->enable_dma ? "DMA" : "PIO");
+	else
+		dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
+			drv_data->master->max_speed_hz / 2
+				/ (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
+			chip->enable_dma ? "DMA" : "PIO");
 
 	message->state = RUNNING_STATE;

@@ -1099,9 +1110,7 @@ static int setup(struct spi_device *spi)
 	struct chip_data *chip;
 	const struct lpss_config *config;
 	struct driver_data *drv_data = spi_master_get_devdata(spi->master);
-	unsigned int clk_div;
 	uint tx_thres, tx_hi_thres, rx_thres;
-	u32 cr0;
 
 	switch (drv_data->ssp_type) {
 	case QUARK_X1000_SSP:

@@ -1192,8 +1201,6 @@ static int setup(struct spi_device *spi)
 		}
 	}
 
-	clk_div = pxa2xx_ssp_get_clk_div(drv_data, chip, spi->max_speed_hz);
-
 	switch (drv_data->ssp_type) {
 	case QUARK_X1000_SSP:
 		chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)

@@ -1214,19 +1221,6 @@ static int setup(struct spi_device *spi)
 	if (spi->mode & SPI_LOOP)
 		chip->cr1 |= SSCR1_LBM;
 
-	/* NOTE:  PXA25x_SSP _could_ use external clocking ... */
-	cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, spi->bits_per_word);
-	if (!pxa25x_ssp_comp(drv_data))
-		dev_dbg(&spi->dev, "%u Hz actual, %s\n",
-			drv_data->master->max_speed_hz
-				/ (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
-			chip->enable_dma ? "DMA" : "PIO");
-	else
-		dev_dbg(&spi->dev, "%u Hz actual, %s\n",
-			drv_data->master->max_speed_hz / 2
-				/ (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
-			chip->enable_dma ? "DMA" : "PIO");
-
 	if (spi->bits_per_word <= 8) {
 		chip->n_bytes = 1;
 		chip->read = u8_reader;

Signature · 6 lines

2.6.1

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Robert Jarzmik

Acked-by

2015-10-25 11:39 UTC #26 lore raw

In reply to a message not in the archive

Quoted 8 lines · Jarkko Nikula

From: Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/[email protected]>
The speed can be changed from transfer to transfer, that's why the messages do not depict the actual values during ->setup(). Move debug messages from ->setup() to pump_transfers(). Get rid of leftovers as well.
Signed-off-by Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/[email protected]>
Signed-off-by Jarkko Nikula <jarkko.nikula-VuQAYsv1563Yd54FQh9/[email protected]>

Acked-by Robert Jarzmik <[email protected]>

Cheers.

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Robert
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