spi: zynq_[q]spi: Use BIT macro

PATCH Superseded Jagan Teki 3 participants 9 messages Oct 22, 2015

Subsystems (6)

Arm i.MX and Layerscape SPI Arm Samsung Exynos Tegra architecture support +2 more subsystems

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Jagan Teki

author

2015-10-22 17:45 UTC #0 lore raw

PATCH v3 1/4 spi: zynq_[q]spi: Use BIT macro

BIT macro used on zynq_spi.c and zynq_qspi.c

Replace (1 << nr) to BIT(nr) where nr = 0, 1, 2 .... 31

Cc Tom Rini <[email protected]>

Signed-off-by Jagan Teki <[email protected]>

---
Changes for v3, v2:
- none

 drivers/spi/zynq_qspi.c | 20 ++++++++++----------
 drivers/spi/zynq_spi.c  | 16 ++++++++--------
 2 files changed, 18 insertions(+), 18 deletions(-)

drivers/spi/zynq_qspi.c +10 ~~-10~~

index 8aa61d7..dd530a1 100644
@@ -16,20 +16,20 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* zynq qspi register bit masks ZYNQ_QSPI_<REG>_<BIT>_MASK */
-#define ZYNQ_QSPI_CR_IFMODE_MASK	(1 << 31)	/* Flash intrface mode*/
-#define ZYNQ_QSPI_CR_MSA_MASK		(1 << 15)	/* Manual start enb */
-#define ZYNQ_QSPI_CR_MCS_MASK		(1 << 14)	/* Manual chip select */
-#define ZYNQ_QSPI_CR_PCS_MASK		(1 << 10)	/* Peri chip select */
+#define ZYNQ_QSPI_CR_IFMODE_MASK	BIT(31)	/* Flash intrface mode*/
+#define ZYNQ_QSPI_CR_MSA_MASK		BIT(15)	/* Manual start enb */
+#define ZYNQ_QSPI_CR_MCS_MASK		BIT(14)	/* Manual chip select */
+#define ZYNQ_QSPI_CR_PCS_MASK		BIT(10)	/* Peri chip select */
 #define ZYNQ_QSPI_CR_FW_MASK		(0x3 << 6)	/* FIFO width */
 #define ZYNQ_QSPI_CR_SS_MASK		(0xF << 10)	/* Slave Select */
 #define ZYNQ_QSPI_CR_BAUD_MASK		(0x7 << 3)	/* Baud rate div */
-#define ZYNQ_QSPI_CR_CPHA_MASK		(1 << 2)	/* Clock phase */
-#define ZYNQ_QSPI_CR_CPOL_MASK		(1 << 1)	/* Clock polarity */
-#define ZYNQ_QSPI_CR_MSTREN_MASK	(1 << 0)	/* Mode select */
-#define ZYNQ_QSPI_IXR_RXNEMPTY_MASK	(1 << 4)	/* RX_FIFO_not_empty */
-#define ZYNQ_QSPI_IXR_TXOW_MASK		(1 << 2)	/* TX_FIFO_not_full */
+#define ZYNQ_QSPI_CR_CPHA_MASK		BIT(2)	/* Clock phase */
+#define ZYNQ_QSPI_CR_CPOL_MASK		BIT(1)	/* Clock polarity */
+#define ZYNQ_QSPI_CR_MSTREN_MASK	BIT(0)	/* Mode select */
+#define ZYNQ_QSPI_IXR_RXNEMPTY_MASK	BIT(4)	/* RX_FIFO_not_empty */
+#define ZYNQ_QSPI_IXR_TXOW_MASK		BIT(2)	/* TX_FIFO_not_full */
 #define ZYNQ_QSPI_IXR_ALL_MASK		0x7F		/* All IXR bits */
-#define ZYNQ_QSPI_ENR_SPI_EN_MASK	(1 << 0)	/* SPI Enable */
+#define ZYNQ_QSPI_ENR_SPI_EN_MASK	BIT(0)	/* SPI Enable */
 
 /* zynq qspi Transmit Data Register */
 #define ZYNQ_QSPI_TXD_00_00_OFFSET	0x1C	/* Transmit 4-byte inst */

drivers/spi/zynq_spi.c +8 -8

index 65a9633..92e5712 100644
@@ -20,17 +20,17 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */
-#define ZYNQ_SPI_CR_MSA_MASK		(1 << 15)	/* Manual start enb */
-#define ZYNQ_SPI_CR_MCS_MASK		(1 << 14)	/* Manual chip select */
+#define ZYNQ_SPI_CR_MSA_MASK		BIT(15)	/* Manual start enb */
+#define ZYNQ_SPI_CR_MCS_MASK		BIT(14)	/* Manual chip select */
 #define ZYNQ_SPI_CR_CS_MASK		(0xF << 10)	/* Chip select */
 #define ZYNQ_SPI_CR_BAUD_MASK		(0x7 << 3)	/* Baud rate div */
-#define ZYNQ_SPI_CR_CPHA_MASK		(1 << 2)	/* Clock phase */
-#define ZYNQ_SPI_CR_CPOL_MASK		(1 << 1)	/* Clock polarity */
-#define ZYNQ_SPI_CR_MSTREN_MASK		(1 << 0)	/* Mode select */
-#define ZYNQ_SPI_IXR_RXNEMPTY_MASK	(1 << 4)	/* RX_FIFO_not_empty */
-#define ZYNQ_SPI_IXR_TXOW_MASK		(1 << 2)	/* TX_FIFO_not_full */
+#define ZYNQ_SPI_CR_CPHA_MASK		BIT(2)	/* Clock phase */
+#define ZYNQ_SPI_CR_CPOL_MASK		BIT(1)	/* Clock polarity */
+#define ZYNQ_SPI_CR_MSTREN_MASK		BIT(0)	/* Mode select */
+#define ZYNQ_SPI_IXR_RXNEMPTY_MASK	BIT(4)	/* RX_FIFO_not_empty */
+#define ZYNQ_SPI_IXR_TXOW_MASK		BIT(2)	/* TX_FIFO_not_full */
 #define ZYNQ_SPI_IXR_ALL_MASK		0x7F		/* All IXR bits */
-#define ZYNQ_SPI_ENR_SPI_EN_MASK	(1 << 0)	/* SPI Enable */
+#define ZYNQ_SPI_ENR_SPI_EN_MASK	BIT(0)	/* SPI Enable */
 
 #define ZYNQ_SPI_CR_BAUD_MAX		8	/* Baud rate divisor max val */
 #define ZYNQ_SPI_CR_BAUD_SHIFT		3	/* Baud rate divisor shift */

Signature · 1 line

1.9.1

Jagan Teki

author

2015-10-22 17:45 UTC #1 lore raw

PATCH v3 2/4 spi: zynq_[q]spi: Use GENMASK macro

GENMASK macro used on zynq_spi.c and zynq_qspi.c

GENMASK is used to create a contiguous bitmask([hi:lo]).
Ex: (0x7 << 3) => GENMASK(5, 3)

Cc Tom Rini <[email protected]>

Signed-off-by Jagan Teki <[email protected]>

---
Changes for v3, v2:
- none

 drivers/spi/zynq_qspi.c | 8 ++++----
 drivers/spi/zynq_spi.c  | 6 +++---
 2 files changed, 7 insertions(+), 7 deletions(-)

drivers/spi/zynq_qspi.c +4 -4

index dd530a1..64b4eea 100644
@@ -20,15 +20,15 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ZYNQ_QSPI_CR_MSA_MASK		BIT(15)	/* Manual start enb */
 #define ZYNQ_QSPI_CR_MCS_MASK		BIT(14)	/* Manual chip select */
 #define ZYNQ_QSPI_CR_PCS_MASK		BIT(10)	/* Peri chip select */
-#define ZYNQ_QSPI_CR_FW_MASK		(0x3 << 6)	/* FIFO width */
-#define ZYNQ_QSPI_CR_SS_MASK		(0xF << 10)	/* Slave Select */
-#define ZYNQ_QSPI_CR_BAUD_MASK		(0x7 << 3)	/* Baud rate div */
+#define ZYNQ_QSPI_CR_FW_MASK		GENMASK(7, 6)	/* FIFO width */
+#define ZYNQ_QSPI_CR_SS_MASK		GENMASK(13, 10)	/* Slave Select */
+#define ZYNQ_QSPI_CR_BAUD_MASK		GENMASK(5, 3)	/* Baud rate div */
 #define ZYNQ_QSPI_CR_CPHA_MASK		BIT(2)	/* Clock phase */
 #define ZYNQ_QSPI_CR_CPOL_MASK		BIT(1)	/* Clock polarity */
 #define ZYNQ_QSPI_CR_MSTREN_MASK	BIT(0)	/* Mode select */
 #define ZYNQ_QSPI_IXR_RXNEMPTY_MASK	BIT(4)	/* RX_FIFO_not_empty */
 #define ZYNQ_QSPI_IXR_TXOW_MASK		BIT(2)	/* TX_FIFO_not_full */
-#define ZYNQ_QSPI_IXR_ALL_MASK		0x7F		/* All IXR bits */
+#define ZYNQ_QSPI_IXR_ALL_MASK		GENMASK(6, 0)	/* All IXR bits */
 #define ZYNQ_QSPI_ENR_SPI_EN_MASK	BIT(0)	/* SPI Enable */
 
 /* zynq qspi Transmit Data Register */

drivers/spi/zynq_spi.c +3 -3

index 92e5712..9ede099 100644
@@ -22,14 +22,14 @@ DECLARE_GLOBAL_DATA_PTR;
 /* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */
 #define ZYNQ_SPI_CR_MSA_MASK		BIT(15)	/* Manual start enb */
 #define ZYNQ_SPI_CR_MCS_MASK		BIT(14)	/* Manual chip select */
-#define ZYNQ_SPI_CR_CS_MASK		(0xF << 10)	/* Chip select */
-#define ZYNQ_SPI_CR_BAUD_MASK		(0x7 << 3)	/* Baud rate div */
+#define ZYNQ_SPI_CR_CS_MASK		GENMASK(13, 10)	/* Chip select */
+#define ZYNQ_SPI_CR_BAUD_MASK		GENMASK(5, 3)	/* Baud rate div */
 #define ZYNQ_SPI_CR_CPHA_MASK		BIT(2)	/* Clock phase */
 #define ZYNQ_SPI_CR_CPOL_MASK		BIT(1)	/* Clock polarity */
 #define ZYNQ_SPI_CR_MSTREN_MASK		BIT(0)	/* Mode select */
 #define ZYNQ_SPI_IXR_RXNEMPTY_MASK	BIT(4)	/* RX_FIFO_not_empty */
 #define ZYNQ_SPI_IXR_TXOW_MASK		BIT(2)	/* TX_FIFO_not_full */
-#define ZYNQ_SPI_IXR_ALL_MASK		0x7F		/* All IXR bits */
+#define ZYNQ_SPI_IXR_ALL_MASK		GENMASK(6, 0)	/* All IXR bits */
 #define ZYNQ_SPI_ENR_SPI_EN_MASK	BIT(0)	/* SPI Enable */
 
 #define ZYNQ_SPI_CR_BAUD_MAX		8	/* Baud rate divisor max val */

Signature · 1 line

1.9.1

Jagan Teki

author

2015-10-22 17:45 UTC #2 lore raw

PATCH v3 3/4 spi: Use BIT macro in spi/drivers/*

In reply to Jagan Teki

BIT macro used on drivers/spi/*

Replace (1 << nr) to BIT(nr) where nr = 0, 1, 2 .... 31

Cc Tom Rini <[email protected]>

Cc Simon Glass <[email protected]>

Cc Masahiro Yamada <[email protected]>

Cc Peng Fan <[email protected]>

Cc Stefan Roese <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stephen Warren <[email protected]>

Cc Tom Warren <[email protected]>

Signed-off-by Jagan Teki <[email protected]>

---
Changes for v3, v2:
- none

 drivers/spi/altera_spi.c       | 26 ++++++++---------
 drivers/spi/atmel_spi.h        | 52 +++++++++++++++++-----------------
 drivers/spi/bfin_spi6xx.c      |  8 +++---
 drivers/spi/cadence_qspi_apb.c | 28 +++++++++---------
 drivers/spi/designware_spi.c   | 14 ++++-----
 drivers/spi/exynos_spi.c       |  4 +--
 drivers/spi/fsl_dspi.c         |  2 +-
 drivers/spi/fsl_espi.c         | 20 ++++++-------
 drivers/spi/fsl_qspi.c         |  4 +--
 drivers/spi/ich.c              |  4 +--
 drivers/spi/mpc8xxx_spi.c      |  2 +-
 drivers/spi/omap3_spi.h        | 48 +++++++++++++++----------------
 drivers/spi/sh_qspi.c          | 16 +++++------
 drivers/spi/tegra114_spi.c     | 64 +++++++++++++++++++++---------------------
 drivers/spi/tegra20_sflash.c   | 50 ++++++++++++++++-----------------
 drivers/spi/tegra20_slink.c    | 58 +++++++++++++++++++-------------------
 drivers/spi/ti_qspi.c          | 10 +++----
 drivers/spi/xilinx_spi.c       | 32 ++++++++++-----------
 18 files changed, 221 insertions(+), 221 deletions(-)

drivers/spi/altera_spi.c +13 ~~-13~~

index a4d03d9..2302117 100644
@@ -29,19 +29,19 @@ struct altera_spi_regs {
 	u32	slave_sel;
 };
 
-#define ALTERA_SPI_STATUS_ROE_MSK	(1 << 3)
-#define ALTERA_SPI_STATUS_TOE_MSK	(1 << 4)
-#define ALTERA_SPI_STATUS_TMT_MSK	(1 << 5)
-#define ALTERA_SPI_STATUS_TRDY_MSK	(1 << 6)
-#define ALTERA_SPI_STATUS_RRDY_MSK	(1 << 7)
-#define ALTERA_SPI_STATUS_E_MSK		(1 << 8)
-
-#define ALTERA_SPI_CONTROL_IROE_MSK	(1 << 3)
-#define ALTERA_SPI_CONTROL_ITOE_MSK	(1 << 4)
-#define ALTERA_SPI_CONTROL_ITRDY_MSK	(1 << 6)
-#define ALTERA_SPI_CONTROL_IRRDY_MSK	(1 << 7)
-#define ALTERA_SPI_CONTROL_IE_MSK	(1 << 8)
-#define ALTERA_SPI_CONTROL_SSO_MSK	(1 << 10)
+#define ALTERA_SPI_STATUS_ROE_MSK	BIT(3)
+#define ALTERA_SPI_STATUS_TOE_MSK	BIT(4)
+#define ALTERA_SPI_STATUS_TMT_MSK	BIT(5)
+#define ALTERA_SPI_STATUS_TRDY_MSK	BIT(6)
+#define ALTERA_SPI_STATUS_RRDY_MSK	BIT(7)
+#define ALTERA_SPI_STATUS_E_MSK		BIT(8)
+
+#define ALTERA_SPI_CONTROL_IROE_MSK	BIT(3)
+#define ALTERA_SPI_CONTROL_ITOE_MSK	BIT(4)
+#define ALTERA_SPI_CONTROL_ITRDY_MSK	BIT(6)
+#define ALTERA_SPI_CONTROL_IRRDY_MSK	BIT(7)
+#define ALTERA_SPI_CONTROL_IE_MSK	BIT(8)
+#define ALTERA_SPI_CONTROL_SSO_MSK	BIT(10)
 
 static ulong altera_spi_base_list[] = CONFIG_SYS_ALTERA_SPI_LIST;

drivers/spi/atmel_spi.h +26 ~~-26~~

70 lines not on this page · raw message

drivers/spi/bfin_spi6xx.c +4 -4

index eba01d1..8359d76 100644
@@ -63,9 +63,9 @@ void spi_cs_activate(struct spi_slave *slave)
 		ssel = bfin_read32(&bss->regs->ssel);
 		ssel |= 1 << slave->cs;
 		if (bss->cs_pol)
-			ssel |= (1 << 8) << slave->cs;
+			ssel |= BIT(8) << slave->cs;
 		else
-			ssel &= ~((1 << 8) << slave->cs);
+			ssel &= ~(BIT(8) << slave->cs);
 		bfin_write32(&bss->regs->ssel, ssel);
 	}

@@ -83,9 +83,9 @@ void spi_cs_deactivate(struct spi_slave *slave)
 		u32 ssel;
 		ssel = bfin_read32(&bss->regs->ssel);
 		if (bss->cs_pol)
-			ssel &= ~((1 << 8) << slave->cs);
+			ssel &= ~(BIT(8) << slave->cs);
 		else
-			ssel |= (1 << 8) << slave->cs;
+			ssel |= BIT(8) << slave->cs;
 		/* deassert cs */
 		bfin_write32(&bss->regs->ssel, ssel);
 		SSYNC();

drivers/spi/cadence_qspi_apb.c +14 ~~-14~~

index d053407..7786dd6 100644
@@ -58,10 +58,10 @@
 #define	CQSPI_REG_CONFIG			0x00
 #define	CQSPI_REG_CONFIG_CLK_POL_LSB		1
 #define	CQSPI_REG_CONFIG_CLK_PHA_LSB		2
-#define	CQSPI_REG_CONFIG_ENABLE_MASK		(1 << 0)
-#define	CQSPI_REG_CONFIG_DIRECT_MASK		(1 << 7)
-#define	CQSPI_REG_CONFIG_DECODE_MASK		(1 << 9)
-#define	CQSPI_REG_CONFIG_XIP_IMM_MASK		(1 << 18)
+#define	CQSPI_REG_CONFIG_ENABLE_MASK		BIT(0)
+#define	CQSPI_REG_CONFIG_DIRECT_MASK		BIT(7)
+#define	CQSPI_REG_CONFIG_DECODE_MASK		BIT(9)
+#define	CQSPI_REG_CONFIG_XIP_IMM_MASK		BIT(18)
 #define	CQSPI_REG_CONFIG_CHIPSELECT_LSB		10
 #define	CQSPI_REG_CONFIG_BAUD_LSB		19
 #define	CQSPI_REG_CONFIG_IDLE_LSB		31

@@ -122,18 +122,18 @@
 #define	CQSPI_REG_IRQMASK			0x44
 
 #define	CQSPI_REG_INDIRECTRD			0x60
-#define	CQSPI_REG_INDIRECTRD_START_MASK		(1 << 0)
-#define	CQSPI_REG_INDIRECTRD_CANCEL_MASK	(1 << 1)
-#define	CQSPI_REG_INDIRECTRD_INPROGRESS_MASK	(1 << 2)
-#define	CQSPI_REG_INDIRECTRD_DONE_MASK		(1 << 5)
+#define	CQSPI_REG_INDIRECTRD_START_MASK		BIT(0)
+#define	CQSPI_REG_INDIRECTRD_CANCEL_MASK	BIT(1)
+#define	CQSPI_REG_INDIRECTRD_INPROGRESS_MASK	BIT(2)
+#define	CQSPI_REG_INDIRECTRD_DONE_MASK		BIT(5)
 
 #define	CQSPI_REG_INDIRECTRDWATERMARK		0x64
 #define	CQSPI_REG_INDIRECTRDSTARTADDR		0x68
 #define	CQSPI_REG_INDIRECTRDBYTES		0x6C
 
 #define	CQSPI_REG_CMDCTRL			0x90
-#define	CQSPI_REG_CMDCTRL_EXECUTE_MASK		(1 << 0)
-#define	CQSPI_REG_CMDCTRL_INPROGRESS_MASK	(1 << 1)
+#define	CQSPI_REG_CMDCTRL_EXECUTE_MASK		BIT(0)
+#define	CQSPI_REG_CMDCTRL_INPROGRESS_MASK	BIT(1)
 #define	CQSPI_REG_CMDCTRL_DUMMY_LSB		7
 #define	CQSPI_REG_CMDCTRL_WR_BYTES_LSB		12
 #define	CQSPI_REG_CMDCTRL_WR_EN_LSB		15

@@ -149,10 +149,10 @@
 #define	CQSPI_REG_CMDCTRL_OPCODE_MASK		0xFF
 
 #define	CQSPI_REG_INDIRECTWR			0x70
-#define	CQSPI_REG_INDIRECTWR_START_MASK		(1 << 0)
-#define	CQSPI_REG_INDIRECTWR_CANCEL_MASK	(1 << 1)
-#define	CQSPI_REG_INDIRECTWR_INPROGRESS_MASK	(1 << 2)
-#define	CQSPI_REG_INDIRECTWR_DONE_MASK		(1 << 5)
+#define	CQSPI_REG_INDIRECTWR_START_MASK		BIT(0)
+#define	CQSPI_REG_INDIRECTWR_CANCEL_MASK	BIT(1)
+#define	CQSPI_REG_INDIRECTWR_INPROGRESS_MASK	BIT(2)
+#define	CQSPI_REG_INDIRECTWR_DONE_MASK		BIT(5)
 
 #define	CQSPI_REG_INDIRECTWRWATERMARK		0x74
 #define	CQSPI_REG_INDIRECTWRSTARTADDR		0x78

drivers/spi/designware_spi.c +7 -7

index 86ee90f..7885e46 100644
@@ -75,13 +75,13 @@ DECLARE_GLOBAL_DATA_PTR;
 
 /* Bit fields in SR, 7 bits */
 #define SR_MASK				0x7f		/* cover 7 bits */
-#define SR_BUSY				(1 << 0)
-#define SR_TF_NOT_FULL			(1 << 1)
-#define SR_TF_EMPT			(1 << 2)
-#define SR_RF_NOT_EMPT			(1 << 3)
-#define SR_RF_FULL			(1 << 4)
-#define SR_TX_ERR			(1 << 5)
-#define SR_DCOL				(1 << 6)
+#define SR_BUSY				BIT(0)
+#define SR_TF_NOT_FULL			BIT(1)
+#define SR_TF_EMPT			BIT(2)
+#define SR_RF_NOT_EMPT			BIT(3)
+#define SR_RF_FULL			BIT(4)
+#define SR_TX_ERR			BIT(5)
+#define SR_DCOL				BIT(6)
 
 #define RX_TIMEOUT			1000		/* timeout in ms */

drivers/spi/exynos_spi.c +2 -2

index 44948c3..ea3c51d 100644
@@ -86,7 +86,7 @@ static void spi_request_bytes(struct exynos_spi *regs, int count, int step)
 		writel(0, &regs->swap_cfg);
 	}
 
-	assert(count && count < (1 << 16));
+	assert(count && count < BIT(16));
 	setbits_le32(&regs->ch_cfg, SPI_CH_RST);
 	clrbits_le32(&regs->ch_cfg, SPI_CH_RST);

@@ -345,7 +345,7 @@ static int exynos_spi_xfer(struct udevice *dev, unsigned int bitlen,
 	 */
 	bytelen = bitlen / 8;
 	for (upto = 0; !ret && upto < bytelen; upto += todo) {
-		todo = min(bytelen - upto, (1 << 16) - 4);
+		todo = min(bytelen - upto, BIT(16) - 4);
 		ret = spi_rx_tx(priv, todo, &din, &dout, flags);
 		if (ret)
 			break;

drivers/spi/fsl_dspi.c +1 -1

index 887edd8..c8dcb27 100644
@@ -24,7 +24,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* fsl_dspi_platdata flags */
-#define DSPI_FLAG_REGMAP_ENDIAN_BIG	(1 << 0)
+#define DSPI_FLAG_REGMAP_ENDIAN_BIG	BIT(0)
 
 /* idle data value */
 #define DSPI_IDLE_VAL			0x0

drivers/spi/fsl_espi.c +10 ~~-10~~

index 375dc07..b1586d1 100644
@@ -32,26 +32,26 @@ struct fsl_spi_slave {
 #define ESPI_MAX_CS_NUM		4
 #define ESPI_FIFO_WIDTH_BIT	32
 
-#define ESPI_EV_RNE		(1 << 9)
-#define ESPI_EV_TNF		(1 << 8)
-#define ESPI_EV_DON		(1 << 14)
-#define ESPI_EV_TXE		(1 << 15)
+#define ESPI_EV_RNE		BIT(9)
+#define ESPI_EV_TNF		BIT(8)
+#define ESPI_EV_DON		BIT(14)
+#define ESPI_EV_TXE		BIT(15)
 #define ESPI_EV_RFCNT_SHIFT	24
 #define ESPI_EV_RFCNT_MASK	(0x3f << ESPI_EV_RFCNT_SHIFT)
 
-#define ESPI_MODE_EN		(1 << 31)	/* Enable interface */
+#define ESPI_MODE_EN		BIT(31)	/* Enable interface */
 #define ESPI_MODE_TXTHR(x)	((x) << 8)	/* Tx FIFO threshold */
 #define ESPI_MODE_RXTHR(x)	((x) << 0)	/* Rx FIFO threshold */
 
 #define ESPI_COM_CS(x)		((x) << 30)
 #define ESPI_COM_TRANLEN(x)	((x) << 0)
 
-#define ESPI_CSMODE_CI_INACTIVEHIGH	(1 << 31)
-#define ESPI_CSMODE_CP_BEGIN_EDGCLK	(1 << 30)
-#define ESPI_CSMODE_REV_MSB_FIRST	(1 << 29)
-#define ESPI_CSMODE_DIV16		(1 << 28)
+#define ESPI_CSMODE_CI_INACTIVEHIGH	BIT(31)
+#define ESPI_CSMODE_CP_BEGIN_EDGCLK	BIT(30)
+#define ESPI_CSMODE_REV_MSB_FIRST	BIT(29)
+#define ESPI_CSMODE_DIV16		BIT(28)
 #define ESPI_CSMODE_PM(x)		((x) << 24)
-#define ESPI_CSMODE_POL_ASSERTED_LOW	(1 << 20)
+#define ESPI_CSMODE_POL_ASSERTED_LOW	BIT(20)
 #define ESPI_CSMODE_LEN(x)		((x) << 16)
 #define ESPI_CSMODE_CSBEF(x)		((x) << 12)
 #define ESPI_CSMODE_CSAFT(x)		((x) << 8)

drivers/spi/fsl_qspi.c +2 -2

index 868df5f..e1a0ec9 100644
@@ -68,7 +68,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define QSPI_CMD_SE_4B		0xdc    /* Sector erase (usually 64KiB) */
 
 /* fsl_qspi_platdata flags */
-#define QSPI_FLAG_REGMAP_ENDIAN_BIG	(1 << 0)
+#define QSPI_FLAG_REGMAP_ENDIAN_BIG	BIT(0)
 
 /* default SCK frequency, unit: HZ */
 #define FSL_QSPI_DEFAULT_SCK_FREQ	50000000

@@ -383,7 +383,7 @@ static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv)
 	/* Enable the module again (enable the DDR too) */
 	reg |= QSPI_MCR_DDR_EN_MASK;
 	/* Enable bit 29 for imx6sx */
-	reg |= (1 << 29);
+	reg |= BIT(29);
 
 	qspi_write32(priv->flags, &regs->mcr, reg);
 }

drivers/spi/ich.c +2 -2

index be4c0a3..af327c4 100644
@@ -692,13 +692,13 @@ static int ich_spi_probe(struct udevice *bus)
 	 */
 	if (plat->use_sbase) {
 		bios_cntl = ich_readb(priv, priv->bcr);
-		bios_cntl &= ~(1 << 5);	/* clear Enable InSMM_STS (EISS) */
+		bios_cntl &= ~BIT(5);	/* clear Enable InSMM_STS (EISS) */
 		bios_cntl |= 1;		/* Write Protect Disable (WPD) */
 		ich_writeb(priv, bios_cntl, priv->bcr);
 	} else {
 		pci_read_config_byte(plat->dev, 0xdc, &bios_cntl);
 		if (plat->ich_version == 9)
-			bios_cntl &= ~(1 << 5);
+			bios_cntl &= ~BIT(5);
 		pci_write_config_byte(plat->dev, 0xdc, bios_cntl | 0x1);
 	}

drivers/spi/mpc8xxx_spi.c +1 -1

index 0d59c36..00cbcbf 100644
@@ -55,7 +55,7 @@ void spi_init(void)
 	 * some registers
 	 */
 	spi->mode = SPI_MODE_REV | SPI_MODE_MS | SPI_MODE_EN;
-	spi->mode = (spi->mode & 0xfff0ffff) | (1 << 16); /* Use SYSCLK / 8
+	spi->mode = (spi->mode & 0xfff0ffff) | BIT(16); /* Use SYSCLK / 8
 							     (16.67MHz typ.) */
 	spi->event = 0xffffffff;	/* Clear all SPI events */
 	spi->mask = 0x00000000;	/* Mask  all SPI interrupts */

drivers/spi/omap3_spi.h +24 ~~-24~~

64 lines not on this page · raw message

drivers/spi/sh_qspi.c +8 -8

index 77ede6b..7209e1d 100644
@@ -21,19 +21,19 @@
 #define SPPCR_IO3FV	0x04
 #define SPPCR_IO2FV	0x02
 #define SPPCR_IO1FV	0x01
-#define SPBDCR_RXBC0	(1 << 0)
-#define SPCMD_SCKDEN	(1 << 15)
-#define SPCMD_SLNDEN	(1 << 14)
-#define SPCMD_SPNDEN	(1 << 13)
-#define SPCMD_SSLKP	(1 << 7)
-#define SPCMD_BRDV0	(1 << 2)
+#define SPBDCR_RXBC0	BIT(0)
+#define SPCMD_SCKDEN	BIT(15)
+#define SPCMD_SLNDEN	BIT(14)
+#define SPCMD_SPNDEN	BIT(13)
+#define SPCMD_SSLKP	BIT(7)
+#define SPCMD_BRDV0	BIT(2)
 #define SPCMD_INIT1	SPCMD_SCKDEN | SPCMD_SLNDEN | \
 			SPCMD_SPNDEN | SPCMD_SSLKP | \
 			SPCMD_BRDV0
 #define SPCMD_INIT2	SPCMD_SPNDEN | SPCMD_SSLKP | \
 			SPCMD_BRDV0
-#define SPBFCR_TXRST	(1 << 7)
-#define SPBFCR_RXRST	(1 << 6)
+#define SPBFCR_TXRST	BIT(7)
+#define SPBFCR_RXRST	BIT(6)
 
 /* SH QSPI register set */
 struct sh_qspi_regs {

drivers/spi/tegra114_spi.c +32 ~~-32~~

86 lines not on this page · raw message

drivers/spi/tegra20_sflash.c +25 ~~-25~~

62 lines not on this page · raw message

drivers/spi/tegra20_slink.c +29 ~~-29~~

74 lines not on this page · raw message

drivers/spi/ti_qspi.c +5 -5

index bd63db8..ecd9d78 100644
@@ -20,13 +20,13 @@
 #define QSPI_TIMEOUT                    2000000
 #define QSPI_FCLK                       192000000
 /* clock control */
-#define QSPI_CLK_EN                     (1 << 31)
+#define QSPI_CLK_EN                     BIT(31)
 #define QSPI_CLK_DIV_MAX                0xffff
 /* command */
 #define QSPI_EN_CS(n)                   (n << 28)
 #define QSPI_WLEN(n)                    ((n-1) << 19)
-#define QSPI_3_PIN                      (1 << 18)
-#define QSPI_RD_SNGL                    (1 << 16)
+#define QSPI_3_PIN                      BIT(18)
+#define QSPI_RD_SNGL                    BIT(16)
 #define QSPI_WR_SNGL                    (2 << 16)
 #define QSPI_INVAL                      (4 << 16)
 #define QSPI_RD_QUAD                    (7 << 16)

@@ -36,8 +36,8 @@
 #define QSPI_CSPOL(n)                   (1 << (1 + n*8))
 #define QSPI_CKPOL(n)                   (1 << (n*8))
 /* status */
-#define QSPI_WC                         (1 << 1)
-#define QSPI_BUSY                       (1 << 0)
+#define QSPI_WC                         BIT(1)
+#define QSPI_BUSY                       BIT(0)
 #define QSPI_WC_BUSY                    (QSPI_WC | QSPI_BUSY)
 #define QSPI_XFER_DONE                  QSPI_WC
 #define MM_SWITCH                       0x01

drivers/spi/xilinx_spi.c +16 ~~-16~~

index 8ccc578..7620163 100644
@@ -32,24 +32,24 @@
  */
 
 /* SPI Control Register (spicr), [1] p9, [2] p8 */
-#define SPICR_LSB_FIRST		(1 << 9)
-#define SPICR_MASTER_INHIBIT	(1 << 8)
-#define SPICR_MANUAL_SS		(1 << 7)
-#define SPICR_RXFIFO_RESEST	(1 << 6)
-#define SPICR_TXFIFO_RESEST	(1 << 5)
-#define SPICR_CPHA		(1 << 4)
-#define SPICR_CPOL		(1 << 3)
-#define SPICR_MASTER_MODE	(1 << 2)
-#define SPICR_SPE		(1 << 1)
-#define SPICR_LOOP		(1 << 0)
+#define SPICR_LSB_FIRST		BIT(9)
+#define SPICR_MASTER_INHIBIT	BIT(8)
+#define SPICR_MANUAL_SS		BIT(7)
+#define SPICR_RXFIFO_RESEST	BIT(6)
+#define SPICR_TXFIFO_RESEST	BIT(5)
+#define SPICR_CPHA		BIT(4)
+#define SPICR_CPOL		BIT(3)
+#define SPICR_MASTER_MODE	BIT(2)
+#define SPICR_SPE		BIT(1)
+#define SPICR_LOOP		BIT(0)
 
 /* SPI Status Register (spisr), [1] p11, [2] p10 */
-#define SPISR_SLAVE_MODE_SELECT	(1 << 5)
-#define SPISR_MODF		(1 << 4)
-#define SPISR_TX_FULL		(1 << 3)
-#define SPISR_TX_EMPTY		(1 << 2)
-#define SPISR_RX_FULL		(1 << 1)
-#define SPISR_RX_EMPTY		(1 << 0)
+#define SPISR_SLAVE_MODE_SELECT	BIT(5)
+#define SPISR_MODF		BIT(4)
+#define SPISR_TX_FULL		BIT(3)
+#define SPISR_TX_EMPTY		BIT(2)
+#define SPISR_RX_FULL		BIT(1)
+#define SPISR_RX_EMPTY		BIT(0)
 
 /* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */
 #define SPIDTR_8BIT_MASK	(0xff << 0)

Signature · 1 line

1.9.1

Marek Vasut

2015-10-22 18:15 UTC #3 lore raw

PATCH v3 3/4 spi: Use BIT macro in spi/drivers/*

Quoted 4 lines · Jagan Teki

BIT macro used on drivers/spi/*
Replace (1 << nr) to BIT(nr) where nr = 0, 1, 2 .... 31

Quoted 9 lines

Cc Tom Rini <[email protected]>
Cc Simon Glass <[email protected]>
Cc Masahiro Yamada <[email protected]>
Cc Peng Fan <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Stephen Warren <[email protected]>
Cc Tom Warren <[email protected]>
Signed-off-by Jagan Teki <[email protected]>

So, you're sending this horrid blob of changes instead of splitting them into more managable parts, sigh. Moreover, I have a feeling this is a change for the sake of changing something, not great. Also, you did not describe how you performed this change -- was it done using some sort of sed script or by hand ?

Best regards,
Marek Vasut

Jagan Teki

2015-10-22 18:21 UTC #4 lore raw

PATCH v3 3/4 spi: Use BIT macro in spi/drivers/*

Quoted 15 lines · Marek Vasut

Quoted 4 lines · Jagan Teki
BIT macro used on drivers/spi/*
Replace (1 << nr) to BIT(nr) where nr = 0, 1, 2 .... 31
Quoted 9 lines
Cc Tom Rini <[email protected]>
Cc Simon Glass <[email protected]>
Cc Masahiro Yamada <[email protected]>
Cc Peng Fan <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Stephen Warren <[email protected]>
Cc Tom Warren <[email protected]>
Signed-off-by Jagan Teki <[email protected]>

Quoted 5 lines

So, you're sending this horrid blob of changes instead of splitting them into more managable parts, sigh. Moreover, I have a feeling this is a change for the sake of changing something, not great. Also, you did not describe how you performed this change -- was it done using some sort of sed script or by hand ?

Yes this is performed using sed and as this a common change I have combined all spi drivers as I belongs to - did you see any wrong on this?

Signature · 1 line

Jagan.

Marek Vasut

2015-10-22 19:05 UTC #5 lore raw

PATCH v3 3/4 spi: Use BIT macro in spi/drivers/*

Quoted 16 lines · Jagan Teki

Quoted 15 lines · Marek Vasut
Quoted 13 lines · Jagan Teki
BIT macro used on drivers/spi/*
Replace (1 << nr) to BIT(nr) where nr = 0, 1, 2 .... 31
Cc Tom Rini <[email protected]>
Cc Simon Glass <[email protected]>
Cc Masahiro Yamada <[email protected]>
Cc Peng Fan <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Stephen Warren <[email protected]>
Cc Tom Warren <[email protected]>
Signed-off-by Jagan Teki <[email protected]>

Quoted 7 lines

Quoted 5 lines
So, you're sending this horrid blob of changes instead of splitting them into more managable parts, sigh. Moreover, I have a feeling this is a change for the sake of changing something, not great. Also, you did not describe how you performed this change -- was it done using some sort of sed script or by hand ?
Yes this is performed using sed

The script you used should be explained somewhere.

Quoted 3 lines

and as this a common change I have
combined all spi drivers as I belongs to - did you see any wrong on this?

It's hard to review such a big blob, furthermore if you need to adjust some driver, you'd have to repost this whole thing instead of a single patch.

Best regards,
Marek Vasut

Jagan Teki

author

2015-10-22 19:09 UTC #6 lore raw

PATCH v3 3/4 spi: Use BIT macro in spi/drivers/*

Quoted 23 lines · Marek Vasut

Quoted 22 lines · Jagan Teki
Quoted 20 lines · Marek Vasut
Quoted 4 lines · Jagan Teki
BIT macro used on drivers/spi/*
Replace (1 << nr) to BIT(nr) where nr = 0, 1, 2 .... 31
Quoted 9 lines
Cc Tom Rini <[email protected]>
Cc Simon Glass <[email protected]>
Cc Masahiro Yamada <[email protected]>
Cc Peng Fan <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Stephen Warren <[email protected]>
Cc Tom Warren <[email protected]>
Signed-off-by Jagan Teki <[email protected]>
So, you're sending this horrid blob of changes instead of splitting them into more managable parts, sigh. Moreover, I have a feeling this is a change for the sake of changing something, not great. Also, you did not describe how you performed this change -- was it done using some sort of sed script or by hand ?

Quoted 3 lines

Quoted 1 line
Yes this is performed using sed
The script you used should be explained somewhere.

OK, add in next version patches.

Quoted 7 lines

Quoted 4 lines
and as this a common change I have
combined all spi drivers as I belongs to - did you see any wrong on this?
It's hard to review such a big blob, furthermore if you need to adjust some driver, you'd have to repost this whole thing instead of a single patch.

OK, then I will resend it separate patches, for individual drivers.

Signature · 1 line

Jagan | openedev.

Marek Vasut

2015-10-22 20:14 UTC #7 lore raw

PATCH v3 3/4 spi: Use BIT macro in spi/drivers/*

Quoted 34 lines · Jagan Teki

Quoted 23 lines · Marek Vasut
Quoted 22 lines · Jagan Teki
Quoted 20 lines · Marek Vasut
Quoted 4 lines · Jagan Teki
BIT macro used on drivers/spi/*
Replace (1 << nr) to BIT(nr) where nr = 0, 1, 2 .... 31
Quoted 9 lines
Cc Tom Rini <[email protected]>
Cc Simon Glass <[email protected]>
Cc Masahiro Yamada <[email protected]>
Cc Peng Fan <[email protected]>
Cc Stefan Roese <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Stephen Warren <[email protected]>
Cc Tom Warren <[email protected]>
Signed-off-by Jagan Teki <[email protected]>
So, you're sending this horrid blob of changes instead of splitting them into more managable parts, sigh. Moreover, I have a feeling this is a change for the sake of changing something, not great. Also, you did not describe how you performed this change -- was it done using some sort of sed script or by hand ?
Quoted 3 lines
Quoted 1 line
Yes this is performed using sed
The script you used should be explained somewhere.
OK, add in next version patches.
Quoted 4 lines
Quoted 3 lines
and as this a common change I have
combined all spi drivers as I belongs to - did you see any wrong on this?

Quoted 5 lines

Quoted 3 lines
It's hard to review such a big blob, furthermore if you need to adjust some driver, you'd have to repost this whole thing instead of a single patch.
OK, then I will resend it separate patches, for individual drivers.

Also, please fix your mailer, you are constantly CCing Masahiro's old email address for some reason. It's really annoying.

Best regards,
Marek Vasut

Jagan Teki

author

2015-10-22 17:45 UTC #8 lore raw

PATCH v3 4/4 spi: Use GENMASK instead of numeric hexcodes

In reply to Jagan Teki

Updated numeric hexcodes with GENMASK macro in spi drivers.

Cc Tom Rini <[email protected]>

Cc Simon Glass <[email protected]>

Cc Masahiro Yamada <[email protected]>

Cc Peng Fan <[email protected]>

Cc Stefan Roese <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stephen Warren <[email protected]>

Cc Tom Warren <[email protected]>

Signed-off-by Jagan Teki <[email protected]>

---
Changes for v3, v2:
- none

 drivers/spi/atmel_spi.h        |  2 +-
 drivers/spi/cadence_qspi_apb.c | 48 +++++++++++++++++++++---------------------
 drivers/spi/designware_spi.c   |  2 +-
 drivers/spi/fsl_qspi.c         |  2 +-
 drivers/spi/mxs_spi.c          |  2 +-
 drivers/spi/omap3_spi.h        | 10 ++++-----
 drivers/spi/tegra114_spi.c     | 12 +++++------
 drivers/spi/tegra20_sflash.c   |  2 +-
 drivers/spi/tegra20_slink.c    |  4 ++--
 drivers/spi/xilinx_spi.c       | 14 ++++++------
 10 files changed, 49 insertions(+), 49 deletions(-)

drivers/spi/atmel_spi.h +1 -1

index 5b892d2..76b8556 100644
@@ -59,7 +59,7 @@
 #define ATMEL_SPI_CSRx_CSAAT		BIT(3)
 #define ATMEL_SPI_CSRx_BITS(x)		((x) << 4)
 #define ATMEL_SPI_CSRx_SCBR(x)		((x) << 8)
-#define ATMEL_SPI_CSRx_SCBR_MAX		0xff
+#define ATMEL_SPI_CSRx_SCBR_MAX		GENMASK(7, 0)
 #define ATMEL_SPI_CSRx_DLYBS(x)		((x) << 16)
 #define ATMEL_SPI_CSRx_DLYBCT(x)	((x) << 24)

drivers/spi/cadence_qspi_apb.c +24 ~~-24~~

105 lines not on this page · raw message

drivers/spi/designware_spi.c +1 -1

index 7885e46..24a6e98 100644
@@ -74,7 +74,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SPI_CFS_OFFSET			12
 
 /* Bit fields in SR, 7 bits */
-#define SR_MASK				0x7f		/* cover 7 bits */
+#define SR_MASK				GENMASK(6, 0)	/* cover 7 bits */
 #define SR_BUSY				BIT(0)
 #define SR_TF_NOT_FULL			BIT(1)
 #define SR_TF_EMPT			BIT(2)

drivers/spi/fsl_qspi.c +1 -1

index e1a0ec9..10733df 100644
@@ -24,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define TX_BUFFER_SIZE		0x40
 #endif
 
-#define OFFSET_BITS_MASK	0x00ffffff
+#define OFFSET_BITS_MASK	GENMASK(24, 0)
 
 #define FLASH_STATUS_WEL	0x02

drivers/spi/mxs_spi.c +1 -1

index 627644b..459c603 100644
@@ -23,7 +23,7 @@
 
 #define	MXS_SPI_MAX_TIMEOUT	1000000
 #define	MXS_SPI_PORT_OFFSET	0x2000
-#define MXS_SSP_CHIPSELECT_MASK		0x00300000
+#define MXS_SSP_CHIPSELECT_MASK		GENMASK(21, 20)
 #define MXS_SSP_CHIPSELECT_SHIFT	20
 
 #define MXSSSP_SMALL_TRANSFER	512

drivers/spi/omap3_spi.h +5 -5

index fb02ea1..6a07c6d 100644
@@ -64,12 +64,12 @@ struct mcspi {
 
 #define OMAP3_MCSPI_CHCONF_PHA		BIT(0)
 #define OMAP3_MCSPI_CHCONF_POL		BIT(1)
-#define OMAP3_MCSPI_CHCONF_CLKD_MASK	(0x0f << 2)
+#define OMAP3_MCSPI_CHCONF_CLKD_MASK	GENMASK(5, 2)
 #define OMAP3_MCSPI_CHCONF_EPOL		BIT(6)
-#define OMAP3_MCSPI_CHCONF_WL_MASK	(0x1f << 7)
-#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY	(0x01 << 12)
-#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY	(0x02 << 12)
-#define OMAP3_MCSPI_CHCONF_TRM_MASK	(0x03 << 12)
+#define OMAP3_MCSPI_CHCONF_WL_MASK	GENMASK(11, 7)
+#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY	BIT(12)
+#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY	BIT(13)
+#define OMAP3_MCSPI_CHCONF_TRM_MASK	GENMASK(13, 12)
 #define OMAP3_MCSPI_CHCONF_DMAW		BIT(14)
 #define OMAP3_MCSPI_CHCONF_DMAR		BIT(15)
 #define OMAP3_MCSPI_CHCONF_DPE0		BIT(16)

drivers/spi/tegra114_spi.c +6 -6

index d9edd11..98a062c 100644
@@ -35,9 +35,9 @@ DECLARE_GLOBAL_DATA_PTR;
 /* COMMAND1 */
 #define SPI_CMD1_GO			BIT(31)
 #define SPI_CMD1_M_S			BIT(30)
-#define SPI_CMD1_MODE_MASK		0x3
+#define SPI_CMD1_MODE_MASK		GENMASK(1, 0)
 #define SPI_CMD1_MODE_SHIFT		28
-#define SPI_CMD1_CS_SEL_MASK		0x3
+#define SPI_CMD1_CS_SEL_MASK		GENMASK(1, 0)
 #define SPI_CMD1_CS_SEL_SHIFT		26
 #define SPI_CMD1_CS_POL_INACTIVE3	BIT(25)
 #define SPI_CMD1_CS_POL_INACTIVE2	BIT(24)

@@ -45,7 +45,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SPI_CMD1_CS_POL_INACTIVE0	BIT(22)
 #define SPI_CMD1_CS_SW_HW		BIT(21)
 #define SPI_CMD1_CS_SW_VAL		BIT(20)
-#define SPI_CMD1_IDLE_SDA_MASK		0x3
+#define SPI_CMD1_IDLE_SDA_MASK		GENMASK(1, 0)
 #define SPI_CMD1_IDLE_SDA_SHIFT		18
 #define SPI_CMD1_BIDIR			BIT(17)
 #define SPI_CMD1_LSBI_FE		BIT(16)

@@ -55,14 +55,14 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SPI_CMD1_RX_EN			BIT(12)
 #define SPI_CMD1_TX_EN			BIT(11)
 #define SPI_CMD1_PACKED			BIT(5)
-#define SPI_CMD1_BIT_LEN_MASK		0x1F
+#define SPI_CMD1_BIT_LEN_MASK		GENMASK(4, 0)
 #define SPI_CMD1_BIT_LEN_SHIFT		0
 
 /* COMMAND2 */
 #define SPI_CMD2_TX_CLK_TAP_DELAY	BIT(6)
-#define SPI_CMD2_TX_CLK_TAP_DELAY_MASK	(0x3F << 6)
+#define SPI_CMD2_TX_CLK_TAP_DELAY_MASK	GENMASK(11, 6)
 #define SPI_CMD2_RX_CLK_TAP_DELAY	BIT(0)
-#define SPI_CMD2_RX_CLK_TAP_DELAY_MASK	(0x3F << 0)
+#define SPI_CMD2_RX_CLK_TAP_DELAY_MASK	GENMASK(5, 0)
 
 /* TRANSFER STATUS */
 #define SPI_XFER_STS_RDY		BIT(30)

drivers/spi/tegra20_sflash.c +1 -1

index 5dc196b..6888a96 100644
@@ -37,7 +37,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SPI_CMD_CS1_EN			BIT(6)
 #define SPI_CMD_CS0_EN			BIT(5)
 #define SPI_CMD_BIT_LENGTH		BIT(4)
-#define SPI_CMD_BIT_LENGTH_MASK		0x0000001F
+#define SPI_CMD_BIT_LENGTH_MASK		GENMASK(4, 0)
 
 #define SPI_STAT_BSY			BIT(31)
 #define SPI_STAT_RDY			BIT(30)

drivers/spi/tegra20_slink.c +2 -2

index d1abac2..43054f1 100644
@@ -46,13 +46,13 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SLINK_CMD_CS_VAL		BIT(12)
 #define SLINK_CMD_CS_SOFT		BIT(11)
 #define SLINK_CMD_BIT_LENGTH		BIT(4)
-#define SLINK_CMD_BIT_LENGTH_MASK	0x0000001F
+#define SLINK_CMD_BIT_LENGTH_MASK	GENMASK(4, 0)
 /* COMMAND2 */
 #define SLINK_CMD2_TXEN			BIT(30)
 #define SLINK_CMD2_RXEN			BIT(31)
 #define SLINK_CMD2_SS_EN		BIT(18)
 #define SLINK_CMD2_SS_EN_SHIFT		18
-#define SLINK_CMD2_SS_EN_MASK		0x000C0000
+#define SLINK_CMD2_SS_EN_MASK		GENMASK(19, 18)
 #define SLINK_CMD2_CS_ACTIVE_BETWEEN	BIT(17)
 /* STATUS */
 #define SLINK_STAT_BSY			BIT(31)

drivers/spi/xilinx_spi.c +7 -7

index 7620163..0713714 100644
@@ -52,14 +52,14 @@
 #define SPISR_RX_EMPTY		BIT(0)
 
 /* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */
-#define SPIDTR_8BIT_MASK	(0xff << 0)
-#define SPIDTR_16BIT_MASK	(0xffff << 0)
-#define SPIDTR_32BIT_MASK	(0xffffffff << 0)
+#define SPIDTR_8BIT_MASK	GENMASK(7, 0)
+#define SPIDTR_16BIT_MASK	GENMASK(15, 0)
+#define SPIDTR_32BIT_MASK	GENMASK(31, 0)
 
 /* SPI Data Receive Register (spidrr), [1] p12, [2] p12 */
-#define SPIDRR_8BIT_MASK	(0xff << 0)
-#define SPIDRR_16BIT_MASK	(0xffff << 0)
-#define SPIDRR_32BIT_MASK	(0xffffffff << 0)
+#define SPIDRR_8BIT_MASK	GENMASK(7, 0)
+#define SPIDRR_16BIT_MASK	GENMASK(15, 0)
+#define SPIDRR_32BIT_MASK	GENMASK(31, 0)
 
 /* SPI Slave Select Register (spissr), [1] p13, [2] p13 */
 #define SPISSR_MASK(cs)		(1 << (cs))

@@ -75,7 +75,7 @@
 #define XILSPI_SPICR_DFLT_OFF	(SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS)
 
 #ifndef CONFIG_XILINX_SPI_IDLE_VAL
-#define CONFIG_XILINX_SPI_IDLE_VAL	0xff
+#define CONFIG_XILINX_SPI_IDLE_VAL	GENMASK(7, 0)
 #endif
 
 #ifndef CONFIG_SYS_XILINX_SPI_LIST

Signature · 1 line

1.9.1